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drm/i2c: tda998x: avoid racy access to mode clock
[linux-2.6-block.git] / drivers / gpu / drm / i2c / tda998x_drv.c
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e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
c707c361 18#include <linux/component.h>
893c3e53 19#include <linux/hdmi.h>
e7792ce2 20#include <linux/module.h>
12473b7d 21#include <linux/irq.h>
f0b33b28 22#include <sound/asoundef.h>
7e567624 23#include <sound/hdmi-codec.h>
e7792ce2
RC		 24
25#include <drm/drmP.h>
9736e988 26#include <drm/drm_atomic_helper.h>
e7792ce2 27#include <drm/drm_crtc_helper.h>
e7792ce2 28#include <drm/drm_edid.h>
5dbcf319 29#include <drm/drm_of.h>
c4c11dd1 30#include <drm/i2c/tda998x.h>
e7792ce2
RC		 31
32#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
33
7e567624
JS		 34struct tda998x_audio_port {
35 u8 format; /* AFMT_xxx */
36 u8 config; /* AP value */
37};
38
e7792ce2
RC		 39struct tda998x_priv {
40 struct i2c_client *cec;
2f7f730a 41 struct i2c_client *hdmi;
ed9a8426 42 struct mutex mutex;
e66e03ab
RK		 43 u16 rev;
44 u8 current_page;
e7792ce2 45 int dpms;
c4c11dd1 46 bool is_hdmi_sink;
5e74c22c
RK		 47 u8 vip_cntrl_0;
48 u8 vip_cntrl_1;
49 u8 vip_cntrl_2;
319e658c 50 unsigned long tmds_clock;
95db3b25 51 struct tda998x_audio_params audio_params;
12473b7d 52
7e567624
JS		 53 struct platform_device *audio_pdev;
54 struct mutex audio_mutex;
55
12473b7d
JFM		 56 wait_queue_head_t wq_edid;
57 volatile int wq_edid_wait;
0fc6f44d
RK		 58
59 struct work_struct detect_work;
60 struct timer_list edid_delay_timer;
61 wait_queue_head_t edid_delay_waitq;
62 bool edid_delay_active;
78e401f9
RK		 63
64 struct drm_encoder encoder;
eed64b59 65 struct drm_connector connector;
7e567624
JS		 66
67 struct tda998x_audio_port audio_port[2];
e7792ce2
RC		 68};
69
9525c4dd
RK		 70#define conn_to_tda998x_priv(x) \
71 container_of(x, struct tda998x_priv, connector)
72
73#define enc_to_tda998x_priv(x) \
74 container_of(x, struct tda998x_priv, encoder)
75
e7792ce2
RC		 76/* The TDA9988 series of devices use a paged register scheme.. to simplify
77 * things we encode the page # in upper bits of the register #. To read/
78 * write a given register, we need to make sure CURPAGE register is set
79 * appropriately. Which implies reads/writes are not atomic. Fun!
80 */
81
82#define REG(page, addr) (((page) << 8) | (addr))
83#define REG2ADDR(reg) ((reg) & 0xff)
84#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
85
86#define REG_CURPAGE 0xff /* write */
87
88
89/* Page 00h: General Control */
90#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
91#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
92# define MAIN_CNTRL0_SR (1 << 0)
93# define MAIN_CNTRL0_DECS (1 << 1)
94# define MAIN_CNTRL0_DEHS (1 << 2)
95# define MAIN_CNTRL0_CECS (1 << 3)
96# define MAIN_CNTRL0_CEHS (1 << 4)
97# define MAIN_CNTRL0_SCALER (1 << 7)
98#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
99#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
100# define SOFTRESET_AUDIO (1 << 0)
101# define SOFTRESET_I2C_MASTER (1 << 1)
102#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
103#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
104#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
105# define I2C_MASTER_DIS_MM (1 << 0)
106# define I2C_MASTER_DIS_FILT (1 << 1)
107# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1
RK		 108#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
109# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 110#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
111#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
112#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
113# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 114#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 115#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
116#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
117#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
118#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
119#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
120# define VIP_CNTRL_0_MIRR_A (1 << 7)
121# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
122# define VIP_CNTRL_0_MIRR_B (1 << 3)
123# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
124#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
125# define VIP_CNTRL_1_MIRR_C (1 << 7)
126# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
127# define VIP_CNTRL_1_MIRR_D (1 << 3)
128# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
129#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
130# define VIP_CNTRL_2_MIRR_E (1 << 7)
131# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
132# define VIP_CNTRL_2_MIRR_F (1 << 3)
133# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
134#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
135# define VIP_CNTRL_3_X_TGL (1 << 0)
136# define VIP_CNTRL_3_H_TGL (1 << 1)
137# define VIP_CNTRL_3_V_TGL (1 << 2)
138# define VIP_CNTRL_3_EMB (1 << 3)
139# define VIP_CNTRL_3_SYNC_DE (1 << 4)
140# define VIP_CNTRL_3_SYNC_HS (1 << 5)
141# define VIP_CNTRL_3_DE_INT (1 << 6)
142# define VIP_CNTRL_3_EDGE (1 << 7)
143#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
144# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
145# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
146# define VIP_CNTRL_4_CCIR656 (1 << 4)
147# define VIP_CNTRL_4_656_ALT (1 << 5)
148# define VIP_CNTRL_4_TST_656 (1 << 6)
149# define VIP_CNTRL_4_TST_PAT (1 << 7)
150#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
151# define VIP_CNTRL_5_CKCASE (1 << 0)
152# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 153#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
10df1a95
JFM		 154# define MUX_AP_SELECT_I2S 0x64
155# define MUX_AP_SELECT_SPDIF 0x40
bcb2481d 156#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 157#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
158# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
159# define MAT_CONTRL_MAT_BP (1 << 2)
160#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
161#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
162#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
163#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
164#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
165#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
166#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
167#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
168#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
169#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
170#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
171#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
172#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
173#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
174#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
175#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
176#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 177#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
178#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 179#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
180#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 181#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
182#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 183#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
184#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
185#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
186#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
187#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
188#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
189#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
190#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
191#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
192#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 193#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
194#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
195#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
196#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 197#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
198#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
199#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
200#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
201#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 202# define TBG_CNTRL_0_TOP_TGL (1 << 0)
203# define TBG_CNTRL_0_TOP_SEL (1 << 1)
204# define TBG_CNTRL_0_DE_EXT (1 << 2)
205# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 206# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
207# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
208# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
209#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 210# define TBG_CNTRL_1_H_TGL (1 << 0)
211# define TBG_CNTRL_1_V_TGL (1 << 1)
212# define TBG_CNTRL_1_TGL_EN (1 << 2)
213# define TBG_CNTRL_1_X_EXT (1 << 3)
214# define TBG_CNTRL_1_H_EXT (1 << 4)
215# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 216# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
217#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
218#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
219# define HVF_CNTRL_0_SM (1 << 7)
220# define HVF_CNTRL_0_RWB (1 << 6)
221# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
222# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
223#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
224# define HVF_CNTRL_1_FOR (1 << 0)
225# define HVF_CNTRL_1_YUVBLK (1 << 1)
226# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
227# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
228# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
229#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 230#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
231# define I2S_FORMAT(x) (((x) & 3) << 0)
232#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
10df1a95
JFM		 233# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
234# define AIP_CLKSEL_AIP_I2S (1 << 3)
235# define AIP_CLKSEL_FS_ACLK (0 << 0)
236# define AIP_CLKSEL_FS_MCLK (1 << 0)
237# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
e7792ce2
RC		 238
239/* Page 02h: PLL settings */
240#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
241# define PLL_SERIAL_1_SRL_FDN (1 << 0)
242# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
243# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
244#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 245# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 246# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
247#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
248# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
249# define PLL_SERIAL_3_SRL_DE (1 << 2)
250# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
251#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
252#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
253#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
254#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
255#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
256#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
257#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
258#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
259#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 260# define AUDIO_DIV_SERCLK_1 0
261# define AUDIO_DIV_SERCLK_2 1
262# define AUDIO_DIV_SERCLK_4 2
263# define AUDIO_DIV_SERCLK_8 3
264# define AUDIO_DIV_SERCLK_16 4
265# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 266#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
267# define SEL_CLK_SEL_CLK1 (1 << 0)
268# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
269# define SEL_CLK_ENA_SC_CLK (1 << 3)
270#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
271
272
273/* Page 09h: EDID Control */
274#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
275/* next 127 successive registers are the EDID block */
276#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
277#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
278#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
279#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
280#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
281
282
283/* Page 10h: information frames and packets */
c4c11dd1
RK		 284#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
285#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
286#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
287#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
288#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 289
290
291/* Page 11h: audio settings and content info packets */
292#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
293# define AIP_CNTRL_0_RST_FIFO (1 << 0)
294# define AIP_CNTRL_0_SWAP (1 << 1)
295# define AIP_CNTRL_0_LAYOUT (1 << 2)
296# define AIP_CNTRL_0_ACR_MAN (1 << 5)
297# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 298#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
299# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
300# define CA_I2S_HBR_CHSTAT (1 << 6)
301#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
302#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
303#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
304#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
305#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
306#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
307#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
308#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
309# define CTS_N_K(x) (((x) & 7) << 0)
310# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 311#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
312# define ENC_CNTRL_RST_ENC (1 << 0)
313# define ENC_CNTRL_RST_SEL (1 << 1)
314# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 315#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
316# define DIP_FLAGS_ACR (1 << 0)
317# define DIP_FLAGS_GC (1 << 1)
318#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
319# define DIP_IF_FLAGS_IF1 (1 << 1)
320# define DIP_IF_FLAGS_IF2 (1 << 2)
321# define DIP_IF_FLAGS_IF3 (1 << 3)
322# define DIP_IF_FLAGS_IF4 (1 << 4)
323# define DIP_IF_FLAGS_IF5 (1 << 5)
324#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 325
326
327/* Page 12h: HDCP and OTP */
328#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 329#define REG_TX4 REG(0x12, 0x9b) /* read/write */
330# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 331#define REG_TX33 REG(0x12, 0xb8) /* read/write */
332# define TX33_HDMI (1 << 1)
333
334
335/* Page 13h: Gamut related metadata packets */
336
337
338
339/* CEC registers: (not paged)
340 */
12473b7d
JFM		 341#define REG_CEC_INTSTATUS 0xee /* read */
342# define CEC_INTSTATUS_CEC (1 << 0)
343# define CEC_INTSTATUS_HDMI (1 << 1)
e7792ce2
RC		 344#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
345# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
346# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
347# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
348# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
12473b7d
JFM		 349#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
350#define REG_CEC_RXSHPDINT 0xfd /* read */
ec5d3e83
RK		 351# define CEC_RXSHPDINT_RXSENS BIT(0)
352# define CEC_RXSHPDINT_HPD BIT(1)
e7792ce2
RC		 353#define REG_CEC_RXSHPDLEV 0xfe /* read */
354# define CEC_RXSHPDLEV_RXSENS (1 << 0)
355# define CEC_RXSHPDLEV_HPD (1 << 1)
356
357#define REG_CEC_ENAMODS 0xff /* read/write */
358# define CEC_ENAMODS_DIS_FRO (1 << 6)
359# define CEC_ENAMODS_DIS_CCLK (1 << 5)
360# define CEC_ENAMODS_EN_RXSENS (1 << 2)
361# define CEC_ENAMODS_EN_HDMI (1 << 1)
362# define CEC_ENAMODS_EN_CEC (1 << 0)
363
364
365/* Device versions: */
366#define TDA9989N2 0x0101
367#define TDA19989 0x0201
368#define TDA19989N2 0x0202
369#define TDA19988 0x0301
370
371static void
e66e03ab 372cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
e7792ce2 373{
2f7f730a 374 struct i2c_client *client = priv->cec;
e66e03ab 375 u8 buf[] = {addr, val};
e7792ce2
RC		 376 int ret;
377
704d63f5 378 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 379 if (ret < 0)
380 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
381}
382
e66e03ab
RK		 383static u8
384cec_read(struct tda998x_priv *priv, u8 addr)
e7792ce2 385{
2f7f730a 386 struct i2c_client *client = priv->cec;
e66e03ab 387 u8 val;
e7792ce2
RC		 388 int ret;
389
390 ret = i2c_master_send(client, &addr, sizeof(addr));
391 if (ret < 0)
392 goto fail;
393
394 ret = i2c_master_recv(client, &val, sizeof(val));
395 if (ret < 0)
396 goto fail;
397
398 return val;
399
400fail:
401 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
402 return 0;
403}
404
7d2eadc9 405static int
e66e03ab 406set_page(struct tda998x_priv *priv, u16 reg)
e7792ce2 407{
e7792ce2 408 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 409 struct i2c_client *client = priv->hdmi;
e66e03ab 410 u8 buf[] = {
e7792ce2
RC		 411 REG_CURPAGE, REG2PAGE(reg)
412 };
413 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 414 if (ret < 0) {
288ffc73 415 dev_err(&client->dev, "%s %04x err %d\n", __func__,
704d63f5 416 reg, ret);
7d2eadc9
JFM		 417 return ret;
418 }
e7792ce2
RC		 419
420 priv->current_page = REG2PAGE(reg);
421 }
7d2eadc9 422 return 0;
e7792ce2
RC		 423}
424
425static int
e66e03ab 426reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
e7792ce2 427{
2f7f730a 428 struct i2c_client *client = priv->hdmi;
e66e03ab 429 u8 addr = REG2ADDR(reg);
e7792ce2
RC		 430 int ret;
431
ed9a8426 432 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 433 ret = set_page(priv, reg);
434 if (ret < 0)
ed9a8426 435 goto out;
e7792ce2
RC		 436
437 ret = i2c_master_send(client, &addr, sizeof(addr));
438 if (ret < 0)
439 goto fail;
440
441 ret = i2c_master_recv(client, buf, cnt);
442 if (ret < 0)
443 goto fail;
444
ed9a8426 445 goto out;
e7792ce2
RC		 446
447fail:
448 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
ed9a8426
JFM		 449out:
450 mutex_unlock(&priv->mutex);
e7792ce2
RC		 451 return ret;
452}
453
c4c11dd1 454static void
e66e03ab 455reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
c4c11dd1 456{
2f7f730a 457 struct i2c_client *client = priv->hdmi;
e66e03ab 458 u8 buf[cnt+1];
c4c11dd1
RK		 459 int ret;
460
461 buf[0] = REG2ADDR(reg);
462 memcpy(&buf[1], p, cnt);
463
ed9a8426 464 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 465 ret = set_page(priv, reg);
466 if (ret < 0)
ed9a8426 467 goto out;
c4c11dd1
RK		 468
469 ret = i2c_master_send(client, buf, cnt + 1);
470 if (ret < 0)
471 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 472out:
473 mutex_unlock(&priv->mutex);
c4c11dd1
RK		 474}
475
7d2eadc9 476static int
e66e03ab 477reg_read(struct tda998x_priv *priv, u16 reg)
e7792ce2 478{
e66e03ab 479 u8 val = 0;
7d2eadc9
JFM		 480 int ret;
481
482 ret = reg_read_range(priv, reg, &val, sizeof(val));
483 if (ret < 0)
484 return ret;
e7792ce2
RC		 485 return val;
486}
487
488static void
e66e03ab 489reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 490{
2f7f730a 491 struct i2c_client *client = priv->hdmi;
e66e03ab 492 u8 buf[] = {REG2ADDR(reg), val};
e7792ce2
RC		 493 int ret;
494
ed9a8426 495 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 496 ret = set_page(priv, reg);
497 if (ret < 0)
ed9a8426 498 goto out;
e7792ce2 499
704d63f5 500 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 501 if (ret < 0)
502 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 503out:
504 mutex_unlock(&priv->mutex);
e7792ce2
RC		 505}
506
507static void
e66e03ab 508reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
e7792ce2 509{
2f7f730a 510 struct i2c_client *client = priv->hdmi;
e66e03ab 511 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
e7792ce2
RC		 512 int ret;
513
ed9a8426 514 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 515 ret = set_page(priv, reg);
516 if (ret < 0)
ed9a8426 517 goto out;
e7792ce2 518
704d63f5 519 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 520 if (ret < 0)
521 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 522out:
523 mutex_unlock(&priv->mutex);
e7792ce2
RC		 524}
525
526static void
e66e03ab 527reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 528{
7d2eadc9
JFM		 529 int old_val;
530
531 old_val = reg_read(priv, reg);
532 if (old_val >= 0)
533 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 534}
535
536static void
e66e03ab 537reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 538{
7d2eadc9
JFM		 539 int old_val;
540
541 old_val = reg_read(priv, reg);
542 if (old_val >= 0)
543 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 544}
545
546static void
2f7f730a 547tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 548{
549 /* reset audio and i2c master: */
81b53a16 550 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 551 msleep(50);
81b53a16 552 reg_write(priv, REG_SOFTRESET, 0);
e7792ce2
RC		 553 msleep(50);
554
555 /* reset transmitter: */
2f7f730a
JFM		 556 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
557 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 558
559 /* PLL registers common configuration */
2f7f730a
JFM		 560 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
561 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
562 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
563 reg_write(priv, REG_SERIALIZER, 0x00);
564 reg_write(priv, REG_BUFFER_OUT, 0x00);
565 reg_write(priv, REG_PLL_SCG1, 0x00);
566 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
567 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
568 reg_write(priv, REG_PLL_SCGN1, 0xfa);
569 reg_write(priv, REG_PLL_SCGN2, 0x00);
570 reg_write(priv, REG_PLL_SCGR1, 0x5b);
571 reg_write(priv, REG_PLL_SCGR2, 0x00);
572 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 573
574 /* Write the default value MUX register */
2f7f730a 575 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 576}
577
0fc6f44d
RK		 578/*
579 * The TDA998x has a problem when trying to read the EDID close to a
580 * HPD assertion: it needs a delay of 100ms to avoid timing out while
581 * trying to read EDID data.
582 *
583 * However, tda998x_encoder_get_modes() may be called at any moment
9525c4dd 584 * after tda998x_connector_detect() indicates that we are connected, so
0fc6f44d
RK		 585 * we need to delay probing modes in tda998x_encoder_get_modes() after
586 * we have seen a HPD inactive->active transition. This code implements
587 * that delay.
588 */
589static void tda998x_edid_delay_done(unsigned long data)
590{
591 struct tda998x_priv *priv = (struct tda998x_priv *)data;
592
593 priv->edid_delay_active = false;
594 wake_up(&priv->edid_delay_waitq);
595 schedule_work(&priv->detect_work);
596}
597
598static void tda998x_edid_delay_start(struct tda998x_priv *priv)
599{
600 priv->edid_delay_active = true;
601 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
602}
603
604static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
605{
606 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
607}
608
609/*
610 * We need to run the KMS hotplug event helper outside of our threaded
611 * interrupt routine as this can call back into our get_modes method,
612 * which will want to make use of interrupts.
613 */
614static void tda998x_detect_work(struct work_struct *work)
6833d26e 615{
6833d26e 616 struct tda998x_priv *priv =
0fc6f44d 617 container_of(work, struct tda998x_priv, detect_work);
78e401f9 618 struct drm_device *dev = priv->encoder.dev;
6833d26e 619
0fc6f44d
RK		 620 if (dev)
621 drm_kms_helper_hotplug_event(dev);
6833d26e
JFM		 622}
623
12473b7d
JFM		 624/*
625 * only 2 interrupts may occur: screen plug/unplug and EDID read
626 */
627static irqreturn_t tda998x_irq_thread(int irq, void *data)
628{
629 struct tda998x_priv *priv = data;
630 u8 sta, cec, lvl, flag0, flag1, flag2;
f84a97d4 631 bool handled = false;
12473b7d 632
12473b7d
JFM		 633 sta = cec_read(priv, REG_CEC_INTSTATUS);
634 cec = cec_read(priv, REG_CEC_RXSHPDINT);
635 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
636 flag0 = reg_read(priv, REG_INT_FLAGS_0);
637 flag1 = reg_read(priv, REG_INT_FLAGS_1);
638 flag2 = reg_read(priv, REG_INT_FLAGS_2);
639 DRM_DEBUG_DRIVER(
640 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
641 sta, cec, lvl, flag0, flag1, flag2);
ec5d3e83
RK		 642
643 if (cec & CEC_RXSHPDINT_HPD) {
0fc6f44d
RK		 644 if (lvl & CEC_RXSHPDLEV_HPD)
645 tda998x_edid_delay_start(priv);
646 else
647 schedule_work(&priv->detect_work);
648
f84a97d4 649 handled = true;
12473b7d 650 }
ec5d3e83
RK		 651
652 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
653 priv->wq_edid_wait = 0;
654 wake_up(&priv->wq_edid);
655 handled = true;
656 }
657
f84a97d4 658 return IRQ_RETVAL(handled);
12473b7d
JFM		 659}
660
c4c11dd1 661static void
e66e03ab 662tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
96795df1 663 union hdmi_infoframe *frame)
c4c11dd1 664{
96795df1
RK		 665 u8 buf[32];
666 ssize_t len;
667
668 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
669 if (len < 0) {
670 dev_err(&priv->hdmi->dev,
671 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
672 frame->any.type, len);
673 return;
674 }
675
2f7f730a 676 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
96795df1 677 reg_write_range(priv, addr, buf, len);
2f7f730a 678 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 679}
680
95db3b25
JS		 681static int tda998x_write_aif(struct tda998x_priv *priv,
682 struct hdmi_audio_infoframe *cea)
c4c11dd1 683{
96795df1
RK		 684 union hdmi_infoframe frame;
685
95db3b25 686 frame.audio = *cea;
4a6ca1a2 687
96795df1 688 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
95db3b25
JS		 689
690 return 0;
c4c11dd1
RK		 691}
692
693static void
2f7f730a 694tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 695{
96795df1 696 union hdmi_infoframe frame;
8c7a075d 697
96795df1
RK		 698 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
699 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
8c7a075d 700
96795df1 701 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
c4c11dd1
RK		 702}
703
2f7f730a 704static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 705{
706 if (on) {
2f7f730a
JFM		 707 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
708 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
709 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 710 } else {
2f7f730a 711 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 712 }
713}
714
95db3b25 715static int
2f7f730a 716tda998x_configure_audio(struct tda998x_priv *priv,
319e658c 717 struct tda998x_audio_params *params)
c4c11dd1 718{
e66e03ab
RK		 719 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
720 u32 n;
c4c11dd1
RK		 721
722 /* Enable audio ports */
95db3b25 723 reg_write(priv, REG_ENA_AP, params->config);
c4c11dd1
RK		 724
725 /* Set audio input source */
95db3b25 726 switch (params->format) {
c4c11dd1 727 case AFMT_SPDIF:
95db3b25 728 reg_write(priv, REG_ENA_ACLK, 0);
10df1a95
JFM		 729 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
730 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
731 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
c4c11dd1 732 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1
RK		 733 break;
734
735 case AFMT_I2S:
95db3b25 736 reg_write(priv, REG_ENA_ACLK, 1);
10df1a95
JFM		 737 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
738 clksel_aip = AIP_CLKSEL_AIP_I2S;
739 clksel_fs = AIP_CLKSEL_FS_ACLK;
95db3b25
JS		 740 switch (params->sample_width) {
741 case 16:
742 cts_n = CTS_N_M(3) | CTS_N_K(1);
743 break;
744 case 18:
745 case 20:
746 case 24:
747 cts_n = CTS_N_M(3) | CTS_N_K(2);
748 break;
749 default:
750 case 32:
751 cts_n = CTS_N_M(3) | CTS_N_K(3);
752 break;
753 }
c4c11dd1 754 break;
3b28802e
DH		 755
756 default:
7e567624 757 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n");
95db3b25 758 return -EINVAL;
c4c11dd1
RK		 759 }
760
2f7f730a 761 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
a8b517e5
JFM		 762 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
763 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
2f7f730a 764 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 765
766 /*
767 * Audio input somehow depends on HDMI line rate which is
768 * related to pixclk. Testing showed that modes with pixclk
769 * >100MHz need a larger divider while <40MHz need the default.
770 * There is no detailed info in the datasheet, so we just
771 * assume 100MHz requires larger divider.
772 */
2470fecc 773 adiv = AUDIO_DIV_SERCLK_8;
319e658c 774 if (priv->tmds_clock > 100000)
2470fecc
JFM		 775 adiv++; /* AUDIO_DIV_SERCLK_16 */
776
777 /* S/PDIF asks for a larger divider */
95db3b25 778 if (params->format == AFMT_SPDIF)
2470fecc
JFM		 779 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
780
2f7f730a 781 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 782
783 /*
784 * This is the approximate value of N, which happens to be
785 * the recommended values for non-coherent clocks.
786 */
95db3b25 787 n = 128 * params->sample_rate / 1000;
c4c11dd1
RK		 788
789 /* Write the CTS and N values */
790 buf[0] = 0x44;
791 buf[1] = 0x42;
792 buf[2] = 0x01;
793 buf[3] = n;
794 buf[4] = n >> 8;
795 buf[5] = n >> 16;
2f7f730a 796 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 797
798 /* Set CTS clock reference */
2f7f730a 799 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 800
801 /* Reset CTS generator */
2f7f730a
JFM		 802 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
803 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1 804
95db3b25
JS		 805 /* Write the channel status
806 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
807 * there is a separate register for each I2S wire.
808 */
809 buf[0] = params->status[0];
810 buf[1] = params->status[1];
811 buf[2] = params->status[3];
812 buf[3] = params->status[4];
2f7f730a 813 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 814
2f7f730a 815 tda998x_audio_mute(priv, true);
73d5e253 816 msleep(20);
2f7f730a 817 tda998x_audio_mute(priv, false);
c4c11dd1 818
95db3b25 819 return tda998x_write_aif(priv, &params->cea);
c4c11dd1
RK		 820}
821
e7792ce2
RC		 822/* DRM encoder functions */
823
a8f4d4d6
RK		 824static void tda998x_encoder_set_config(struct tda998x_priv *priv,
825 const struct tda998x_encoder_params *p)
e7792ce2 826{
c4c11dd1
RK		 827 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
828 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
829 VIP_CNTRL_0_SWAP_B(p->swap_b) |
830 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
831 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
832 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
833 VIP_CNTRL_1_SWAP_D(p->swap_d) |
834 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
835 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
836 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
837 VIP_CNTRL_2_SWAP_F(p->swap_f) |
838 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
839
95db3b25 840 priv->audio_params = p->audio_params;
e7792ce2
RC		 841}
842
9525c4dd 843static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
e7792ce2 844{
9525c4dd
RK		 845 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
846
e7792ce2
RC		 847 /* we only care about on or off: */
848 if (mode != DRM_MODE_DPMS_ON)
849 mode = DRM_MODE_DPMS_OFF;
850
851 if (mode == priv->dpms)
852 return;
853
854 switch (mode) {
855 case DRM_MODE_DPMS_ON:
c4c11dd1 856 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 857 reg_write(priv, REG_ENA_VP_0, 0xff);
858 reg_write(priv, REG_ENA_VP_1, 0xff);
859 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 860 /* set muxing after enabling ports: */
2f7f730a
JFM		 861 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
862 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
863 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
e7792ce2
RC		 864 break;
865 case DRM_MODE_DPMS_OFF:
db6aaf4d 866 /* disable video ports */
2f7f730a
JFM		 867 reg_write(priv, REG_ENA_VP_0, 0x00);
868 reg_write(priv, REG_ENA_VP_1, 0x00);
869 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2
RC		 870 break;
871 }
872
873 priv->dpms = mode;
874}
875
9525c4dd
RK		 876static int tda998x_connector_mode_valid(struct drm_connector *connector,
877 struct drm_display_mode *mode)
e7792ce2 878{
e4618c46
LDA		 879 /* TDA19988 dotclock can go up to 165MHz */
880 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
881
882 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
92fbdfcd
RK		 883 return MODE_CLOCK_HIGH;
884 if (mode->htotal >= BIT(13))
885 return MODE_BAD_HVALUE;
886 if (mode->vtotal >= BIT(11))
887 return MODE_BAD_VVALUE;
e7792ce2
RC		 888 return MODE_OK;
889}
890
891static void
9525c4dd 892tda998x_encoder_mode_set(struct drm_encoder *encoder,
a8f4d4d6
RK		 893 struct drm_display_mode *mode,
894 struct drm_display_mode *adjusted_mode)
e7792ce2 895{
9525c4dd 896 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
e66e03ab
RK		 897 u16 ref_pix, ref_line, n_pix, n_line;
898 u16 hs_pix_s, hs_pix_e;
899 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
900 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
901 u16 vwin1_line_s, vwin1_line_e;
902 u16 vwin2_line_s, vwin2_line_e;
903 u16 de_pix_s, de_pix_e;
904 u8 reg, div, rep;
e7792ce2 905
088d61d1
SH		 906 /*
907 * Internally TDA998x is using ITU-R BT.656 style sync but
908 * we get VESA style sync. TDA998x is using a reference pixel
909 * relative to ITU to sync to the input frame and for output
910 * sync generation. Currently, we are using reference detection
911 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
912 * which is position of rising VS with coincident rising HS.
913 *
914 * Now there is some issues to take care of:
915 * - HDMI data islands require sync-before-active
916 * - TDA998x register values must be > 0 to be enabled
917 * - REFLINE needs an additional offset of +1
918 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
919 *
920 * So we add +1 to all horizontal and vertical register values,
921 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 922 */
088d61d1
SH		 923 n_pix = mode->htotal;
924 n_line = mode->vtotal;
925
926 hs_pix_e = mode->hsync_end - mode->hdisplay;
927 hs_pix_s = mode->hsync_start - mode->hdisplay;
928 de_pix_e = mode->htotal;
929 de_pix_s = mode->htotal - mode->hdisplay;
930 ref_pix = 3 + hs_pix_s;
931
179f1aa4
SH		 932 /*
933 * Attached LCD controllers may generate broken sync. Allow
934 * those to adjust the position of the rising VS edge by adding
935 * HSKEW to ref_pix.
936 */
937 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
938 ref_pix += adjusted_mode->hskew;
939
088d61d1
SH		 940 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
941 ref_line = 1 + mode->vsync_start - mode->vdisplay;
942 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
943 vwin1_line_e = vwin1_line_s + mode->vdisplay;
944 vs1_pix_s = vs1_pix_e = hs_pix_s;
945 vs1_line_s = mode->vsync_start - mode->vdisplay;
946 vs1_line_e = vs1_line_s +
947 mode->vsync_end - mode->vsync_start;
948 vwin2_line_s = vwin2_line_e = 0;
949 vs2_pix_s = vs2_pix_e = 0;
950 vs2_line_s = vs2_line_e = 0;
951 } else {
952 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
953 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
954 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
955 vs1_pix_s = vs1_pix_e = hs_pix_s;
956 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
957 vs1_line_e = vs1_line_s +
958 (mode->vsync_end - mode->vsync_start)/2;
959 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
960 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
961 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
962 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
963 vs2_line_e = vs2_line_s +
964 (mode->vsync_end - mode->vsync_start)/2;
965 }
e7792ce2
RC		 966
967 div = 148500 / mode->clock;
3ae471f7
JFM		 968 if (div != 0) {
969 div--;
970 if (div > 3)
971 div = 3;
972 }
e7792ce2 973
e7792ce2 974 /* mute the audio FIFO: */
2f7f730a 975 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 976
977 /* set HDMI HDCP mode off: */
81b53a16 978 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
2f7f730a
JFM		 979 reg_clear(priv, REG_TX33, TX33_HDMI);
980 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 981
e7792ce2 982 /* no pre-filter or interpolator: */
2f7f730a 983 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 984 HVF_CNTRL_0_INTPOL(0));
2f7f730a
JFM		 985 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
986 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 987 VIP_CNTRL_4_BLC(0));
e7792ce2 988
2f7f730a 989 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
a8b517e5
JFM		 990 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
991 PLL_SERIAL_3_SRL_DE);
2f7f730a
JFM		 992 reg_write(priv, REG_SERIALIZER, 0);
993 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 994
995 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
996 rep = 0;
2f7f730a
JFM		 997 reg_write(priv, REG_RPT_CNTRL, 0);
998 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 999 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1000
2f7f730a 1001 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 1002 PLL_SERIAL_2_SRL_PR(rep));
1003
e7792ce2 1004 /* set color matrix bypass flag: */
81b53a16
JFM		 1005 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1006 MAT_CONTRL_MAT_SC(1));
e7792ce2
RC		 1007
1008 /* set BIAS tmds value: */
2f7f730a 1009 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 1010
088d61d1
SH		 1011 /*
1012 * Sync on rising HSYNC/VSYNC
1013 */
81b53a16 1014 reg = VIP_CNTRL_3_SYNC_HS;
088d61d1
SH		 1015
1016 /*
1017 * TDA19988 requires high-active sync at input stage,
1018 * so invert low-active sync provided by master encoder here
1019 */
1020 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
81b53a16 1021 reg |= VIP_CNTRL_3_H_TGL;
e7792ce2 1022 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
81b53a16
JFM		 1023 reg |= VIP_CNTRL_3_V_TGL;
1024 reg_write(priv, REG_VIP_CNTRL_3, reg);
2f7f730a
JFM		 1025
1026 reg_write(priv, REG_VIDFORMAT, 0x00);
1027 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1028 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1029 reg_write16(priv, REG_NPIX_MSB, n_pix);
1030 reg_write16(priv, REG_NLINE_MSB, n_line);
1031 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1032 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1033 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1034 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1035 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1036 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1037 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1038 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1039 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1040 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1041 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1042 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1043 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1044 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1045 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1046 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 1047
1048 if (priv->rev == TDA19988) {
1049 /* let incoming pixels fill the active space (if any) */
2f7f730a 1050 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 1051 }
1052
81b53a16
JFM		 1053 /*
1054 * Always generate sync polarity relative to input sync and
1055 * revert input stage toggled sync at output stage
1056 */
1057 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1058 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1059 reg |= TBG_CNTRL_1_H_TGL;
1060 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1061 reg |= TBG_CNTRL_1_V_TGL;
1062 reg_write(priv, REG_TBG_CNTRL_1, reg);
1063
e7792ce2 1064 /* must be last register set: */
81b53a16 1065 reg_write(priv, REG_TBG_CNTRL_0, 0);
c4c11dd1 1066
319e658c
RK		 1067 mutex_lock(&priv->audio_mutex);
1068
1069 priv->tmds_clock = adjusted_mode->clock;
1070
c4c11dd1
RK		 1071 /* Only setup the info frames if the sink is HDMI */
1072 if (priv->is_hdmi_sink) {
1073 /* We need to turn HDMI HDCP stuff on to get audio through */
81b53a16
JFM		 1074 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1075 reg_write(priv, REG_TBG_CNTRL_1, reg);
2f7f730a
JFM		 1076 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1077 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 1078
2f7f730a 1079 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1 1080
6d30c0f7 1081 if (priv->audio_params.format != AFMT_UNUSED)
319e658c 1082 tda998x_configure_audio(priv, &priv->audio_params);
c4c11dd1 1083 }
319e658c
RK		 1084
1085 mutex_unlock(&priv->audio_mutex);
e7792ce2
RC		 1086}
1087
1088static enum drm_connector_status
9525c4dd 1089tda998x_connector_detect(struct drm_connector *connector, bool force)
e7792ce2 1090{
9525c4dd 1091 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
e66e03ab 1092 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
2f7f730a 1093
e7792ce2
RC		 1094 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1095 connector_status_disconnected;
1096}
1097
07259f8b 1098static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
e7792ce2 1099{
07259f8b 1100 struct tda998x_priv *priv = data;
e66e03ab 1101 u8 offset, segptr;
e7792ce2
RC		 1102 int ret, i;
1103
e7792ce2
RC		 1104 offset = (blk & 1) ? 128 : 0;
1105 segptr = blk / 2;
1106
2f7f730a
JFM		 1107 reg_write(priv, REG_DDC_ADDR, 0xa0);
1108 reg_write(priv, REG_DDC_OFFS, offset);
1109 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1110 reg_write(priv, REG_DDC_SEGM, segptr);
e7792ce2
RC		 1111
1112 /* enable reading EDID: */
12473b7d 1113 priv->wq_edid_wait = 1;
2f7f730a 1114 reg_write(priv, REG_EDID_CTRL, 0x1);
e7792ce2
RC		 1115
1116 /* flag must be cleared by sw: */
2f7f730a 1117 reg_write(priv, REG_EDID_CTRL, 0x0);
e7792ce2
RC		 1118
1119 /* wait for block read to complete: */
12473b7d
JFM		 1120 if (priv->hdmi->irq) {
1121 i = wait_event_timeout(priv->wq_edid,
1122 !priv->wq_edid_wait,
1123 msecs_to_jiffies(100));
1124 if (i < 0) {
5e7fe2fe 1125 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
12473b7d
JFM		 1126 return i;
1127 }
1128 } else {
713456db
RK		 1129 for (i = 100; i > 0; i--) {
1130 msleep(1);
12473b7d
JFM		 1131 ret = reg_read(priv, REG_INT_FLAGS_2);
1132 if (ret < 0)
1133 return ret;
1134 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1135 break;
1136 }
e7792ce2
RC		 1137 }
1138
12473b7d 1139 if (i == 0) {
5e7fe2fe 1140 dev_err(&priv->hdmi->dev, "read edid timeout\n");
e7792ce2 1141 return -ETIMEDOUT;
12473b7d 1142 }
e7792ce2 1143
07259f8b
LP		 1144 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1145 if (ret != length) {
5e7fe2fe
RK		 1146 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1147 blk, ret);
e7792ce2
RC		 1148 return ret;
1149 }
1150
e7792ce2
RC		 1151 return 0;
1152}
1153
9525c4dd 1154static int tda998x_connector_get_modes(struct drm_connector *connector)
e7792ce2 1155{
9525c4dd 1156 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
07259f8b
LP		 1157 struct edid *edid;
1158 int n;
e7792ce2 1159
0fc6f44d
RK		 1160 /*
1161 * If we get killed while waiting for the HPD timeout, return
1162 * no modes found: we are not in a restartable path, so we
1163 * can't handle signals gracefully.
1164 */
1165 if (tda998x_edid_delay_wait(priv))
1166 return 0;
1167
063b472f 1168 if (priv->rev == TDA19988)
2f7f730a 1169 reg_clear(priv, REG_TX4, TX4_PD_RAM);
063b472f 1170
07259f8b 1171 edid = drm_do_get_edid(connector, read_edid_block, priv);
e7792ce2 1172
063b472f 1173 if (priv->rev == TDA19988)
2f7f730a 1174 reg_set(priv, REG_TX4, TX4_PD_RAM);
063b472f 1175
07259f8b
LP		 1176 if (!edid) {
1177 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1178 return 0;
e7792ce2
RC		 1179 }
1180
07259f8b
LP		 1181 drm_mode_connector_update_edid_property(connector, edid);
1182 n = drm_add_edid_modes(connector, edid);
1183 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
7e567624
JS		 1184 drm_edid_to_eld(connector, edid);
1185
07259f8b
LP		 1186 kfree(edid);
1187
e7792ce2
RC		 1188 return n;
1189}
1190
a8f4d4d6
RK		 1191static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1192 struct drm_connector *connector)
e7792ce2 1193{
12473b7d
JFM		 1194 if (priv->hdmi->irq)
1195 connector->polled = DRM_CONNECTOR_POLL_HPD;
1196 else
1197 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1198 DRM_CONNECTOR_POLL_DISCONNECT;
e7792ce2
RC		 1199}
1200
a8f4d4d6 1201static void tda998x_destroy(struct tda998x_priv *priv)
e7792ce2 1202{
12473b7d
JFM		 1203 /* disable all IRQs and free the IRQ handler */
1204 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1205 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
0fc6f44d 1206
7e567624
JS		 1207 if (priv->audio_pdev)
1208 platform_device_unregister(priv->audio_pdev);
1209
0fc6f44d 1210 if (priv->hdmi->irq)
12473b7d 1211 free_irq(priv->hdmi->irq, priv);
0fc6f44d
RK		 1212
1213 del_timer_sync(&priv->edid_delay_timer);
1214 cancel_work_sync(&priv->detect_work);
12473b7d 1215
89fc8686 1216 i2c_unregister_device(priv->cec);
a8f4d4d6
RK		 1217}
1218
7e567624
JS		 1219static int tda998x_audio_hw_params(struct device *dev, void *data,
1220 struct hdmi_codec_daifmt *daifmt,
1221 struct hdmi_codec_params *params)
1222{
1223 struct tda998x_priv *priv = dev_get_drvdata(dev);
1224 int i, ret;
1225 struct tda998x_audio_params audio = {
1226 .sample_width = params->sample_width,
1227 .sample_rate = params->sample_rate,
1228 .cea = params->cea,
1229 };
1230
7e567624
JS		 1231 memcpy(audio.status, params->iec.status,
1232 min(sizeof(audio.status), sizeof(params->iec.status)));
1233
1234 switch (daifmt->fmt) {
1235 case HDMI_I2S:
1236 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
1237 daifmt->bit_clk_master || daifmt->frame_clk_master) {
1238 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1239 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1240 daifmt->bit_clk_master,
1241 daifmt->frame_clk_master);
1242 return -EINVAL;
1243 }
1244 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
1245 if (priv->audio_port[i].format == AFMT_I2S)
1246 audio.config = priv->audio_port[i].config;
1247 audio.format = AFMT_I2S;
1248 break;
1249 case HDMI_SPDIF:
1250 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
1251 if (priv->audio_port[i].format == AFMT_SPDIF)
1252 audio.config = priv->audio_port[i].config;
1253 audio.format = AFMT_SPDIF;
1254 break;
1255 default:
1256 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1257 return -EINVAL;
1258 }
1259
1260 if (audio.config == 0) {
1261 dev_err(dev, "%s: No audio configutation found\n", __func__);
1262 return -EINVAL;
1263 }
1264
1265 mutex_lock(&priv->audio_mutex);
319e658c 1266 ret = tda998x_configure_audio(priv, &audio);
7e567624
JS		 1267
1268 if (ret == 0)
1269 priv->audio_params = audio;
1270 mutex_unlock(&priv->audio_mutex);
1271
1272 return ret;
1273}
1274
1275static void tda998x_audio_shutdown(struct device *dev, void *data)
1276{
1277 struct tda998x_priv *priv = dev_get_drvdata(dev);
1278
1279 mutex_lock(&priv->audio_mutex);
1280
1281 reg_write(priv, REG_ENA_AP, 0);
1282
1283 priv->audio_params.format = AFMT_UNUSED;
1284
1285 mutex_unlock(&priv->audio_mutex);
1286}
1287
1288int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
1289{
1290 struct tda998x_priv *priv = dev_get_drvdata(dev);
1291
1292 mutex_lock(&priv->audio_mutex);
1293
1294 tda998x_audio_mute(priv, enable);
1295
1296 mutex_unlock(&priv->audio_mutex);
1297 return 0;
1298}
1299
1300static int tda998x_audio_get_eld(struct device *dev, void *data,
1301 uint8_t *buf, size_t len)
1302{
1303 struct tda998x_priv *priv = dev_get_drvdata(dev);
1304 struct drm_mode_config *config = &priv->encoder.dev->mode_config;
1305 struct drm_connector *connector;
1306 int ret = -ENODEV;
1307
1308 mutex_lock(&config->mutex);
1309 list_for_each_entry(connector, &config->connector_list, head) {
1310 if (&priv->encoder == connector->encoder) {
1311 memcpy(buf, connector->eld,
1312 min(sizeof(connector->eld), len));
1313 ret = 0;
1314 }
1315 }
1316 mutex_unlock(&config->mutex);
1317
1318 return ret;
1319}
1320
1321static const struct hdmi_codec_ops audio_codec_ops = {
1322 .hw_params = tda998x_audio_hw_params,
1323 .audio_shutdown = tda998x_audio_shutdown,
1324 .digital_mute = tda998x_audio_digital_mute,
1325 .get_eld = tda998x_audio_get_eld,
1326};
1327
1328static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1329 struct device *dev)
1330{
1331 struct hdmi_codec_pdata codec_data = {
1332 .ops = &audio_codec_ops,
1333 .max_i2s_channels = 2,
1334 };
1335 int i;
1336
1337 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) {
1338 if (priv->audio_port[i].format == AFMT_I2S &&
1339 priv->audio_port[i].config != 0)
1340 codec_data.i2s = 1;
1341 if (priv->audio_port[i].format == AFMT_SPDIF &&
1342 priv->audio_port[i].config != 0)
1343 codec_data.spdif = 1;
1344 }
1345
1346 priv->audio_pdev = platform_device_register_data(
1347 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1348 &codec_data, sizeof(codec_data));
1349
1350 return PTR_ERR_OR_ZERO(priv->audio_pdev);
1351}
1352
e7792ce2
RC		 1353/* I2C driver functions */
1354
7e567624
JS		 1355static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1356 struct device_node *np)
1357{
1358 const u32 *port_data;
1359 u32 size;
1360 int i;
1361
1362 port_data = of_get_property(np, "audio-ports", &size);
1363 if (!port_data)
1364 return 0;
1365
1366 size /= sizeof(u32);
1367 if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) {
1368 dev_err(&priv->hdmi->dev,
1369 "Bad number of elements in audio-ports dt-property\n");
1370 return -EINVAL;
1371 }
1372
1373 size /= 2;
1374
1375 for (i = 0; i < size; i++) {
1376 u8 afmt = be32_to_cpup(&port_data[2*i]);
1377 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1378
1379 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) {
1380 dev_err(&priv->hdmi->dev,
1381 "Bad audio format %u\n", afmt);
1382 return -EINVAL;
1383 }
1384
1385 priv->audio_port[i].format = afmt;
1386 priv->audio_port[i].config = ena_ap;
1387 }
1388
1389 if (priv->audio_port[0].format == priv->audio_port[1].format) {
1390 dev_err(&priv->hdmi->dev,
1391 "There can only be on I2S port and one SPDIF port\n");
1392 return -EINVAL;
1393 }
1394 return 0;
1395}
1396
a8f4d4d6 1397static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
e7792ce2 1398{
0d44ea19
JFM		 1399 struct device_node *np = client->dev.of_node;
1400 u32 video;
fb7544d7 1401 int rev_lo, rev_hi, ret;
cfe38757 1402 unsigned short cec_addr;
e7792ce2 1403
ba300c17
RK		 1404 mutex_init(&priv->audio_mutex); /* Protect access from audio thread */
1405
5e74c22c
RK		 1406 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1407 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1408 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1409
2eb4c7b1 1410 priv->current_page = 0xff;
2f7f730a 1411 priv->hdmi = client;
cfe38757
AJ		 1412 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1413 cec_addr = 0x34 + (client->addr & 0x03);
1414 priv->cec = i2c_new_dummy(client->adapter, cec_addr);
a8f4d4d6 1415 if (!priv->cec)
6ae668cc 1416 return -ENODEV;
12473b7d 1417
e7792ce2
RC		 1418 priv->dpms = DRM_MODE_DPMS_OFF;
1419
ed9a8426 1420 mutex_init(&priv->mutex); /* protect the page access */
0fc6f44d
RK		 1421 init_waitqueue_head(&priv->edid_delay_waitq);
1422 setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1423 (unsigned long)priv);
1424 INIT_WORK(&priv->detect_work, tda998x_detect_work);
ed9a8426 1425
e7792ce2 1426 /* wake up the device: */
2f7f730a 1427 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1428 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1429
2f7f730a 1430 tda998x_reset(priv);
e7792ce2
RC		 1431
1432 /* read version: */
fb7544d7
RK		 1433 rev_lo = reg_read(priv, REG_VERSION_LSB);
1434 rev_hi = reg_read(priv, REG_VERSION_MSB);
1435 if (rev_lo < 0 || rev_hi < 0) {
1436 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1437 goto fail;
fb7544d7
RK		 1438 }
1439
1440 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1441
1442 /* mask off feature bits: */
1443 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1444
1445 switch (priv->rev) {
b728fab7
JFM		 1446 case TDA9989N2:
1447 dev_info(&client->dev, "found TDA9989 n2");
1448 break;
1449 case TDA19989:
1450 dev_info(&client->dev, "found TDA19989");
1451 break;
1452 case TDA19989N2:
1453 dev_info(&client->dev, "found TDA19989 n2");
1454 break;
1455 case TDA19988:
1456 dev_info(&client->dev, "found TDA19988");
1457 break;
e7792ce2 1458 default:
b728fab7
JFM		 1459 dev_err(&client->dev, "found unsupported device: %04x\n",
1460 priv->rev);
e7792ce2
RC		 1461 goto fail;
1462 }
1463
1464 /* after reset, enable DDC: */
2f7f730a 1465 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1466
1467 /* set clock on DDC channel: */
2f7f730a 1468 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1469
1470 /* if necessary, disable multi-master: */
1471 if (priv->rev == TDA19989)
2f7f730a 1472 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1473
2f7f730a 1474 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1475 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1476
12473b7d
JFM		 1477 /* initialize the optional IRQ */
1478 if (client->irq) {
1479 int irqf_trigger;
1480
6833d26e 1481 /* init read EDID waitqueue and HDP work */
12473b7d
JFM		 1482 init_waitqueue_head(&priv->wq_edid);
1483
1484 /* clear pending interrupts */
1485 reg_read(priv, REG_INT_FLAGS_0);
1486 reg_read(priv, REG_INT_FLAGS_1);
1487 reg_read(priv, REG_INT_FLAGS_2);
1488
1489 irqf_trigger =
1490 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1491 ret = request_threaded_irq(client->irq, NULL,
1492 tda998x_irq_thread,
1493 irqf_trigger | IRQF_ONESHOT,
1494 "tda998x", priv);
1495 if (ret) {
1496 dev_err(&client->dev,
1497 "failed to request IRQ#%u: %d\n",
1498 client->irq, ret);
1499 goto fail;
1500 }
1501
1502 /* enable HPD irq */
1503 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1504 }
1505
e4782627
JFM		 1506 /* enable EDID read irq: */
1507 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1508
0d44ea19
JFM		 1509 if (!np)
1510 return 0; /* non-DT */
1511
7e567624 1512 /* get the device tree parameters */
0d44ea19
JFM		 1513 ret = of_property_read_u32(np, "video-ports", &video);
1514 if (ret == 0) {
1515 priv->vip_cntrl_0 = video >> 16;
1516 priv->vip_cntrl_1 = video >> 8;
1517 priv->vip_cntrl_2 = video;
1518 }
1519
7e567624
JS		 1520 ret = tda998x_get_audio_ports(priv, np);
1521 if (ret)
1522 goto fail;
1523
1524 if (priv->audio_port[0].format != AFMT_UNUSED)
1525 tda998x_audio_codec_init(priv, &client->dev);
1526
1527 return 0;
e7792ce2
RC		 1528fail:
1529 /* if encoder_init fails, the encoder slave is never registered,
1530 * so cleanup here:
1531 */
1532 if (priv->cec)
1533 i2c_unregister_device(priv->cec);
e7792ce2
RC		 1534 return -ENXIO;
1535}
1536
c707c361
RK		 1537static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1538{
9525c4dd 1539 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
c707c361
RK		 1540}
1541
1542static void tda998x_encoder_commit(struct drm_encoder *encoder)
1543{
9525c4dd 1544 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
c707c361
RK		 1545}
1546
1547static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
9525c4dd 1548 .dpms = tda998x_encoder_dpms,
c707c361
RK		 1549 .prepare = tda998x_encoder_prepare,
1550 .commit = tda998x_encoder_commit,
9525c4dd 1551 .mode_set = tda998x_encoder_mode_set,
c707c361
RK		 1552};
1553
1554static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1555{
a3584f60 1556 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
c707c361 1557
a3584f60 1558 tda998x_destroy(priv);
c707c361
RK		 1559 drm_encoder_cleanup(encoder);
1560}
1561
1562static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1563 .destroy = tda998x_encoder_destroy,
1564};
1565
c707c361
RK		 1566static struct drm_encoder *
1567tda998x_connector_best_encoder(struct drm_connector *connector)
1568{
a3584f60 1569 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
c707c361 1570
a3584f60 1571 return &priv->encoder;
c707c361
RK		 1572}
1573
1574static
1575const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1576 .get_modes = tda998x_connector_get_modes,
1577 .mode_valid = tda998x_connector_mode_valid,
1578 .best_encoder = tda998x_connector_best_encoder,
1579};
1580
c707c361
RK		 1581static void tda998x_connector_destroy(struct drm_connector *connector)
1582{
c707c361
RK		 1583 drm_connector_cleanup(connector);
1584}
1585
dad82ea3
JS		 1586static int tda998x_connector_dpms(struct drm_connector *connector, int mode)
1587{
1588 if (drm_core_check_feature(connector->dev, DRIVER_ATOMIC))
1589 return drm_atomic_helper_connector_dpms(connector, mode);
1590 else
1591 return drm_helper_connector_dpms(connector, mode);
1592}
1593
c707c361 1594static const struct drm_connector_funcs tda998x_connector_funcs = {
dad82ea3 1595 .dpms = tda998x_connector_dpms,
9736e988 1596 .reset = drm_atomic_helper_connector_reset,
c707c361
RK		 1597 .fill_modes = drm_helper_probe_single_connector_modes,
1598 .detect = tda998x_connector_detect,
1599 .destroy = tda998x_connector_destroy,
9736e988
LDA		 1600 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1601 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
c707c361
RK		 1602};
1603
1604static int tda998x_bind(struct device *dev, struct device *master, void *data)
1605{
1606 struct tda998x_encoder_params *params = dev->platform_data;
1607 struct i2c_client *client = to_i2c_client(dev);
1608 struct drm_device *drm = data;
a3584f60 1609 struct tda998x_priv *priv;
e66e03ab 1610 u32 crtcs = 0;
c707c361
RK		 1611 int ret;
1612
1613 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1614 if (!priv)
1615 return -ENOMEM;
1616
1617 dev_set_drvdata(dev, priv);
1618
5dbcf319
RK		 1619 if (dev->of_node)
1620 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1621
1622 /* If no CRTCs were found, fall back to our old behaviour */
1623 if (crtcs == 0) {
1624 dev_warn(dev, "Falling back to first CRTC\n");
1625 crtcs = 1 << 0;
1626 }
1627
a3584f60
RK		 1628 priv->connector.interlace_allowed = 1;
1629 priv->encoder.possible_crtcs = crtcs;
c707c361 1630
a3584f60 1631 ret = tda998x_create(client, priv);
c707c361
RK		 1632 if (ret)
1633 return ret;
1634
1635 if (!dev->of_node && params)
a3584f60 1636 tda998x_encoder_set_config(priv, params);
c707c361 1637
a3584f60 1638 tda998x_encoder_set_polling(priv, &priv->connector);
c707c361 1639
a3584f60
RK		 1640 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1641 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
13a3d91f 1642 DRM_MODE_ENCODER_TMDS, NULL);
c707c361
RK		 1643 if (ret)
1644 goto err_encoder;
1645
a3584f60 1646 drm_connector_helper_add(&priv->connector,
c707c361 1647 &tda998x_connector_helper_funcs);
a3584f60 1648 ret = drm_connector_init(drm, &priv->connector,
c707c361
RK		 1649 &tda998x_connector_funcs,
1650 DRM_MODE_CONNECTOR_HDMIA);
1651 if (ret)
1652 goto err_connector;
1653
a3584f60 1654 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
c707c361
RK		 1655
1656 return 0;
1657
c707c361 1658err_connector:
a3584f60 1659 drm_encoder_cleanup(&priv->encoder);
c707c361 1660err_encoder:
a3584f60 1661 tda998x_destroy(priv);
c707c361
RK		 1662 return ret;
1663}
1664
1665static void tda998x_unbind(struct device *dev, struct device *master,
1666 void *data)
1667{
a3584f60 1668 struct tda998x_priv *priv = dev_get_drvdata(dev);
c707c361 1669
a3584f60
RK		 1670 drm_connector_cleanup(&priv->connector);
1671 drm_encoder_cleanup(&priv->encoder);
1672 tda998x_destroy(priv);
c707c361
RK		 1673}
1674
1675static const struct component_ops tda998x_ops = {
1676 .bind = tda998x_bind,
1677 .unbind = tda998x_unbind,
1678};
1679
1680static int
1681tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1682{
1683 return component_add(&client->dev, &tda998x_ops);
1684}
1685
1686static int tda998x_remove(struct i2c_client *client)
1687{
1688 component_del(&client->dev, &tda998x_ops);
1689 return 0;
1690}
1691
0d44ea19
JFM		 1692#ifdef CONFIG_OF
1693static const struct of_device_id tda998x_dt_ids[] = {
1694 { .compatible = "nxp,tda998x", },
1695 { }
1696};
1697MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1698#endif
1699
e7792ce2
RC		 1700static struct i2c_device_id tda998x_ids[] = {
1701 { "tda998x", 0 },
1702 { }
1703};
1704MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1705
3d58e318
RK		 1706static struct i2c_driver tda998x_driver = {
1707 .probe = tda998x_probe,
1708 .remove = tda998x_remove,
1709 .driver = {
1710 .name = "tda998x",
1711 .of_match_table = of_match_ptr(tda998x_dt_ids),
e7792ce2 1712 },
3d58e318 1713 .id_table = tda998x_ids,
e7792ce2
RC		 1714};
1715
3d58e318 1716module_i2c_driver(tda998x_driver);
e7792ce2
RC		 1717
1718MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1719MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1720MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)