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Merge tag 'mfd-fixes-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / inc / smu74_discrete.h
CommitLineData
b304ac83 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef SMU74_DISCRETE_H
25#define SMU74_DISCRETE_H
26
27#include "smu74.h"
28
29#pragma pack(push, 1)
30
31
32#define NUM_SCLK_RANGE 8
33
34#define VCO_3_6 1
35#define VCO_2_4 3
36
37#define POSTDIV_DIV_BY_1 0
38#define POSTDIV_DIV_BY_2 1
39#define POSTDIV_DIV_BY_4 2
40#define POSTDIV_DIV_BY_8 3
41#define POSTDIV_DIV_BY_16 4
42
43struct sclkFcwRange_t {
44 uint8_t vco_setting;
45 uint8_t postdiv;
46 uint16_t fcw_pcc;
47
48 uint16_t fcw_trans_upper;
49 uint16_t fcw_trans_lower;
50};
51typedef struct sclkFcwRange_t sclkFcwRange_t;
52
53struct SMIO_Pattern {
54 uint16_t Voltage;
55 uint8_t Smio;
56 uint8_t padding;
57};
58
59typedef struct SMIO_Pattern SMIO_Pattern;
60
61struct SMIO_Table {
62 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
63};
64
65typedef struct SMIO_Table SMIO_Table;
66
67struct SMU_SclkSetting {
68 uint32_t SclkFrequency;
69 uint16_t Fcw_int;
70 uint16_t Fcw_frac;
71 uint16_t Pcc_fcw_int;
72 uint8_t PllRange;
73 uint8_t SSc_En;
a6ece7ff 74 uint16_t Sclk_slew_rate;
75 uint16_t Pcc_up_slew_rate;
76 uint16_t Pcc_down_slew_rate;
b304ac83 77 uint16_t Fcw1_int;
78 uint16_t Fcw1_frac;
a6ece7ff 79 uint16_t Sclk_ss_slew_rate;
b304ac83 80};
81typedef struct SMU_SclkSetting SMU_SclkSetting;
82
83struct SMU74_Discrete_GraphicsLevel {
84 SMU_VoltageLevel MinVoltage;
85 uint8_t pcieDpmLevel;
86 uint8_t DeepSleepDivId;
87 uint16_t ActivityLevel;
88 uint32_t CgSpllFuncCntl3;
89 uint32_t CgSpllFuncCntl4;
90 uint32_t CcPwrDynRm;
91 uint32_t CcPwrDynRm1;
92 uint8_t SclkDid;
93 uint8_t padding;
94 uint8_t EnabledForActivity;
95 uint8_t EnabledForThrottle;
96 uint8_t UpHyst;
97 uint8_t DownHyst;
98 uint8_t VoltageDownHyst;
99 uint8_t PowerThrottle;
100 SMU_SclkSetting SclkSetting;
101};
102
103typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
104
105struct SMU74_Discrete_ACPILevel {
106 uint32_t Flags;
107 SMU_VoltageLevel MinVoltage;
108 uint32_t SclkFrequency;
109 uint8_t SclkDid;
110 uint8_t DisplayWatermark;
111 uint8_t DeepSleepDivId;
112 uint8_t padding;
113 uint32_t CcPwrDynRm;
114 uint32_t CcPwrDynRm1;
115
116 SMU_SclkSetting SclkSetting;
117};
118
119typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
120
121struct SMU74_Discrete_Ulv {
122 uint32_t CcPwrDynRm;
123 uint32_t CcPwrDynRm1;
124 uint16_t VddcOffset;
125 uint8_t VddcOffsetVid;
126 uint8_t VddcPhase;
a6ece7ff 127 uint16_t BifSclkDfs;
128 uint16_t Reserved;
b304ac83 129};
130
131typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
132
133struct SMU74_Discrete_MemoryLevel {
134 SMU_VoltageLevel MinVoltage;
135 uint32_t MinMvdd;
136
137 uint32_t MclkFrequency;
138
139 uint8_t StutterEnable;
140 uint8_t EnabledForThrottle;
141 uint8_t EnabledForActivity;
142 uint8_t padding_0;
143
144 uint8_t UpHyst;
145 uint8_t DownHyst;
146 uint8_t VoltageDownHyst;
147 uint8_t padding_1;
148
149 uint16_t ActivityLevel;
150 uint8_t DisplayWatermark;
151 uint8_t Reserved;
152};
153
154typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
155
156struct SMU74_Discrete_LinkLevel {
157 uint8_t PcieGenSpeed;
158 uint8_t PcieLaneCount;
159 uint8_t EnabledForActivity;
160 uint8_t SPC;
161 uint32_t DownThreshold;
162 uint32_t UpThreshold;
a6ece7ff 163 uint16_t BifSclkDfs;
164 uint16_t Reserved;
b304ac83 165};
166
167typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
168
169struct SMU74_Discrete_MCArbDramTimingTableEntry {
170 uint32_t McArbDramTiming;
171 uint32_t McArbDramTiming2;
172 uint8_t McArbBurstTime;
173 uint8_t padding[3];
174};
175
176typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
177
178struct SMU74_Discrete_MCArbDramTimingTable {
179 SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
180};
181
182typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
183
184struct SMU74_Discrete_UvdLevel {
185 uint32_t VclkFrequency;
186 uint32_t DclkFrequency;
187 SMU_VoltageLevel MinVoltage;
188 uint8_t VclkDivider;
189 uint8_t DclkDivider;
190 uint8_t padding[2];
191};
192
193typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
194
195struct SMU74_Discrete_ExtClkLevel {
196 uint32_t Frequency;
197 SMU_VoltageLevel MinVoltage;
198 uint8_t Divider;
199 uint8_t padding[3];
200};
201
202typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
203
204struct SMU74_Discrete_StateInfo {
205 uint32_t SclkFrequency;
206 uint32_t MclkFrequency;
207 uint32_t VclkFrequency;
208 uint32_t DclkFrequency;
209 uint32_t SamclkFrequency;
210 uint32_t AclkFrequency;
211 uint32_t EclkFrequency;
212 uint16_t MvddVoltage;
213 uint16_t padding16;
214 uint8_t DisplayWatermark;
215 uint8_t McArbIndex;
216 uint8_t McRegIndex;
217 uint8_t SeqIndex;
218 uint8_t SclkDid;
219 int8_t SclkIndex;
220 int8_t MclkIndex;
221 uint8_t PCIeGen;
222};
223
224typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
225
31b21243
RZ		 226struct SMU_QuadraticCoeffs {
227 int32_t m1;
228 uint32_t b;
229
230 int16_t m2;
231 uint8_t m1_shift;
232 uint8_t m2_shift;
233};
234typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
235
b304ac83 236struct SMU74_Discrete_DpmTable {
237
238 SMU74_PIDController GraphicsPIDController;
239 SMU74_PIDController MemoryPIDController;
240 SMU74_PIDController LinkPIDController;
241
242 uint32_t SystemFlags;
243
244 uint32_t VRConfig;
245 uint32_t SmioMask1;
246 uint32_t SmioMask2;
247 SMIO_Table SmioTable1;
248 SMIO_Table SmioTable2;
249
250 uint32_t MvddLevelCount;
251
252
253 uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
254 uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
255 uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
256
257 uint8_t GraphicsDpmLevelCount;
258 uint8_t MemoryDpmLevelCount;
259 uint8_t LinkLevelCount;
260 uint8_t MasterDeepSleepControl;
261
262 uint8_t UvdLevelCount;
263 uint8_t VceLevelCount;
264 uint8_t AcpLevelCount;
265 uint8_t SamuLevelCount;
266
267 uint8_t ThermOutGpio;
268 uint8_t ThermOutPolarity;
269 uint8_t ThermOutMode;
270 uint8_t BootPhases;
31b21243
RZ		 271
272 uint8_t VRHotLevel;
273 uint8_t Reserved1[3];
274 uint16_t FanStartTemperature;
275 uint16_t FanStopTemperature;
276 uint16_t MaxVoltage;
277 uint16_t Reserved2;
278 uint32_t Reserved[1];
b304ac83 279
280 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
281 SMU74_Discrete_MemoryLevel MemoryACPILevel;
282 SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
283 SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK];
284 SMU74_Discrete_ACPILevel ACPILevel;
285 SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD];
286 SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE];
287 SMU74_Discrete_ExtClkLevel AcpLevel[SMU74_MAX_LEVELS_ACP];
288 SMU74_Discrete_ExtClkLevel SamuLevel[SMU74_MAX_LEVELS_SAMU];
289 SMU74_Discrete_Ulv Ulv;
290
291 uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
292
293 uint32_t SclkStepSize;
294 uint32_t Smio[SMU74_MAX_ENTRIES_SMIO];
295
296 uint8_t UvdBootLevel;
297 uint8_t VceBootLevel;
298 uint8_t AcpBootLevel;
299 uint8_t SamuBootLevel;
300
301 uint8_t GraphicsBootLevel;
302 uint8_t GraphicsVoltageChangeEnable;
303 uint8_t GraphicsThermThrottleEnable;
304 uint8_t GraphicsInterval;
305
306 uint8_t VoltageInterval;
307 uint8_t ThermalInterval;
308 uint16_t TemperatureLimitHigh;
309
310 uint16_t TemperatureLimitLow;
311 uint8_t MemoryBootLevel;
312 uint8_t MemoryVoltageChangeEnable;
313
314 uint16_t BootMVdd;
315 uint8_t MemoryInterval;
316 uint8_t MemoryThermThrottleEnable;
317
318 uint16_t VoltageResponseTime;
319 uint16_t PhaseResponseTime;
320
321 uint8_t PCIeBootLinkLevel;
322 uint8_t PCIeGenInterval;
323 uint8_t DTEInterval;
324 uint8_t DTEMode;
325
326 uint8_t SVI2Enable;
327 uint8_t VRHotGpio;
328 uint8_t AcDcGpio;
329 uint8_t ThermGpio;
330
331 uint16_t PPM_PkgPwrLimit;
332 uint16_t PPM_TemperatureLimit;
333
334 uint16_t DefaultTdp;
335 uint16_t TargetTdp;
336
337 uint16_t FpsHighThreshold;
338 uint16_t FpsLowThreshold;
339
340 uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
341 uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
342
e16ff21d
RZ		 343 uint16_t TemperatureLimitEdge;
344 uint16_t TemperatureLimitHotspot;
345
b304ac83 346 uint16_t BootVddc;
347 uint16_t BootVddci;
348
e16ff21d
RZ		 349 uint16_t FanGainEdge;
350 uint16_t FanGainHotspot;
b304ac83 351
352 uint32_t LowSclkInterruptThreshold;
353 uint32_t VddGfxReChkWait;
354
355 uint8_t ClockStretcherAmount;
356 uint8_t Sclk_CKS_masterEn0_7;
357 uint8_t Sclk_CKS_masterEn8_15;
358 uint8_t DPMFreezeAndForced;
359
360 uint8_t Sclk_voltageOffset[8];
361
362 SMU_ClockStretcherDataTable ClockStretcherDataTable;
363 SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
364
365 uint32_t CurrSclkPllRange;
366 sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
31b21243
RZ		 367 GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
368 SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
b304ac83 369};
370
371typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
372
373
374struct SMU74_Discrete_FanTable {
375 uint16_t FdoMode;
376 int16_t TempMin;
377 int16_t TempMed;
378 int16_t TempMax;
379 int16_t Slope1;
380 int16_t Slope2;
381 int16_t FdoMin;
382 int16_t HystUp;
383 int16_t HystDown;
384 int16_t HystSlope;
385 int16_t TempRespLim;
386 int16_t TempCurr;
387 int16_t SlopeCurr;
388 int16_t PwmCurr;
389 uint32_t RefreshPeriod;
390 int16_t FdoMax;
391 uint8_t TempSrc;
392 int8_t Padding;
393};
394
395typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
396
397#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
398#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
399
400
401struct SMU7_MclkDpmScoreboard {
402 uint32_t PercentageBusy;
403
404 int32_t PIDError;
405 int32_t PIDIntegral;
406 int32_t PIDOutput;
407
408 uint32_t SigmaDeltaAccum;
409 uint32_t SigmaDeltaOutput;
410 uint32_t SigmaDeltaLevel;
411
412 uint32_t UtilizationSetpoint;
413
414 uint8_t TdpClampMode;
415 uint8_t TdcClampMode;
416 uint8_t ThermClampMode;
417 uint8_t VoltageBusy;
418
419 int8_t CurrLevel;
420 int8_t TargLevel;
421 uint8_t LevelChangeInProgress;
422 uint8_t UpHyst;
423
424 uint8_t DownHyst;
425 uint8_t VoltageDownHyst;
426 uint8_t DpmEnable;
427 uint8_t DpmRunning;
428
429 uint8_t DpmForce;
430 uint8_t DpmForceLevel;
431 uint8_t padding2;
432 uint8_t McArbIndex;
433
434 uint32_t MinimumPerfMclk;
435
436 uint8_t AcpiReq;
437 uint8_t AcpiAck;
438 uint8_t MclkSwitchInProgress;
439 uint8_t MclkSwitchCritical;
440
441 uint8_t IgnoreVBlank;
442 uint8_t TargetMclkIndex;
443 uint16_t VbiFailureCount;
444 uint8_t VbiWaitCounter;
445 uint8_t EnabledLevelsChange;
446
447 uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
448 uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
449
450 void (*TargetStateCalculator)(uint8_t);
451 void (*SavedTargetStateCalculator)(uint8_t);
452
453 uint16_t AutoDpmInterval;
454 uint16_t AutoDpmRange;
455
456 uint16_t VbiTimeoutCount;
457 uint16_t MclkSwitchingTime;
458
459 uint8_t fastSwitch;
460 uint8_t Save_PIC_VDDGFX_EXIT;
461 uint8_t Save_PIC_VDDGFX_ENTER;
462 uint8_t padding;
463};
464
465typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
466
467struct SMU7_UlvScoreboard {
468 uint8_t EnterUlv;
469 uint8_t ExitUlv;
470 uint8_t UlvActive;
471 uint8_t WaitingForUlv;
472 uint8_t UlvEnable;
473 uint8_t UlvRunning;
474 uint8_t UlvMasterEnable;
475 uint8_t padding;
476 uint32_t UlvAbortedCount;
477 uint32_t UlvTimeStamp;
478};
479
480typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
481
482struct VddgfxSavedRegisters {
483 uint32_t GPU_DBG[3];
484 uint32_t MEC_BaseAddress_Hi;
485 uint32_t MEC_BaseAddress_Lo;
486 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
487 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
488 uint32_t CP_INT_CNTL;
489};
490
491typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
492
493struct SMU7_VddGfxScoreboard {
494 uint8_t VddGfxEnable;
495 uint8_t VddGfxActive;
496 uint8_t VPUResetOccured;
497 uint8_t padding;
498
499 uint32_t VddGfxEnteredCount;
500 uint32_t VddGfxAbortedCount;
501
502 uint32_t VddGfxVid;
503
504 VddgfxSavedRegisters SavedRegisters;
505};
506
507typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
508
509struct SMU7_TdcLimitScoreboard {
510 uint8_t Enable;
511 uint8_t Running;
512 uint16_t Alpha;
513 uint32_t FilteredIddc;
514 uint32_t IddcLimit;
515 uint32_t IddcHyst;
516 SMU7_HystController_Data HystControllerData;
517};
518
519typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
520
521struct SMU7_PkgPwrLimitScoreboard {
522 uint8_t Enable;
523 uint8_t Running;
524 uint16_t Alpha;
525 uint32_t FilteredPkgPwr;
526 uint32_t Limit;
527 uint32_t Hyst;
528 uint32_t LimitFromDriver;
529 SMU7_HystController_Data HystControllerData;
530};
531
532typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
533
534struct SMU7_BapmScoreboard {
535 uint32_t source_powers[SMU74_DTE_SOURCES];
536 uint32_t source_powers_last[SMU74_DTE_SOURCES];
537 int32_t entity_temperatures[SMU74_NUM_GPU_TES];
538 int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
539 int32_t Limit;
540 int32_t Hyst;
541 int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
542 int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
543 uint16_t ConfigTDPPowerScalar;
544 uint16_t FanSpeedPowerScalar;
545 uint16_t OverDrivePowerScalar;
546 uint16_t OverDriveLimitScalar;
547 uint16_t FinalPowerScalar;
548 uint8_t VariantID;
549 uint8_t spare997;
550
551 SMU7_HystController_Data HystControllerData;
552
553 int32_t temperature_gradient_slope;
554 int32_t temperature_gradient;
555 uint32_t measured_temperature;
556};
557
558
559typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
560
561struct SMU7_AcpiScoreboard {
562 uint32_t SavedInterruptMask[2];
563 uint8_t LastACPIRequest;
564 uint8_t CgBifResp;
565 uint8_t RequestType;
566 uint8_t Padding;
567 SMU74_Discrete_ACPILevel D0Level;
568};
569
570typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
571
b304ac83 572struct SMU74_Discrete_PmFuses {
573 uint8_t BapmVddCVidHiSidd[8];
574 uint8_t BapmVddCVidLoSidd[8];
575 uint8_t VddCVid[8];
576 uint8_t SviLoadLineEn;
577 uint8_t SviLoadLineVddC;
578 uint8_t SviLoadLineTrimVddC;
579 uint8_t SviLoadLineOffsetVddC;
580 uint16_t TDC_VDDC_PkgLimit;
581 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
582 uint8_t TDC_MAWt;
583 uint8_t TdcWaterfallCtl;
584 uint8_t LPMLTemperatureMin;
585 uint8_t LPMLTemperatureMax;
586 uint8_t Reserved;
587
588 uint8_t LPMLTemperatureScaler[16];
589
590 int16_t FuzzyFan_ErrorSetDelta;
591 int16_t FuzzyFan_ErrorRateSetDelta;
592 int16_t FuzzyFan_PwmSetDelta;
593 uint16_t Reserved6;
594
595 uint8_t GnbLPML[16];
596
597 uint8_t GnbLPMLMaxVid;
598 uint8_t GnbLPMLMinVid;
599 uint8_t Reserved1[2];
600
601 uint16_t BapmVddCBaseLeakageHiSidd;
602 uint16_t BapmVddCBaseLeakageLoSidd;
603
604 uint16_t VFT_Temp[3];
605 uint16_t padding;
606
607 SMU_QuadraticCoeffs VFT_ATE[3];
608
609 SMU_QuadraticCoeffs AVFS_GB;
610 SMU_QuadraticCoeffs ATE_ACBTC_GB;
611
612 SMU_QuadraticCoeffs P2V;
613
614 uint32_t PsmCharzFreq;
615
616 uint16_t InversionVoltage;
617 uint16_t PsmCharzTemp;
618
619 uint32_t EnabledAvfsModules;
620};
621
622typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
623
624struct SMU7_Discrete_Log_Header_Table {
625 uint32_t version;
626 uint32_t asic_id;
627 uint16_t flags;
628 uint16_t entry_size;
629 uint32_t total_size;
630 uint32_t num_of_entries;
631 uint8_t type;
632 uint8_t mode;
633 uint8_t filler_0[2];
634 uint32_t filler_1[2];
635};
636
637typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
638
639struct SMU7_Discrete_Log_Cntl {
640 uint8_t Enabled;
641 uint8_t Type;
642 uint8_t padding[2];
643 uint32_t BufferSize;
644 uint32_t SamplesLogged;
645 uint32_t SampleSize;
646 uint32_t AddrL;
647 uint32_t AddrH;
648};
649
650typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
651
652#if defined SMU__DGPU_ONLY
653#define CAC_ACC_NW_NUM_OF_SIGNALS 87
654#endif
655
656
657struct SMU7_Discrete_Cac_Collection_Table {
658 uint32_t temperature;
659 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
660};
661
662typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
663
664struct SMU7_Discrete_Cac_Verification_Table {
665 uint32_t VddcTotalPower;
666 uint32_t VddcLeakagePower;
667 uint32_t VddcConstantPower;
668 uint32_t VddcGfxDynamicPower;
669 uint32_t VddcUvdDynamicPower;
670 uint32_t VddcVceDynamicPower;
671 uint32_t VddcAcpDynamicPower;
672 uint32_t VddcPcieDynamicPower;
673 uint32_t VddcDceDynamicPower;
674 uint32_t VddcCurrent;
675 uint32_t VddcVoltage;
676 uint32_t VddciTotalPower;
677 uint32_t VddciLeakagePower;
678 uint32_t VddciConstantPower;
679 uint32_t VddciDynamicPower;
680 uint32_t Vddr1TotalPower;
681 uint32_t Vddr1LeakagePower;
682 uint32_t Vddr1ConstantPower;
683 uint32_t Vddr1DynamicPower;
684 uint32_t spare[4];
685 uint32_t temperature;
686};
687
688typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
689
690struct SMU7_Discrete_Pm_Status_Table {
691 int32_t T_meas_max;
692 int32_t T_meas_acc;
693 int32_t T_calc_max;
694 int32_t T_calc_acc;
695 uint32_t P_scalar_acc;
696 uint32_t P_calc_max;
697 uint32_t P_calc_acc;
698
699 uint32_t I_calc_max;
700 uint32_t I_calc_acc;
701 uint32_t I_calc_acc_vddci;
702 uint32_t V_calc_noload_acc;
703 uint32_t V_calc_load_acc;
704 uint32_t V_calc_noload_acc_vddci;
705 uint32_t P_meas_acc;
706 uint32_t V_meas_noload_acc;
707 uint32_t V_meas_load_acc;
708 uint32_t I_meas_acc;
709 uint32_t P_meas_acc_vddci;
710 uint32_t V_meas_noload_acc_vddci;
711 uint32_t V_meas_load_acc_vddci;
712 uint32_t I_meas_acc_vddci;
713
714 uint16_t Sclk_dpm_residency[8];
715 uint16_t Uvd_dpm_residency[8];
716 uint16_t Vce_dpm_residency[8];
2cc0c0b5 717 uint16_t Mclk_dpm_residency[4];
b304ac83 718
719 uint32_t P_vddci_acc;
720 uint32_t P_vddr1_acc;
721 uint32_t P_nte1_acc;
722 uint32_t PkgPwr_max;
723 uint32_t PkgPwr_acc;
724 uint32_t MclkSwitchingTime_max;
725 uint32_t MclkSwitchingTime_acc;
726 uint32_t FanPwm_acc;
727 uint32_t FanRpm_acc;
728
729 uint32_t AccCnt;
730};
731
732typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
733
734#define SMU7_MAX_GFX_CU_COUNT 16
735
736struct SMU7_GfxCuPgScoreboard {
737 uint8_t Enabled;
738 uint8_t WaterfallUp;
739 uint8_t WaterfallDown;
740 uint8_t WaterfallLimit;
741 uint8_t CurrMaxCu;
742 uint8_t TargMaxCu;
743 uint8_t ClampMode;
744 uint8_t Active;
745 uint8_t MaxSupportedCu;
746 uint8_t MinSupportedCu;
747 uint8_t PendingGfxCuHostInterrupt;
748 uint8_t LastFilteredMaxCuInteger;
749 uint16_t FilteredMaxCu;
750 uint16_t FilteredMaxCuAlpha;
751 uint16_t FilterResetCount;
752 uint16_t FilterResetCountLimit;
753 uint8_t ForceCu;
754 uint8_t ForceCuCount;
755 uint8_t spare[2];
756};
757
758typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
759
760#define SMU7_SCLK_CAC 0x561
761#define SMU7_MCLK_CAC 0xF9
762#define SMU7_VCLK_CAC 0x2DE
763#define SMU7_DCLK_CAC 0x2DE
764#define SMU7_ECLK_CAC 0x25E
765#define SMU7_ACLK_CAC 0x25E
766#define SMU7_SAMCLK_CAC 0x25E
767#define SMU7_DISPCLK_CAC 0x100
768#define SMU7_CAC_CONSTANT 0x2EE3430
769#define SMU7_CAC_CONSTANT_SHIFT 18
770
771#define SMU7_VDDCI_MCLK_CONST 1765
772#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
773#define SMU7_VDDCI_VDDCI_CONST 50958
774#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
775#define SMU7_VDDCI_CONST 11781
776#define SMU7_VDDCI_STROBE_PWR 1331
777
778#define SMU7_VDDR1_CONST 693
779#define SMU7_VDDR1_CAC_WEIGHT 20
780#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
781#define SMU7_VDDR1_STROBE_PWR 512
782
783#define SMU7_AREA_COEFF_UVD 0xA78
784#define SMU7_AREA_COEFF_VCE 0x190A
785#define SMU7_AREA_COEFF_ACP 0x22D1
786#define SMU7_AREA_COEFF_SAMU 0x534
787
788#define SMU7_THERM_OUT_MODE_DISABLE 0x0
789#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
790#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
791
2cc0c0b5
FC		 792// DIDT Defines
793#define SQ_Enable_MASK 0x1
794#define SQ_IR_MASK 0x2
795#define SQ_PCC_MASK 0x4
796#define SQ_EDC_MASK 0x8
797
798#define TCP_Enable_MASK 0x100
799#define TCP_IR_MASK 0x200
800#define TCP_PCC_MASK 0x400
801#define TCP_EDC_MASK 0x800
802
803#define TD_Enable_MASK 0x10000
804#define TD_IR_MASK 0x20000
805#define TD_PCC_MASK 0x40000
806#define TD_EDC_MASK 0x80000
807
808#define DB_Enable_MASK 0x1000000
809#define DB_IR_MASK 0x2000000
810#define DB_PCC_MASK 0x4000000
811#define DB_EDC_MASK 0x8000000
812
813#define SQ_Enable_SHIFT 0
814#define SQ_IR_SHIFT 1
815#define SQ_PCC_SHIFT 2
816#define SQ_EDC_SHIFT 3
817
818#define TCP_Enable_SHIFT 8
819#define TCP_IR_SHIFT 9
820#define TCP_PCC_SHIFT 10
821#define TCP_EDC_SHIFT 11
822
823#define TD_Enable_SHIFT 16
824#define TD_IR_SHIFT 17
825#define TD_PCC_SHIFT 18
826#define TD_EDC_SHIFT 19
827
828#define DB_Enable_SHIFT 24
829#define DB_IR_SHIFT 25
830#define DB_PCC_SHIFT 26
831#define DB_EDC_SHIFT 27
832
31b21243
RZ		 833#define BTCGB0_Vdroop_Enable_MASK 0x1
834#define BTCGB1_Vdroop_Enable_MASK 0x2
835#define AVFSGB0_Vdroop_Enable_MASK 0x4
836#define AVFSGB1_Vdroop_Enable_MASK 0x8
837
838#define BTCGB0_Vdroop_Enable_SHIFT 0
839#define BTCGB1_Vdroop_Enable_SHIFT 1
840#define AVFSGB0_Vdroop_Enable_SHIFT 2
841#define AVFSGB1_Vdroop_Enable_SHIFT 3
842
843
b304ac83 844#pragma pack(pop)
845
846
847#endif
848
Linux 6.x block layer and io_uring tree(s)