| b2441318 |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 306d8db3 |
2 | #ifndef SMU72_DISCRETE_H |
| 3 | #define SMU72_DISCRETE_H |
| 4 | |
| 5 | #include "smu72.h" |
| 6 | |
| 7 | #if !defined(SMC_MICROCODE) |
| 8 | #pragma pack(push, 1) |
| 9 | #endif |
| 10 | |
| 11 | struct SMIO_Pattern { |
| 12 | uint16_t Voltage; |
| 13 | uint8_t Smio; |
| 14 | uint8_t padding; |
| 15 | }; |
| 16 | |
| 17 | typedef struct SMIO_Pattern SMIO_Pattern; |
| 18 | |
| 19 | struct SMIO_Table { |
| 20 | SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; |
| 21 | }; |
| 22 | |
| 23 | typedef struct SMIO_Table SMIO_Table; |
| 24 | |
| 25 | struct SMU72_Discrete_GraphicsLevel { |
| 26 | SMU_VoltageLevel MinVoltage; |
| 27 | |
| 28 | uint32_t SclkFrequency; |
| 29 | |
| 30 | uint8_t pcieDpmLevel; |
| 31 | uint8_t DeepSleepDivId; |
| 32 | uint16_t ActivityLevel; |
| 33 | |
| 34 | uint32_t CgSpllFuncCntl3; |
| 35 | uint32_t CgSpllFuncCntl4; |
| 36 | uint32_t SpllSpreadSpectrum; |
| 37 | uint32_t SpllSpreadSpectrum2; |
| 38 | uint32_t CcPwrDynRm; |
| 39 | uint32_t CcPwrDynRm1; |
| 40 | uint8_t SclkDid; |
| 41 | uint8_t DisplayWatermark; |
| 42 | uint8_t EnabledForActivity; |
| 43 | uint8_t EnabledForThrottle; |
| 44 | uint8_t UpHyst; |
| 45 | uint8_t DownHyst; |
| 46 | uint8_t VoltageDownHyst; |
| 47 | uint8_t PowerThrottle; |
| 48 | }; |
| 49 | |
| 50 | typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel; |
| 51 | |
| 52 | struct SMU72_Discrete_ACPILevel { |
| 53 | uint32_t Flags; |
| 54 | SMU_VoltageLevel MinVoltage; |
| 55 | uint32_t SclkFrequency; |
| 56 | uint8_t SclkDid; |
| 57 | uint8_t DisplayWatermark; |
| 58 | uint8_t DeepSleepDivId; |
| 59 | uint8_t padding; |
| 60 | uint32_t CgSpllFuncCntl; |
| 61 | uint32_t CgSpllFuncCntl2; |
| 62 | uint32_t CgSpllFuncCntl3; |
| 63 | uint32_t CgSpllFuncCntl4; |
| 64 | uint32_t SpllSpreadSpectrum; |
| 65 | uint32_t SpllSpreadSpectrum2; |
| 66 | uint32_t CcPwrDynRm; |
| 67 | uint32_t CcPwrDynRm1; |
| 68 | }; |
| 69 | |
| 70 | typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel; |
| 71 | |
| 72 | struct SMU72_Discrete_Ulv { |
| 73 | uint32_t CcPwrDynRm; |
| 74 | uint32_t CcPwrDynRm1; |
| 75 | uint16_t VddcOffset; |
| 76 | uint8_t VddcOffsetVid; |
| 77 | uint8_t VddcPhase; |
| 78 | uint32_t Reserved; |
| 79 | }; |
| 80 | |
| 81 | typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv; |
| 82 | |
| 83 | struct SMU72_Discrete_MemoryLevel { |
| 84 | SMU_VoltageLevel MinVoltage; |
| 85 | uint32_t MinMvdd; |
| 86 | |
| 87 | uint32_t MclkFrequency; |
| 88 | |
| 89 | uint8_t EdcReadEnable; |
| 90 | uint8_t EdcWriteEnable; |
| 91 | uint8_t RttEnable; |
| 92 | uint8_t StutterEnable; |
| 93 | |
| 94 | uint8_t StrobeEnable; |
| 95 | uint8_t StrobeRatio; |
| 96 | uint8_t EnabledForThrottle; |
| 97 | uint8_t EnabledForActivity; |
| 98 | |
| 99 | uint8_t UpHyst; |
| 100 | uint8_t DownHyst; |
| 101 | uint8_t VoltageDownHyst; |
| 102 | uint8_t padding; |
| 103 | |
| 104 | uint16_t ActivityLevel; |
| 105 | uint8_t DisplayWatermark; |
| 106 | uint8_t padding1; |
| 107 | |
| 108 | uint32_t MpllFuncCntl; |
| 109 | uint32_t MpllFuncCntl_1; |
| 110 | uint32_t MpllFuncCntl_2; |
| 111 | uint32_t MpllAdFuncCntl; |
| 112 | uint32_t MpllDqFuncCntl; |
| 113 | uint32_t MclkPwrmgtCntl; |
| 114 | uint32_t DllCntl; |
| 115 | uint32_t MpllSs1; |
| 116 | uint32_t MpllSs2; |
| 117 | }; |
| 118 | |
| 119 | typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel; |
| 120 | |
| 121 | struct SMU72_Discrete_LinkLevel { |
| 122 | uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */ |
| 123 | uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ |
| 124 | uint8_t EnabledForActivity; |
| 125 | uint8_t SPC; |
| 126 | uint32_t DownThreshold; |
| 127 | uint32_t UpThreshold; |
| 128 | uint32_t Reserved; |
| 129 | }; |
| 130 | |
| 131 | typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel; |
| 132 | |
| 133 | /* MC ARB DRAM Timing registers. */ |
| 134 | struct SMU72_Discrete_MCArbDramTimingTableEntry { |
| 135 | uint32_t McArbDramTiming; |
| 136 | uint32_t McArbDramTiming2; |
| 137 | uint8_t McArbBurstTime; |
| 138 | uint8_t padding[3]; |
| 139 | }; |
| 140 | |
| 141 | typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry; |
| 142 | |
| 143 | struct SMU72_Discrete_MCArbDramTimingTable { |
| 144 | SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; |
| 145 | }; |
| 146 | |
| 147 | typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable; |
| 148 | |
| 149 | /* UVD VCLK/DCLK state (level) definition. */ |
| 150 | struct SMU72_Discrete_UvdLevel { |
| 151 | uint32_t VclkFrequency; |
| 152 | uint32_t DclkFrequency; |
| 153 | SMU_VoltageLevel MinVoltage; |
| 154 | uint8_t VclkDivider; |
| 155 | uint8_t DclkDivider; |
| 156 | uint8_t padding[2]; |
| 157 | }; |
| 158 | |
| 159 | typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel; |
| 160 | |
| 161 | /* Clocks for other external blocks (VCE, ACP, SAMU). */ |
| 162 | struct SMU72_Discrete_ExtClkLevel { |
| 163 | uint32_t Frequency; |
| 164 | SMU_VoltageLevel MinVoltage; |
| 165 | uint8_t Divider; |
| 166 | uint8_t padding[3]; |
| 167 | }; |
| 168 | |
| 169 | typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel; |
| 170 | |
| 171 | struct SMU72_Discrete_StateInfo { |
| 172 | uint32_t SclkFrequency; |
| 173 | uint32_t MclkFrequency; |
| 174 | uint32_t VclkFrequency; |
| 175 | uint32_t DclkFrequency; |
| 176 | uint32_t SamclkFrequency; |
| 177 | uint32_t AclkFrequency; |
| 178 | uint32_t EclkFrequency; |
| 179 | uint16_t MvddVoltage; |
| 180 | uint16_t padding16; |
| 181 | uint8_t DisplayWatermark; |
| 182 | uint8_t McArbIndex; |
| 183 | uint8_t McRegIndex; |
| 184 | uint8_t SeqIndex; |
| 185 | uint8_t SclkDid; |
| 186 | int8_t SclkIndex; |
| 187 | int8_t MclkIndex; |
| 188 | uint8_t PCIeGen; |
| 189 | |
| 190 | }; |
| 191 | |
| 192 | typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo; |
| 193 | |
| 194 | struct SMU72_Discrete_DpmTable { |
| 195 | /* Multi-DPM controller settings */ |
| 196 | SMU72_PIDController GraphicsPIDController; |
| 197 | SMU72_PIDController MemoryPIDController; |
| 198 | SMU72_PIDController LinkPIDController; |
| 199 | |
| 200 | uint32_t SystemFlags; |
| 201 | |
| 202 | /* SMIO masks for voltage and phase controls */ |
| 203 | uint32_t VRConfig; |
| 204 | uint32_t SmioMask1; |
| 205 | uint32_t SmioMask2; |
| 206 | SMIO_Table SmioTable1; |
| 207 | SMIO_Table SmioTable2; |
| 208 | |
| 209 | uint32_t VddcLevelCount; |
| 210 | uint32_t VddciLevelCount; |
| 211 | uint32_t VddGfxLevelCount; |
| 212 | uint32_t MvddLevelCount; |
| 213 | |
| 214 | uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC]; |
| 215 | uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX]; |
| 216 | uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI]; |
| 217 | |
| 218 | uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX]; |
| 219 | uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX]; |
| 220 | uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX]; |
| 221 | |
| 222 | uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC]; |
| 223 | uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC]; |
| 224 | uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC]; |
| 225 | |
| 226 | uint8_t GraphicsDpmLevelCount; |
| 227 | uint8_t MemoryDpmLevelCount; |
| 228 | uint8_t LinkLevelCount; |
| 229 | uint8_t MasterDeepSleepControl; |
| 230 | |
| 231 | uint8_t UvdLevelCount; |
| 232 | uint8_t VceLevelCount; |
| 233 | uint8_t AcpLevelCount; |
| 234 | uint8_t SamuLevelCount; |
| 235 | |
| 236 | uint8_t ThermOutGpio; |
| 237 | uint8_t ThermOutPolarity; |
| 238 | uint8_t ThermOutMode; |
| 239 | uint8_t DPMFreezeAndForced; |
| 240 | uint32_t Reserved[4]; |
| 241 | |
| 242 | /* State table entries for each DPM state */ |
| 243 | SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS]; |
| 244 | SMU72_Discrete_MemoryLevel MemoryACPILevel; |
| 245 | SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY]; |
| 246 | SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK]; |
| 247 | SMU72_Discrete_ACPILevel ACPILevel; |
| 248 | SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD]; |
| 249 | SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE]; |
| 250 | SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP]; |
| 251 | SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU]; |
| 252 | SMU72_Discrete_Ulv Ulv; |
| 253 | |
| 254 | uint32_t SclkStepSize; |
| 255 | uint32_t Smio[SMU72_MAX_ENTRIES_SMIO]; |
| 256 | |
| 257 | uint8_t UvdBootLevel; |
| 258 | uint8_t VceBootLevel; |
| 259 | uint8_t AcpBootLevel; |
| 260 | uint8_t SamuBootLevel; |
| 261 | |
| 262 | uint8_t GraphicsBootLevel; |
| 263 | uint8_t GraphicsVoltageChangeEnable; |
| 264 | uint8_t GraphicsThermThrottleEnable; |
| 265 | uint8_t GraphicsInterval; |
| 266 | |
| 267 | uint8_t VoltageInterval; |
| 268 | uint8_t ThermalInterval; |
| 269 | uint16_t TemperatureLimitHigh; |
| 270 | |
| 271 | uint16_t TemperatureLimitLow; |
| 272 | uint8_t MemoryBootLevel; |
| 273 | uint8_t MemoryVoltageChangeEnable; |
| 274 | |
| 275 | uint16_t BootMVdd; |
| 276 | uint8_t MemoryInterval; |
| 277 | uint8_t MemoryThermThrottleEnable; |
| 278 | |
| 279 | uint16_t VoltageResponseTime; |
| 280 | uint16_t PhaseResponseTime; |
| 281 | |
| 282 | uint8_t PCIeBootLinkLevel; |
| 283 | uint8_t PCIeGenInterval; |
| 284 | uint8_t DTEInterval; |
| 285 | uint8_t DTEMode; |
| 286 | |
| 287 | uint8_t SVI2Enable; |
| 288 | uint8_t VRHotGpio; |
| 289 | uint8_t AcDcGpio; |
| 290 | uint8_t ThermGpio; |
| 291 | |
| 292 | uint16_t PPM_PkgPwrLimit; |
| 293 | uint16_t PPM_TemperatureLimit; |
| 294 | |
| 295 | uint16_t DefaultTdp; |
| 296 | uint16_t TargetTdp; |
| 297 | |
| 298 | uint16_t FpsHighThreshold; |
| 299 | uint16_t FpsLowThreshold; |
| 300 | |
| 301 | uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; |
| 302 | uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; |
| 303 | |
| 304 | uint8_t DTEAmbientTempBase; |
| 305 | uint8_t DTETjOffset; |
| 306 | uint8_t GpuTjMax; |
| 307 | uint8_t GpuTjHyst; |
| 308 | |
| 309 | SMU_VoltageLevel BootVoltage; |
| 310 | |
| 311 | uint32_t BAPM_TEMP_GRADIENT; |
| 312 | |
| 313 | uint32_t LowSclkInterruptThreshold; |
| 314 | uint32_t VddGfxReChkWait; |
| 315 | |
| 316 | uint8_t ClockStretcherAmount; |
| 317 | |
| 318 | uint8_t Sclk_CKS_masterEn0_7; |
| 319 | uint8_t Sclk_CKS_masterEn8_15; |
| 320 | uint8_t padding[1]; |
| 321 | |
| 322 | uint8_t Sclk_voltageOffset[8]; |
| 323 | |
| 324 | SMU_ClockStretcherDataTable ClockStretcherDataTable; |
| 325 | SMU_CKS_LOOKUPTable CKS_LOOKUPTable; |
| 326 | }; |
| 327 | |
| 328 | typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable; |
| 329 | |
| 330 | /* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */ |
| 331 | #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 |
| 332 | #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */ |
| 333 | |
| 334 | struct SMU72_Discrete_MCRegisterAddress { |
| 335 | uint16_t s0; |
| 336 | uint16_t s1; |
| 337 | }; |
| 338 | |
| 339 | typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress; |
| 340 | |
| 341 | struct SMU72_Discrete_MCRegisterSet { |
| 342 | uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; |
| 343 | }; |
| 344 | |
| 345 | typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet; |
| 346 | |
| 347 | struct SMU72_Discrete_MCRegisters { |
| 348 | uint8_t last; |
| 349 | uint8_t reserved[3]; |
| 350 | SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; |
| 351 | SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; |
| 352 | }; |
| 353 | |
| 354 | typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters; |
| 355 | |
| 356 | |
| 357 | /* --------------------------------------------------- Fan Table ----------------------------------------------------------- */ |
| 358 | |
| 359 | struct SMU72_Discrete_FanTable { |
| 360 | uint16_t FdoMode; |
| 361 | int16_t TempMin; |
| 362 | int16_t TempMed; |
| 363 | int16_t TempMax; |
| 364 | int16_t Slope1; |
| 365 | int16_t Slope2; |
| 366 | int16_t FdoMin; |
| 367 | int16_t HystUp; |
| 368 | int16_t HystDown; |
| 369 | int16_t HystSlope; |
| 370 | int16_t TempRespLim; |
| 371 | int16_t TempCurr; |
| 372 | int16_t SlopeCurr; |
| 373 | int16_t PwmCurr; |
| 374 | uint32_t RefreshPeriod; |
| 375 | int16_t FdoMax; |
| 376 | uint8_t TempSrc; |
| 377 | int8_t FanControl_GL_Flag; |
| 378 | }; |
| 379 | |
| 380 | typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable; |
| 381 | |
| 382 | #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 |
| 383 | #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) |
| 384 | |
| 385 | struct SMU7_MclkDpmScoreboard { |
| 386 | |
| 387 | uint32_t PercentageBusy; |
| 388 | |
| 389 | int32_t PIDError; |
| 390 | int32_t PIDIntegral; |
| 391 | int32_t PIDOutput; |
| 392 | |
| 393 | uint32_t SigmaDeltaAccum; |
| 394 | uint32_t SigmaDeltaOutput; |
| 395 | uint32_t SigmaDeltaLevel; |
| 396 | |
| 397 | uint32_t UtilizationSetpoint; |
| 398 | |
| 399 | uint8_t TdpClampMode; |
| 400 | uint8_t TdcClampMode; |
| 401 | uint8_t ThermClampMode; |
| 402 | uint8_t VoltageBusy; |
| 403 | |
| 404 | int8_t CurrLevel; |
| 405 | int8_t TargLevel; |
| 406 | uint8_t LevelChangeInProgress; |
| 407 | uint8_t UpHyst; |
| 408 | |
| 409 | uint8_t DownHyst; |
| 410 | uint8_t VoltageDownHyst; |
| 411 | uint8_t DpmEnable; |
| 412 | uint8_t DpmRunning; |
| 413 | |
| 414 | uint8_t DpmForce; |
| 415 | uint8_t DpmForceLevel; |
| 416 | uint8_t DisplayWatermark; |
| 417 | uint8_t McArbIndex; |
| 418 | |
| 419 | uint32_t MinimumPerfMclk; |
| 420 | |
| 421 | uint8_t AcpiReq; |
| 422 | uint8_t AcpiAck; |
| 423 | uint8_t MclkSwitchInProgress; |
| 424 | uint8_t MclkSwitchCritical; |
| 425 | |
| 426 | uint8_t IgnoreVBlank; |
| 427 | uint8_t TargetMclkIndex; |
| 428 | uint8_t TargetMvddIndex; |
| 429 | uint8_t MclkSwitchResult; |
| 430 | |
| 431 | uint16_t VbiFailureCount; |
| 432 | uint8_t VbiWaitCounter; |
| 433 | uint8_t EnabledLevelsChange; |
| 434 | |
| 435 | uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY]; |
| 436 | uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY]; |
| 437 | |
| 438 | void (*TargetStateCalculator)(uint8_t); |
| 439 | void (*SavedTargetStateCalculator)(uint8_t); |
| 440 | |
| 441 | uint16_t AutoDpmInterval; |
| 442 | uint16_t AutoDpmRange; |
| 443 | |
| 444 | uint16_t VbiTimeoutCount; |
| 445 | uint16_t MclkSwitchingTime; |
| 446 | |
| 447 | uint8_t fastSwitch; |
| 448 | uint8_t Save_PIC_VDDGFX_EXIT; |
| 449 | uint8_t Save_PIC_VDDGFX_ENTER; |
| 450 | uint8_t padding; |
| 451 | |
| 452 | }; |
| 453 | |
| 454 | typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; |
| 455 | |
| 456 | struct SMU7_UlvScoreboard { |
| 457 | uint8_t EnterUlv; |
| 458 | uint8_t ExitUlv; |
| 459 | uint8_t UlvActive; |
| 460 | uint8_t WaitingForUlv; |
| 461 | uint8_t UlvEnable; |
| 462 | uint8_t UlvRunning; |
| 463 | uint8_t UlvMasterEnable; |
| 464 | uint8_t padding; |
| 465 | uint32_t UlvAbortedCount; |
| 466 | uint32_t UlvTimeStamp; |
| 467 | }; |
| 468 | |
| 469 | typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; |
| 470 | |
| 471 | struct VddgfxSavedRegisters { |
| 472 | uint32_t GPU_DBG[3]; |
| 473 | uint32_t MEC_BaseAddress_Hi; |
| 474 | uint32_t MEC_BaseAddress_Lo; |
| 475 | uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; |
| 476 | uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; |
| 477 | uint32_t CP_INT_CNTL; |
| 478 | }; |
| 479 | |
| 480 | typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; |
| 481 | |
| 482 | struct SMU7_VddGfxScoreboard { |
| 483 | uint8_t VddGfxEnable; |
| 484 | uint8_t VddGfxActive; |
| 485 | uint8_t VPUResetOccured; |
| 486 | uint8_t padding; |
| 487 | |
| 488 | uint32_t VddGfxEnteredCount; |
| 489 | uint32_t VddGfxAbortedCount; |
| 490 | |
| 491 | uint32_t VddGfxVid; |
| 492 | |
| 493 | VddgfxSavedRegisters SavedRegisters; |
| 494 | }; |
| 495 | |
| 496 | typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; |
| 497 | |
| 498 | struct SMU7_TdcLimitScoreboard { |
| 499 | uint8_t Enable; |
| 500 | uint8_t Running; |
| 501 | uint16_t Alpha; |
| 502 | uint32_t FilteredIddc; |
| 503 | uint32_t IddcLimit; |
| 504 | uint32_t IddcHyst; |
| 505 | SMU7_HystController_Data HystControllerData; |
| 506 | }; |
| 507 | |
| 508 | typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; |
| 509 | |
| 510 | struct SMU7_PkgPwrLimitScoreboard { |
| 511 | uint8_t Enable; |
| 512 | uint8_t Running; |
| 513 | uint16_t Alpha; |
| 514 | uint32_t FilteredPkgPwr; |
| 515 | uint32_t Limit; |
| 516 | uint32_t Hyst; |
| 517 | uint32_t LimitFromDriver; |
| 518 | SMU7_HystController_Data HystControllerData; |
| 519 | }; |
| 520 | |
| 521 | typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; |
| 522 | |
| 523 | struct SMU7_BapmScoreboard { |
| 524 | uint32_t source_powers[SMU72_DTE_SOURCES]; |
| 525 | uint32_t source_powers_last[SMU72_DTE_SOURCES]; |
| 526 | int32_t entity_temperatures[SMU72_NUM_GPU_TES]; |
| 527 | int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES]; |
| 528 | int32_t Limit; |
| 529 | int32_t Hyst; |
| 530 | int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2]; |
| 531 | int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS]; |
| 532 | uint16_t ConfigTDPPowerScalar; |
| 533 | uint16_t FanSpeedPowerScalar; |
| 534 | uint16_t OverDrivePowerScalar; |
| 535 | uint16_t OverDriveLimitScalar; |
| 536 | uint16_t FinalPowerScalar; |
| 537 | uint8_t VariantID; |
| 538 | uint8_t spare997; |
| 539 | |
| 540 | SMU7_HystController_Data HystControllerData; |
| 541 | |
| 542 | int32_t temperature_gradient_slope; |
| 543 | int32_t temperature_gradient; |
| 544 | uint32_t measured_temperature; |
| 545 | }; |
| 546 | |
| 547 | |
| 548 | typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; |
| 549 | |
| 550 | struct SMU7_AcpiScoreboard { |
| 551 | uint32_t SavedInterruptMask[2]; |
| 552 | uint8_t LastACPIRequest; |
| 553 | uint8_t CgBifResp; |
| 554 | uint8_t RequestType; |
| 555 | uint8_t Padding; |
| 556 | SMU72_Discrete_ACPILevel D0Level; |
| 557 | }; |
| 558 | |
| 559 | typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; |
| 560 | |
| 561 | struct SMU72_Discrete_PmFuses { |
| 562 | /* dw1 */ |
| 563 | uint8_t SviLoadLineEn; |
| 564 | uint8_t SviLoadLineVddC; |
| 565 | uint8_t SviLoadLineTrimVddC; |
| 566 | uint8_t SviLoadLineOffsetVddC; |
| 567 | |
| 568 | /* dw2 */ |
| 569 | uint16_t TDC_VDDC_PkgLimit; |
| 570 | uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; |
| 571 | uint8_t TDC_MAWt; |
| 572 | |
| 573 | /* dw3 */ |
| 574 | uint8_t TdcWaterfallCtl; |
| 575 | uint8_t LPMLTemperatureMin; |
| 576 | uint8_t LPMLTemperatureMax; |
| 577 | uint8_t Reserved; |
| 578 | |
| 579 | /* dw4-dw7 */ |
| 580 | uint8_t LPMLTemperatureScaler[16]; |
| 581 | |
| 582 | /* dw8-dw9 */ |
| 583 | int16_t FuzzyFan_ErrorSetDelta; |
| 584 | int16_t FuzzyFan_ErrorRateSetDelta; |
| 585 | int16_t FuzzyFan_PwmSetDelta; |
| 586 | uint16_t Reserved6; |
| 587 | |
| 588 | /* dw10-dw14 */ |
| 589 | uint8_t GnbLPML[16]; |
| 590 | |
| 591 | /* dw15 */ |
| 592 | uint8_t GnbLPMLMaxVid; |
| 593 | uint8_t GnbLPMLMinVid; |
| 594 | uint8_t Reserved1[2]; |
| 595 | |
| 596 | /* dw16 */ |
| 597 | uint16_t BapmVddCBaseLeakageHiSidd; |
| 598 | uint16_t BapmVddCBaseLeakageLoSidd; |
| 599 | }; |
| 600 | |
| 601 | typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses; |
| 602 | |
| 603 | struct SMU7_Discrete_Log_Header_Table { |
| 604 | uint32_t version; |
| 605 | uint32_t asic_id; |
| 606 | uint16_t flags; |
| 607 | uint16_t entry_size; |
| 608 | uint32_t total_size; |
| 609 | uint32_t num_of_entries; |
| 610 | uint8_t type; |
| 611 | uint8_t mode; |
| 612 | uint8_t filler_0[2]; |
| 613 | uint32_t filler_1[2]; |
| 614 | }; |
| 615 | |
| 616 | typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; |
| 617 | |
| 618 | struct SMU7_Discrete_Log_Cntl { |
| 619 | uint8_t Enabled; |
| 620 | uint8_t Type; |
| 621 | uint8_t padding[2]; |
| 622 | uint32_t BufferSize; |
| 623 | uint32_t SamplesLogged; |
| 624 | uint32_t SampleSize; |
| 625 | uint32_t AddrL; |
| 626 | uint32_t AddrH; |
| 627 | }; |
| 628 | |
| 629 | typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; |
| 630 | |
| 631 | #define CAC_ACC_NW_NUM_OF_SIGNALS 87 |
| 632 | |
| 633 | struct SMU7_Discrete_Cac_Collection_Table { |
| 634 | uint32_t temperature; |
| 635 | uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; |
| 636 | }; |
| 637 | |
| 638 | typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; |
| 639 | |
| 640 | struct SMU7_Discrete_Cac_Verification_Table { |
| 641 | uint32_t VddcTotalPower; |
| 642 | uint32_t VddcLeakagePower; |
| 643 | uint32_t VddcConstantPower; |
| 644 | uint32_t VddcGfxDynamicPower; |
| 645 | uint32_t VddcUvdDynamicPower; |
| 646 | uint32_t VddcVceDynamicPower; |
| 647 | uint32_t VddcAcpDynamicPower; |
| 648 | uint32_t VddcPcieDynamicPower; |
| 649 | uint32_t VddcDceDynamicPower; |
| 650 | uint32_t VddcCurrent; |
| 651 | uint32_t VddcVoltage; |
| 652 | uint32_t VddciTotalPower; |
| 653 | uint32_t VddciLeakagePower; |
| 654 | uint32_t VddciConstantPower; |
| 655 | uint32_t VddciDynamicPower; |
| 656 | uint32_t Vddr1TotalPower; |
| 657 | uint32_t Vddr1LeakagePower; |
| 658 | uint32_t Vddr1ConstantPower; |
| 659 | uint32_t Vddr1DynamicPower; |
| 660 | uint32_t spare[4]; |
| 661 | uint32_t temperature; |
| 662 | }; |
| 663 | |
| 664 | typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; |
| 665 | |
| 666 | struct SMU7_Discrete_Pm_Status_Table { |
| 667 | /* Thermal entities */ |
| 668 | int32_t T_meas_max; |
| 669 | int32_t T_meas_acc; |
| 670 | int32_t T_calc_max; |
| 671 | int32_t T_calc_acc; |
| 672 | uint32_t P_scalar_acc; |
| 673 | uint32_t P_calc_max; |
| 674 | uint32_t P_calc_acc; |
| 675 | |
| 676 | /*Voltage domains */ |
| 677 | uint32_t I_calc_max; |
| 678 | uint32_t I_calc_acc; |
| 679 | uint32_t I_calc_acc_vddci; |
| 680 | uint32_t V_calc_noload_acc; |
| 681 | uint32_t V_calc_load_acc; |
| 682 | uint32_t V_calc_noload_acc_vddci; |
| 683 | uint32_t P_meas_acc; |
| 684 | uint32_t V_meas_noload_acc; |
| 685 | uint32_t V_meas_load_acc; |
| 686 | uint32_t I_meas_acc; |
| 687 | uint32_t P_meas_acc_vddci; |
| 688 | uint32_t V_meas_noload_acc_vddci; |
| 689 | uint32_t V_meas_load_acc_vddci; |
| 690 | uint32_t I_meas_acc_vddci; |
| 691 | |
| 692 | /*Frequency */ |
| 693 | uint16_t Sclk_dpm_residency[8]; |
| 694 | uint16_t Uvd_dpm_residency[8]; |
| 695 | uint16_t Vce_dpm_residency[8]; |
| 696 | uint16_t Mclk_dpm_residency[4]; |
| 697 | |
| 698 | /*Chip */ |
| 699 | uint32_t P_vddci_acc; |
| 700 | uint32_t P_vddr1_acc; |
| 701 | uint32_t P_nte1_acc; |
| 702 | uint32_t PkgPwr_max; |
| 703 | uint32_t PkgPwr_acc; |
| 704 | uint32_t MclkSwitchingTime_max; |
| 705 | uint32_t MclkSwitchingTime_acc; |
| 706 | uint32_t FanPwm_acc; |
| 707 | uint32_t FanRpm_acc; |
| 708 | |
| 709 | uint32_t AccCnt; |
| 710 | }; |
| 711 | |
| 712 | typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; |
| 713 | |
| 714 | /*FIXME THESE NEED TO BE UPDATED */ |
| 715 | #define SMU7_SCLK_CAC 0x561 |
| 716 | #define SMU7_MCLK_CAC 0xF9 |
| 717 | #define SMU7_VCLK_CAC 0x2DE |
| 718 | #define SMU7_DCLK_CAC 0x2DE |
| 719 | #define SMU7_ECLK_CAC 0x25E |
| 720 | #define SMU7_ACLK_CAC 0x25E |
| 721 | #define SMU7_SAMCLK_CAC 0x25E |
| 722 | #define SMU7_DISPCLK_CAC 0x100 |
| 723 | #define SMU7_CAC_CONSTANT 0x2EE3430 |
| 724 | #define SMU7_CAC_CONSTANT_SHIFT 18 |
| 725 | |
| 726 | #define SMU7_VDDCI_MCLK_CONST 1765 |
| 727 | #define SMU7_VDDCI_MCLK_CONST_SHIFT 16 |
| 728 | #define SMU7_VDDCI_VDDCI_CONST 50958 |
| 729 | #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 |
| 730 | #define SMU7_VDDCI_CONST 11781 |
| 731 | |
| 732 | #define SMU7_12C_VDDCI_MCLK_CONST 1623 |
| 733 | #define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15 |
| 734 | #define SMU7_12C_VDDCI_VDDCI_CONST 40088 |
| 735 | #define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13 |
| 736 | #define SMU7_12C_VDDCI_CONST 20856 |
| 737 | |
| 738 | #define SMU7_VDDCI_STROBE_PWR 1331 |
| 739 | |
| 740 | #define SMU7_VDDR1_CONST 693 |
| 741 | #define SMU7_VDDR1_CAC_WEIGHT 20 |
| 742 | #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 |
| 743 | #define SMU7_VDDR1_STROBE_PWR 512 |
| 744 | |
| 745 | #define SMU7_AREA_COEFF_UVD 0xA78 |
| 746 | #define SMU7_AREA_COEFF_VCE 0x190A |
| 747 | #define SMU7_AREA_COEFF_ACP 0x22D1 |
| 748 | #define SMU7_AREA_COEFF_SAMU 0x534 |
| 749 | |
| 750 | /*ThermOutMode values */ |
| 751 | #define SMU7_THERM_OUT_MODE_DISABLE 0x0 |
| 752 | #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 |
| 753 | #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 |
| 754 | |
| 755 | #if !defined(SMC_MICROCODE) |
| 756 | #pragma pack(pop) |
| 757 | #endif |
| 758 | |
| 759 | |
| 760 | #endif |
| 761 | |
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