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Merge tag 'mfd-fixes-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / polaris10_hwmgr.h
CommitLineData
a23eefa2
RZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
2cc0c0b5
FC		 24#ifndef POLARIS10_HWMGR_H
25#define POLARIS10_HWMGR_H
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RZ		 26
27#include "hwmgr.h"
28#include "smu74.h"
29#include "smu74_discrete.h"
30#include "ppatomctrl.h"
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FC		 31#include "polaris10_ppsmc.h"
32#include "polaris10_powertune.h"
a23eefa2 33
2cc0c0b5 34#define POLARIS10_MAX_HARDWARE_POWERLEVELS 2
a23eefa2 35
2cc0c0b5
FC		 36#define POLARIS10_VOLTAGE_CONTROL_NONE 0x0
37#define POLARIS10_VOLTAGE_CONTROL_BY_GPIO 0x1
38#define POLARIS10_VOLTAGE_CONTROL_BY_SVID2 0x2
39#define POLARIS10_VOLTAGE_CONTROL_MERGED 0x3
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RZ		 40
41#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
42#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
43#define DPMTABLE_UPDATE_SCLK 0x00000004
44#define DPMTABLE_UPDATE_MCLK 0x00000008
45
2cc0c0b5 46struct polaris10_performance_level {
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RZ		 47 uint32_t memory_clock;
48 uint32_t engine_clock;
49 uint16_t pcie_gen;
50 uint16_t pcie_lane;
51};
52
2cc0c0b5 53struct polaris10_uvd_clocks {
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RZ		 54 uint32_t vclk;
55 uint32_t dclk;
56};
57
2cc0c0b5 58struct polaris10_vce_clocks {
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RZ		 59 uint32_t evclk;
60 uint32_t ecclk;
61};
62
2cc0c0b5 63struct polaris10_power_state {
a23eefa2 64 uint32_t magic;
2cc0c0b5
FC		 65 struct polaris10_uvd_clocks uvd_clks;
66 struct polaris10_vce_clocks vce_clks;
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RZ		 67 uint32_t sam_clk;
68 uint16_t performance_level_count;
69 bool dc_compatible;
70 uint32_t sclk_threshold;
2cc0c0b5 71 struct polaris10_performance_level performance_levels[POLARIS10_MAX_HARDWARE_POWERLEVELS];
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RZ		 72};
73
2cc0c0b5 74struct polaris10_dpm_level {
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RZ		 75 bool enabled;
76 uint32_t value;
77 uint32_t param1;
78};
79
2cc0c0b5 80#define POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID 5
a23eefa2 81#define MAX_REGULAR_DPM_NUMBER 8
2cc0c0b5 82#define POLARIS10_MINIMUM_ENGINE_CLOCK 2500
a23eefa2 83
2cc0c0b5 84struct polaris10_single_dpm_table {
a23eefa2 85 uint32_t count;
2cc0c0b5 86 struct polaris10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
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RZ		 87};
88
2cc0c0b5
FC		 89struct polaris10_dpm_table {
90 struct polaris10_single_dpm_table sclk_table;
91 struct polaris10_single_dpm_table mclk_table;
92 struct polaris10_single_dpm_table pcie_speed_table;
93 struct polaris10_single_dpm_table vddc_table;
94 struct polaris10_single_dpm_table vddci_table;
95 struct polaris10_single_dpm_table mvdd_table;
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RZ		 96};
97
2cc0c0b5 98struct polaris10_clock_registers {
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RZ		 99 uint32_t vCG_SPLL_FUNC_CNTL;
100 uint32_t vCG_SPLL_FUNC_CNTL_2;
101 uint32_t vCG_SPLL_FUNC_CNTL_3;
102 uint32_t vCG_SPLL_FUNC_CNTL_4;
103 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
104 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
105 uint32_t vDLL_CNTL;
106 uint32_t vMCLK_PWRMGT_CNTL;
107 uint32_t vMPLL_AD_FUNC_CNTL;
108 uint32_t vMPLL_DQ_FUNC_CNTL;
109 uint32_t vMPLL_FUNC_CNTL;
110 uint32_t vMPLL_FUNC_CNTL_1;
111 uint32_t vMPLL_FUNC_CNTL_2;
112 uint32_t vMPLL_SS1;
113 uint32_t vMPLL_SS2;
114};
115
116#define DISABLE_MC_LOADMICROCODE 1
117#define DISABLE_MC_CFGPROGRAMMING 2
118
2cc0c0b5 119struct polaris10_voltage_smio_registers {
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RZ		 120 uint32_t vS0_VID_LOWER_SMIO_CNTL;
121};
122
2cc0c0b5 123#define POLARIS10_MAX_LEAKAGE_COUNT 8
a23eefa2 124
2cc0c0b5 125struct polaris10_leakage_voltage {
a23eefa2 126 uint16_t count;
2cc0c0b5
FC		 127 uint16_t leakage_id[POLARIS10_MAX_LEAKAGE_COUNT];
128 uint16_t actual_voltage[POLARIS10_MAX_LEAKAGE_COUNT];
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RZ		 129};
130
2cc0c0b5 131struct polaris10_vbios_boot_state {
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RZ		 132 uint16_t mvdd_bootup_value;
133 uint16_t vddc_bootup_value;
134 uint16_t vddci_bootup_value;
135 uint32_t sclk_bootup_value;
136 uint32_t mclk_bootup_value;
137 uint16_t pcie_gen_bootup_value;
138 uint16_t pcie_lane_bootup_value;
139};
140
141/* Ultra Low Voltage parameter structure */
2cc0c0b5 142struct polaris10_ulv_parm {
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RZ		 143 bool ulv_supported;
144 uint32_t cg_ulv_parameter;
145 uint32_t ulv_volt_change_delay;
2cc0c0b5 146 struct polaris10_performance_level ulv_power_level;
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RZ		 147};
148
2cc0c0b5 149struct polaris10_display_timing {
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RZ		 150 uint32_t min_clock_in_sr;
151 uint32_t num_existing_displays;
152};
153
2cc0c0b5 154struct polaris10_dpmlevel_enable_mask {
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RZ		 155 uint32_t uvd_dpm_enable_mask;
156 uint32_t vce_dpm_enable_mask;
157 uint32_t acp_dpm_enable_mask;
158 uint32_t samu_dpm_enable_mask;
159 uint32_t sclk_dpm_enable_mask;
160 uint32_t mclk_dpm_enable_mask;
161 uint32_t pcie_dpm_enable_mask;
162};
163
2cc0c0b5 164struct polaris10_pcie_perf_range {
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RZ		 165 uint16_t max;
166 uint16_t min;
167};
2cc0c0b5 168struct polaris10_range_table {
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RZ		 169 uint32_t trans_lower_frequency; /* in 10khz */
170 uint32_t trans_upper_frequency;
171};
172
2cc0c0b5
FC		 173struct polaris10_hwmgr {
174 struct polaris10_dpm_table dpm_table;
175 struct polaris10_dpm_table golden_dpm_table;
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RZ		 176 SMU74_Discrete_DpmTable smc_state_table;
177 struct SMU74_Discrete_Ulv ulv_setting;
178
2cc0c0b5 179 struct polaris10_range_table range_table[NUM_SCLK_RANGE];
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RZ		 180 uint32_t voting_rights_clients0;
181 uint32_t voting_rights_clients1;
182 uint32_t voting_rights_clients2;
183 uint32_t voting_rights_clients3;
184 uint32_t voting_rights_clients4;
185 uint32_t voting_rights_clients5;
186 uint32_t voting_rights_clients6;
187 uint32_t voting_rights_clients7;
188 uint32_t static_screen_threshold_unit;
189 uint32_t static_screen_threshold;
190 uint32_t voltage_control;
191 uint32_t vddc_vddci_delta;
192
193 uint32_t active_auto_throttle_sources;
194
2cc0c0b5
FC		 195 struct polaris10_clock_registers clock_registers;
196 struct polaris10_voltage_smio_registers voltage_smio_registers;
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RZ		 197
198 bool is_memory_gddr5;
199 uint16_t acpi_vddc;
200 bool pspp_notify_required;
201 uint16_t force_pcie_gen;
202 uint16_t acpi_pcie_gen;
203 uint32_t pcie_gen_cap;
204 uint32_t pcie_lane_cap;
205 uint32_t pcie_spc_cap;
2cc0c0b5
FC		 206 struct polaris10_leakage_voltage vddc_leakage;
207 struct polaris10_leakage_voltage Vddci_leakage;
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RZ		 208
209 uint32_t mvdd_control;
210 uint32_t vddc_mask_low;
211 uint32_t mvdd_mask_low;
212 uint16_t max_vddc_in_pptable;
213 uint16_t min_vddc_in_pptable;
214 uint16_t max_vddci_in_pptable;
215 uint16_t min_vddci_in_pptable;
216 uint32_t mclk_strobe_mode_threshold;
217 uint32_t mclk_stutter_mode_threshold;
218 uint32_t mclk_edc_enable_threshold;
219 uint32_t mclk_edcwr_enable_threshold;
220 bool is_uvd_enabled;
2cc0c0b5 221 struct polaris10_vbios_boot_state vbios_boot_state;
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RZ		 222
223 bool pcie_performance_request;
224 bool battery_state;
225 bool is_tlu_enabled;
226
227 /* ---- SMC SRAM Address of firmware header tables ---- */
228 uint32_t sram_end;
229 uint32_t dpm_table_start;
230 uint32_t soft_regs_start;
231 uint32_t mc_reg_table_start;
232 uint32_t fan_table_start;
233 uint32_t arb_table_start;
234
235 /* ---- Stuff originally coming from Evergreen ---- */
236 uint32_t vddci_control;
237 struct pp_atomctrl_voltage_table vddc_voltage_table;
238 struct pp_atomctrl_voltage_table vddci_voltage_table;
239 struct pp_atomctrl_voltage_table mvdd_voltage_table;
240
241 uint32_t mgcg_cgtt_local2;
242 uint32_t mgcg_cgtt_local3;
243 uint32_t gpio_debug;
244 uint32_t mc_micro_code_feature;
245 uint32_t highest_mclk;
246 uint16_t acpi_vddci;
247 uint8_t mvdd_high_index;
248 uint8_t mvdd_low_index;
249 bool dll_default_on;
250 bool performance_request_registered;
251
252 /* ---- Low Power Features ---- */
2cc0c0b5 253 struct polaris10_ulv_parm ulv;
a23eefa2
RZ		 254
255 /* ---- CAC Stuff ---- */
256 uint32_t cac_table_start;
257 bool cac_configuration_required;
258 bool driver_calculate_cac_leakage;
259 bool cac_enabled;
260
261 /* ---- DPM2 Parameters ---- */
262 uint32_t power_containment_features;
263 bool enable_dte_feature;
264 bool enable_tdc_limit_feature;
265 bool enable_pkg_pwr_tracking_feature;
266 bool disable_uvd_power_tune_feature;
909a0631 267 const struct polaris10_pt_defaults *power_tune_defaults;
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RZ		 268 struct SMU74_Discrete_PmFuses power_tune_table;
269 uint32_t dte_tj_offset;
270 uint32_t fast_watermark_threshold;
271
272 /* ---- Phase Shedding ---- */
273 bool vddc_phase_shed_control;
274
275 /* ---- DI/DT ---- */
2cc0c0b5 276 struct polaris10_display_timing display_timing;
e85c7d66 277 uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK];
a23eefa2
RZ		 278
279 /* ---- Thermal Temperature Setting ---- */
2cc0c0b5 280 struct polaris10_dpmlevel_enable_mask dpm_level_enable_mask;
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RZ		 281 uint32_t need_update_smu7_dpm_table;
282 uint32_t sclk_dpm_key_disabled;
283 uint32_t mclk_dpm_key_disabled;
284 uint32_t pcie_dpm_key_disabled;
285 uint32_t min_engine_clocks;
2cc0c0b5
FC		 286 struct polaris10_pcie_perf_range pcie_gen_performance;
287 struct polaris10_pcie_perf_range pcie_lane_performance;
288 struct polaris10_pcie_perf_range pcie_gen_power_saving;
289 struct polaris10_pcie_perf_range pcie_lane_power_saving;
a23eefa2
RZ		 290 bool use_pcie_performance_levels;
291 bool use_pcie_power_saving_levels;
292 uint32_t activity_target[SMU74_MAX_LEVELS_GRAPHICS];
293 uint32_t mclk_activity_target;
294 uint32_t mclk_dpm0_activity_target;
295 uint32_t low_sclk_interrupt_threshold;
296 uint32_t last_mclk_dpm_enable_mask;
297 bool uvd_enabled;
298
299 /* ---- Power Gating States ---- */
300 bool uvd_power_gated;
301 bool vce_power_gated;
302 bool samu_power_gated;
303 bool need_long_memory_training;
304
305 /* Application power optimization parameters */
306 bool update_up_hyst;
307 bool update_down_hyst;
308 uint32_t down_hyst;
309 uint32_t up_hyst;
310 uint32_t disable_dpm_mask;
311 bool apply_optimized_settings;
a72d5604
EH		 312
313 /* soft pptable for re-uploading into smu */
314 void *soft_pp_table;
432c3a3c
RZ		 315
316 uint32_t avfs_vdroop_override_setting;
317 bool apply_avfs_cks_off_voltage;
a23eefa2
RZ		 318};
319
320/* To convert to Q8.8 format for firmware */
2cc0c0b5
FC		 321#define POLARIS10_Q88_FORMAT_CONVERSION_UNIT 256
322
323enum Polaris10_I2CLineID {
324 Polaris10_I2CLineID_DDC1 = 0x90,
325 Polaris10_I2CLineID_DDC2 = 0x91,
326 Polaris10_I2CLineID_DDC3 = 0x92,
327 Polaris10_I2CLineID_DDC4 = 0x93,
328 Polaris10_I2CLineID_DDC5 = 0x94,
329 Polaris10_I2CLineID_DDC6 = 0x95,
330 Polaris10_I2CLineID_SCLSDA = 0x96,
331 Polaris10_I2CLineID_DDCVGA = 0x97
a23eefa2
RZ		 332};
333
2cc0c0b5
FC		 334#define POLARIS10_I2C_DDC1DATA 0
335#define POLARIS10_I2C_DDC1CLK 1
336#define POLARIS10_I2C_DDC2DATA 2
337#define POLARIS10_I2C_DDC2CLK 3
338#define POLARIS10_I2C_DDC3DATA 4
339#define POLARIS10_I2C_DDC3CLK 5
340#define POLARIS10_I2C_SDA 40
341#define POLARIS10_I2C_SCL 41
342#define POLARIS10_I2C_DDC4DATA 65
343#define POLARIS10_I2C_DDC4CLK 66
344#define POLARIS10_I2C_DDC5DATA 0x48
345#define POLARIS10_I2C_DDC5CLK 0x49
346#define POLARIS10_I2C_DDC6DATA 0x4a
347#define POLARIS10_I2C_DDC6CLK 0x4b
348#define POLARIS10_I2C_DDCVGADATA 0x4c
349#define POLARIS10_I2C_DDCVGACLK 0x4d
350
351#define POLARIS10_UNUSED_GPIO_PIN 0x7F
352
353int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
354
355int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
356int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
357int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
92c6d645 358
a23eefa2
RZ		 359#endif
360
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