[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / amd_powerplay.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/slab.h>
#include "amd_shared.h"
#include "amd_powerplay.h"
#include "pp_instance.h"
#include "power_state.h"
#include "eventmanager.h"

#define PP_CHECK(handle)						\
	do {								\
		if ((handle) == NULL || (handle)->pp_valid != PP_VALID)	\
			return -EINVAL;					\
	} while (0)

static int pp_early_init(void *handle)
{
	return 0;
}

static int pp_sw_init(void *handle)
{
	struct pp_instance *pp_handle;
	struct pp_hwmgr  *hwmgr;
	int ret = 0;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	hwmgr = pp_handle->hwmgr;

	if (hwmgr == NULL || hwmgr->pptable_func == NULL ||
	    hwmgr->hwmgr_func == NULL ||
	    hwmgr->pptable_func->pptable_init == NULL ||
	    hwmgr->hwmgr_func->backend_init == NULL)
		return -EINVAL;

	ret = hwmgr->pptable_func->pptable_init(hwmgr);

	if (ret == 0)
		ret = hwmgr->hwmgr_func->backend_init(hwmgr);

	if (ret)
		printk("amdgpu: powerplay initialization failed\n");
	else
		printk("amdgpu: powerplay initialized\n");

	return ret;
}

static int pp_sw_fini(void *handle)
{
	struct pp_instance *pp_handle;
	struct pp_hwmgr  *hwmgr;
	int ret = 0;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	hwmgr = pp_handle->hwmgr;

	if (hwmgr != NULL || hwmgr->hwmgr_func != NULL ||
	    hwmgr->hwmgr_func->backend_fini != NULL)
		ret = hwmgr->hwmgr_func->backend_fini(hwmgr);

	return ret;
}

static int pp_hw_init(void *handle)
{
	struct pp_instance *pp_handle;
	struct pp_smumgr *smumgr;
	struct pp_eventmgr *eventmgr;
	int ret = 0;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	smumgr = pp_handle->smu_mgr;

	if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
		smumgr->smumgr_funcs->smu_init == NULL ||
		smumgr->smumgr_funcs->start_smu == NULL)
		return -EINVAL;

	ret = smumgr->smumgr_funcs->smu_init(smumgr);
	if (ret) {
		printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
		return ret;
	}

	ret = smumgr->smumgr_funcs->start_smu(smumgr);
	if (ret) {
		printk(KERN_ERR "[ powerplay ] smc start failed\n");
		smumgr->smumgr_funcs->smu_fini(smumgr);
		return ret;
	}

	hw_init_power_state_table(pp_handle->hwmgr);
	eventmgr = pp_handle->eventmgr;

	if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
		return -EINVAL;

	ret = eventmgr->pp_eventmgr_init(eventmgr);
	return 0;
}

static int pp_hw_fini(void *handle)
{
	struct pp_instance *pp_handle;
	struct pp_smumgr *smumgr;
	struct pp_eventmgr *eventmgr;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	eventmgr = pp_handle->eventmgr;

	if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL)
		eventmgr->pp_eventmgr_fini(eventmgr);

	smumgr = pp_handle->smu_mgr;

	if (smumgr != NULL || smumgr->smumgr_funcs != NULL ||
		smumgr->smumgr_funcs->smu_fini != NULL)
		smumgr->smumgr_funcs->smu_fini(smumgr);

	return 0;
}

static bool pp_is_idle(void *handle)
{
	return 0;
}

static int pp_wait_for_idle(void *handle)
{
	return 0;
}

static int pp_sw_reset(void *handle)
{
	return 0;
}

static void pp_print_status(void *handle)
{

}

static int pp_set_clockgating_state(void *handle,
				    enum amd_clockgating_state state)
{
	return 0;
}

static int pp_set_powergating_state(void *handle,
				    enum amd_powergating_state state)
{
	return 0;
}

static int pp_suspend(void *handle)
{
	struct pp_instance *pp_handle;
	struct pp_eventmgr *eventmgr;
	struct pem_event_data event_data = { {0} };

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	eventmgr = pp_handle->eventmgr;
	pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
	return 0;
}

static int pp_resume(void *handle)
{
	struct pp_instance *pp_handle;
	struct pp_eventmgr *eventmgr;
	struct pem_event_data event_data = { {0} };
	struct pp_smumgr *smumgr;
	int ret;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	smumgr = pp_handle->smu_mgr;

	if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
		smumgr->smumgr_funcs->start_smu == NULL)
		return -EINVAL;

	ret = smumgr->smumgr_funcs->start_smu(smumgr);
	if (ret) {
		printk(KERN_ERR "[ powerplay ] smc start failed\n");
		smumgr->smumgr_funcs->smu_fini(smumgr);
		return ret;
	}

	eventmgr = pp_handle->eventmgr;
	pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);

	return 0;
}

const struct amd_ip_funcs pp_ip_funcs = {
	.early_init = pp_early_init,
	.late_init = NULL,
	.sw_init = pp_sw_init,
	.sw_fini = pp_sw_fini,
	.hw_init = pp_hw_init,
	.hw_fini = pp_hw_fini,
	.suspend = pp_suspend,
	.resume = pp_resume,
	.is_idle = pp_is_idle,
	.wait_for_idle = pp_wait_for_idle,
	.soft_reset = pp_sw_reset,
	.print_status = pp_print_status,
	.set_clockgating_state = pp_set_clockgating_state,
	.set_powergating_state = pp_set_powergating_state,
};

static int pp_dpm_load_fw(void *handle)
{
	return 0;
}

static int pp_dpm_fw_loading_complete(void *handle)
{
	return 0;
}

static int pp_dpm_force_performance_level(void *handle,
					enum amd_dpm_forced_level level)
{
	struct pp_instance *pp_handle;
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;

	hwmgr = pp_handle->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	    hwmgr->hwmgr_func->force_dpm_level == NULL)
		return -EINVAL;

	hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);

	return 0;
}

static enum amd_dpm_forced_level pp_dpm_get_performance_level(
								void *handle)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL)
		return -EINVAL;

	return (((struct pp_instance *)handle)->hwmgr->dpm_level);
}

static int pp_dpm_get_sclk(void *handle, bool low)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	    hwmgr->hwmgr_func->get_sclk == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
}

static int pp_dpm_get_mclk(void *handle, bool low)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	    hwmgr->hwmgr_func->get_mclk == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
}

static int pp_dpm_powergate_vce(void *handle, bool gate)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	    hwmgr->hwmgr_func->powergate_vce == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
}

static int pp_dpm_powergate_uvd(void *handle, bool gate)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	    hwmgr->hwmgr_func->powergate_uvd == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
}

static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
{
	switch (state) {
	case POWER_STATE_TYPE_BATTERY:
		return PP_StateUILabel_Battery;
	case POWER_STATE_TYPE_BALANCED:
		return PP_StateUILabel_Balanced;
	case POWER_STATE_TYPE_PERFORMANCE:
		return PP_StateUILabel_Performance;
	default:
		return PP_StateUILabel_None;
	}
}

int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
{
	int ret = 0;
	struct pp_instance *pp_handle;
	struct pem_event_data data = { {0} };

	pp_handle = (struct pp_instance *)handle;

	if (pp_handle == NULL)
		return -EINVAL;

	switch (event_id) {
	case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
		break;
	case AMD_PP_EVENT_ENABLE_USER_STATE:
	{
		enum amd_pm_state_type  ps;

		if (input == NULL)
			return -EINVAL;
		ps = *(unsigned long *)input;

		data.requested_ui_label = power_state_convert(ps);
		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
		break;
	}
	case AMD_PP_EVENT_COMPLETE_INIT:
		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
		break;
	default:
		break;
	}
	return ret;
}

enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
{
	struct pp_hwmgr *hwmgr;
	struct pp_power_state *state;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->current_ps == NULL)
		return -EINVAL;

	state = hwmgr->current_ps;

	switch (state->classification.ui_label) {
	case PP_StateUILabel_Battery:
		return POWER_STATE_TYPE_BATTERY;
	case PP_StateUILabel_Balanced:
		return POWER_STATE_TYPE_BALANCED;
	case PP_StateUILabel_Performance:
		return POWER_STATE_TYPE_PERFORMANCE;
	default:
		return POWER_STATE_TYPE_DEFAULT;
	}
}

static void
pp_debugfs_print_current_performance_level(void *handle,
					       struct seq_file *m)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	  hwmgr->hwmgr_func->print_current_perforce_level == NULL)
		return;

	hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
}

static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	  hwmgr->hwmgr_func->set_fan_control_mode == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
}

static int pp_dpm_get_fan_control_mode(void *handle)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	  hwmgr->hwmgr_func->get_fan_control_mode == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
}

static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	  hwmgr->hwmgr_func->set_fan_speed_percent == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
}

static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	  hwmgr->hwmgr_func->get_fan_speed_percent == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
}

static int pp_dpm_get_temperature(void *handle)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
	  hwmgr->hwmgr_func->get_temperature == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_temperature(hwmgr);
}

const struct amd_powerplay_funcs pp_dpm_funcs = {
	.get_temperature = pp_dpm_get_temperature,
	.load_firmware = pp_dpm_load_fw,
	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
	.force_performance_level = pp_dpm_force_performance_level,
	.get_performance_level = pp_dpm_get_performance_level,
	.get_current_power_state = pp_dpm_get_current_power_state,
	.get_sclk = pp_dpm_get_sclk,
	.get_mclk = pp_dpm_get_mclk,
	.powergate_vce = pp_dpm_powergate_vce,
	.powergate_uvd = pp_dpm_powergate_uvd,
	.dispatch_tasks = pp_dpm_dispatch_tasks,
	.print_current_performance_level = pp_debugfs_print_current_performance_level,
	.set_fan_control_mode = pp_dpm_set_fan_control_mode,
	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
	.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
	.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
};

static int amd_pp_instance_init(struct amd_pp_init *pp_init,
				struct amd_powerplay *amd_pp)
{
	int ret;
	struct pp_instance *handle;

	handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
	if (handle == NULL)
		return -ENOMEM;

	handle->pp_valid = PP_VALID;

	ret = smum_init(pp_init, handle);
	if (ret)
		goto fail_smum;

	ret = hwmgr_init(pp_init, handle);
	if (ret)
		goto fail_hwmgr;

	ret = eventmgr_init(handle);
	if (ret)
		goto fail_eventmgr;

	amd_pp->pp_handle = handle;
	return 0;

fail_eventmgr:
	hwmgr_fini(handle->hwmgr);
fail_hwmgr:
	smum_fini(handle->smu_mgr);
fail_smum:
	kfree(handle);
	return ret;
}

static int amd_pp_instance_fini(void *handle)
{
	struct pp_instance *instance = (struct pp_instance *)handle;

	if (instance == NULL)
		return -EINVAL;

	eventmgr_fini(instance->eventmgr);

	hwmgr_fini(instance->hwmgr);

	smum_fini(instance->smu_mgr);

	kfree(handle);
	return 0;
}

int amd_powerplay_init(struct amd_pp_init *pp_init,
		       struct amd_powerplay *amd_pp)
{
	int ret;

	if (pp_init == NULL || amd_pp == NULL)
		return -EINVAL;

	ret = amd_pp_instance_init(pp_init, amd_pp);

	if (ret)
		return ret;

	amd_pp->ip_funcs = &pp_ip_funcs;
	amd_pp->pp_funcs = &pp_dpm_funcs;

	return 0;
}

int amd_powerplay_fini(void *handle)
{
	amd_pp_instance_fini(handle);

	return 0;
}

/* export this function to DAL */

int amd_powerplay_display_configuration_change(void *handle, const void *input)
{
	struct pp_hwmgr  *hwmgr;
	const struct amd_pp_display_configuration *display_config = input;

	PP_CHECK((struct pp_instance *)handle);

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	phm_store_dal_configuration_data(hwmgr, display_config);

	return 0;
}

int amd_powerplay_get_display_power_level(void *handle,
		struct amd_pp_dal_clock_info *output)
{
	struct pp_hwmgr  *hwmgr;

	PP_CHECK((struct pp_instance *)handle);

	if (output == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	return phm_get_dal_power_level(hwmgr, output);
}
Commit	Line	Data
1f7371b2 AD	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/types.h>
	24	#include <linux/kernel.h>
	25	#include <linux/gfp.h>
ac885b3a	26	#include <linux/slab.h>
1f7371b2 AD	27	#include "amd_shared.h"
1f7371b2 AD	28	#include "amd_powerplay.h"
ac885b3a	29	#include "pp_instance.h"
577bbe01 RZ	30	#include "power_state.h"
577bbe01 RZ	31	#include "eventmanager.h"
1f7371b2	32
a969e163 RZ	33	#define PP_CHECK(handle) \
	34	do { \
	35	if ((handle) == NULL \|\| (handle)->pp_valid != PP_VALID) \
	36	return -EINVAL; \
	37	} while (0)
	38
1f7371b2 AD	39	static int pp_early_init(void *handle)
	40	{
	41	return 0;
	42	}
	43
	44	static int pp_sw_init(void *handle)
	45	{
3bace359 JZ	46	struct pp_instance *pp_handle;
	47	struct pp_hwmgr *hwmgr;
	48	int ret = 0;
	49
	50	if (handle == NULL)
	51	return -EINVAL;
	52
	53	pp_handle = (struct pp_instance *)handle;
	54	hwmgr = pp_handle->hwmgr;
	55
	56	if (hwmgr == NULL \|\| hwmgr->pptable_func == NULL \|\|
	57	hwmgr->hwmgr_func == NULL \|\|
	58	hwmgr->pptable_func->pptable_init == NULL \|\|
	59	hwmgr->hwmgr_func->backend_init == NULL)
	60	return -EINVAL;
	61
	62	ret = hwmgr->pptable_func->pptable_init(hwmgr);
e92a0370	63
3bace359 JZ	64	if (ret == 0)
	65	ret = hwmgr->hwmgr_func->backend_init(hwmgr);
	66
9441f964 AD	67	if (ret)
	68	printk("amdgpu: powerplay initialization failed\n");
	69	else
	70	printk("amdgpu: powerplay initialized\n");
	71
3bace359	72	return ret;
1f7371b2 AD	73	}
	74
	75	static int pp_sw_fini(void *handle)
	76	{
3bace359 JZ	77	struct pp_instance *pp_handle;
	78	struct pp_hwmgr *hwmgr;
	79	int ret = 0;
	80
	81	if (handle == NULL)
	82	return -EINVAL;
	83
	84	pp_handle = (struct pp_instance *)handle;
	85	hwmgr = pp_handle->hwmgr;
	86
	87	if (hwmgr != NULL \|\| hwmgr->hwmgr_func != NULL \|\|
	88	hwmgr->hwmgr_func->backend_fini != NULL)
	89	ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
	90
	91	return ret;
1f7371b2 AD	92	}
	93
	94	static int pp_hw_init(void *handle)
	95	{
ac885b3a JZ	96	struct pp_instance *pp_handle;
ac885b3a JZ	97	struct pp_smumgr *smumgr;
e92a0370	98	struct pp_eventmgr *eventmgr;
ac885b3a JZ	99	int ret = 0;
	100
	101	if (handle == NULL)
	102	return -EINVAL;
	103
	104	pp_handle = (struct pp_instance *)handle;
	105	smumgr = pp_handle->smu_mgr;
	106
	107	if (smumgr == NULL \|\| smumgr->smumgr_funcs == NULL \|\|
	108	smumgr->smumgr_funcs->smu_init == NULL \|\|
	109	smumgr->smumgr_funcs->start_smu == NULL)
	110	return -EINVAL;
	111
	112	ret = smumgr->smumgr_funcs->smu_init(smumgr);
	113	if (ret) {
	114	printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
	115	return ret;
	116	}
	117
	118	ret = smumgr->smumgr_funcs->start_smu(smumgr);
	119	if (ret) {
	120	printk(KERN_ERR "[ powerplay ] smc start failed\n");
	121	smumgr->smumgr_funcs->smu_fini(smumgr);
	122	return ret;
	123	}
e92a0370	124
3bace359	125	hw_init_power_state_table(pp_handle->hwmgr);
e92a0370	126	eventmgr = pp_handle->eventmgr;
3bace359	127
e92a0370 RZ	128	if (eventmgr == NULL \|\| eventmgr->pp_eventmgr_init == NULL)
	129	return -EINVAL;
	130
	131	ret = eventmgr->pp_eventmgr_init(eventmgr);
1f7371b2 AD	132	return 0;
	133	}
	134
	135	static int pp_hw_fini(void *handle)
	136	{
ac885b3a JZ	137	struct pp_instance *pp_handle;
ac885b3a JZ	138	struct pp_smumgr *smumgr;
e92a0370	139	struct pp_eventmgr *eventmgr;
ac885b3a JZ	140
	141	if (handle == NULL)
	142	return -EINVAL;
	143
	144	pp_handle = (struct pp_instance *)handle;
e92a0370 RZ	145	eventmgr = pp_handle->eventmgr;
	146
	147	if (eventmgr != NULL \|\| eventmgr->pp_eventmgr_fini != NULL)
	148	eventmgr->pp_eventmgr_fini(eventmgr);
	149
ac885b3a JZ	150	smumgr = pp_handle->smu_mgr;
	151
	152	if (smumgr != NULL \|\| smumgr->smumgr_funcs != NULL \|\|
	153	smumgr->smumgr_funcs->smu_fini != NULL)
	154	smumgr->smumgr_funcs->smu_fini(smumgr);
	155
1f7371b2 AD	156	return 0;
	157	}
	158
	159	static bool pp_is_idle(void *handle)
	160	{
	161	return 0;
	162	}
	163
	164	static int pp_wait_for_idle(void *handle)
	165	{
	166	return 0;
	167	}
	168
	169	static int pp_sw_reset(void *handle)
	170	{
	171	return 0;
	172	}
	173
	174	static void pp_print_status(void *handle)
	175	{
	176
	177	}
	178
	179	static int pp_set_clockgating_state(void *handle,
	180	enum amd_clockgating_state state)
	181	{
	182	return 0;
	183	}
	184
	185	static int pp_set_powergating_state(void *handle,
	186	enum amd_powergating_state state)
	187	{
	188	return 0;
	189	}
	190
	191	static int pp_suspend(void *handle)
	192	{
577bbe01 RZ	193	struct pp_instance *pp_handle;
	194	struct pp_eventmgr *eventmgr;
	195	struct pem_event_data event_data = { {0} };
	196
	197	if (handle == NULL)
	198	return -EINVAL;
	199
	200	pp_handle = (struct pp_instance *)handle;
	201	eventmgr = pp_handle->eventmgr;
	202	pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
1f7371b2 AD	203	return 0;
	204	}
	205
	206	static int pp_resume(void *handle)
	207	{
577bbe01 RZ	208	struct pp_instance *pp_handle;
	209	struct pp_eventmgr *eventmgr;
	210	struct pem_event_data event_data = { {0} };
e0b71a7e RZ	211	struct pp_smumgr *smumgr;
e0b71a7e RZ	212	int ret;
577bbe01 RZ	213
	214	if (handle == NULL)
	215	return -EINVAL;
	216
	217	pp_handle = (struct pp_instance *)handle;
e0b71a7e RZ	218	smumgr = pp_handle->smu_mgr;
	219
	220	if (smumgr == NULL \|\| smumgr->smumgr_funcs == NULL \|\|
	221	smumgr->smumgr_funcs->start_smu == NULL)
	222	return -EINVAL;
	223
	224	ret = smumgr->smumgr_funcs->start_smu(smumgr);
	225	if (ret) {
	226	printk(KERN_ERR "[ powerplay ] smc start failed\n");
	227	smumgr->smumgr_funcs->smu_fini(smumgr);
	228	return ret;
	229	}
	230
577bbe01 RZ	231	eventmgr = pp_handle->eventmgr;
577bbe01 RZ	232	pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
e0b71a7e	233
1f7371b2 AD	234	return 0;
	235	}
	236
	237	const struct amd_ip_funcs pp_ip_funcs = {
	238	.early_init = pp_early_init,
	239	.late_init = NULL,
	240	.sw_init = pp_sw_init,
	241	.sw_fini = pp_sw_fini,
	242	.hw_init = pp_hw_init,
	243	.hw_fini = pp_hw_fini,
	244	.suspend = pp_suspend,
	245	.resume = pp_resume,
	246	.is_idle = pp_is_idle,
	247	.wait_for_idle = pp_wait_for_idle,
	248	.soft_reset = pp_sw_reset,
	249	.print_status = pp_print_status,
	250	.set_clockgating_state = pp_set_clockgating_state,
	251	.set_powergating_state = pp_set_powergating_state,
	252	};
	253
	254	static int pp_dpm_load_fw(void *handle)
	255	{
	256	return 0;
	257	}
	258
	259	static int pp_dpm_fw_loading_complete(void *handle)
	260	{
	261	return 0;
	262	}
	263
	264	static int pp_dpm_force_performance_level(void *handle,
	265	enum amd_dpm_forced_level level)
	266	{
577bbe01 RZ	267	struct pp_instance *pp_handle;
	268	struct pp_hwmgr *hwmgr;
	269
	270	if (handle == NULL)
	271	return -EINVAL;
	272
	273	pp_handle = (struct pp_instance *)handle;
	274
	275	hwmgr = pp_handle->hwmgr;
	276
	277	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	278	hwmgr->hwmgr_func->force_dpm_level == NULL)
	279	return -EINVAL;
	280
	281	hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
	282
1f7371b2 AD	283	return 0;
1f7371b2 AD	284	}
577bbe01	285
1f7371b2 AD	286	static enum amd_dpm_forced_level pp_dpm_get_performance_level(
	287	void *handle)
	288	{
577bbe01 RZ	289	struct pp_hwmgr *hwmgr;
	290
	291	if (handle == NULL)
	292	return -EINVAL;
	293
	294	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	295
	296	if (hwmgr == NULL)
	297	return -EINVAL;
	298
	299	return (((struct pp_instance *)handle)->hwmgr->dpm_level);
1f7371b2	300	}
577bbe01	301
1f7371b2 AD	302	static int pp_dpm_get_sclk(void *handle, bool low)
1f7371b2 AD	303	{
577bbe01 RZ	304	struct pp_hwmgr *hwmgr;
	305
	306	if (handle == NULL)
	307	return -EINVAL;
	308
	309	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	310
	311	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	312	hwmgr->hwmgr_func->get_sclk == NULL)
	313	return -EINVAL;
	314
	315	return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
1f7371b2	316	}
577bbe01	317
1f7371b2 AD	318	static int pp_dpm_get_mclk(void *handle, bool low)
1f7371b2 AD	319	{
577bbe01 RZ	320	struct pp_hwmgr *hwmgr;
	321
	322	if (handle == NULL)
	323	return -EINVAL;
	324
	325	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	326
	327	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	328	hwmgr->hwmgr_func->get_mclk == NULL)
	329	return -EINVAL;
	330
	331	return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
1f7371b2	332	}
577bbe01	333
1f7371b2 AD	334	static int pp_dpm_powergate_vce(void *handle, bool gate)
1f7371b2 AD	335	{
577bbe01 RZ	336	struct pp_hwmgr *hwmgr;
	337
	338	if (handle == NULL)
	339	return -EINVAL;
	340
	341	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	342
	343	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	344	hwmgr->hwmgr_func->powergate_vce == NULL)
	345	return -EINVAL;
	346
	347	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
1f7371b2	348	}
577bbe01	349
1f7371b2 AD	350	static int pp_dpm_powergate_uvd(void *handle, bool gate)
1f7371b2 AD	351	{
577bbe01 RZ	352	struct pp_hwmgr *hwmgr;
	353
	354	if (handle == NULL)
	355	return -EINVAL;
	356
	357	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	358
	359	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	360	hwmgr->hwmgr_func->powergate_uvd == NULL)
	361	return -EINVAL;
	362
	363	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	364	}
	365
	366	static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
	367	{
	368	switch (state) {
	369	case POWER_STATE_TYPE_BATTERY:
	370	return PP_StateUILabel_Battery;
	371	case POWER_STATE_TYPE_BALANCED:
	372	return PP_StateUILabel_Balanced;
	373	case POWER_STATE_TYPE_PERFORMANCE:
	374	return PP_StateUILabel_Performance;
	375	default:
	376	return PP_StateUILabel_None;
	377	}
1f7371b2 AD	378	}
	379
	380	int pp_dpm_dispatch_tasks(void handle, enum amd_pp_event event_id, void input, void *output)
	381	{
577bbe01 RZ	382	int ret = 0;
	383	struct pp_instance *pp_handle;
	384	struct pem_event_data data = { {0} };
	385
	386	pp_handle = (struct pp_instance *)handle;
	387
	388	if (pp_handle == NULL)
	389	return -EINVAL;
	390
	391	switch (event_id) {
	392	case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
	393	ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
	394	break;
	395	case AMD_PP_EVENT_ENABLE_USER_STATE:
	396	{
	397	enum amd_pm_state_type ps;
	398
	399	if (input == NULL)
	400	return -EINVAL;
	401	ps = (unsigned long )input;
	402
	403	data.requested_ui_label = power_state_convert(ps);
	404	ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
dc26a2a2	405	break;
577bbe01	406	}
dc26a2a2 RZ	407	case AMD_PP_EVENT_COMPLETE_INIT:
	408	ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
	409	break;
577bbe01 RZ	410	default:
	411	break;
	412	}
	413	return ret;
1f7371b2	414	}
577bbe01	415
1f7371b2 AD	416	enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
1f7371b2 AD	417	{
577bbe01 RZ	418	struct pp_hwmgr *hwmgr;
	419	struct pp_power_state *state;
	420
	421	if (handle == NULL)
	422	return -EINVAL;
	423
	424	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	425
	426	if (hwmgr == NULL \|\| hwmgr->current_ps == NULL)
	427	return -EINVAL;
	428
	429	state = hwmgr->current_ps;
	430
	431	switch (state->classification.ui_label) {
	432	case PP_StateUILabel_Battery:
	433	return POWER_STATE_TYPE_BATTERY;
	434	case PP_StateUILabel_Balanced:
	435	return POWER_STATE_TYPE_BALANCED;
	436	case PP_StateUILabel_Performance:
	437	return POWER_STATE_TYPE_PERFORMANCE;
	438	default:
	439	return POWER_STATE_TYPE_DEFAULT;
	440	}
1f7371b2	441	}
577bbe01	442
1f7371b2 AD	443	static void
	444	pp_debugfs_print_current_performance_level(void *handle,
	445	struct seq_file *m)
	446	{
577bbe01 RZ	447	struct pp_hwmgr *hwmgr;
	448
	449	if (handle == NULL)
	450	return;
	451
	452	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	453
	454	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	455	hwmgr->hwmgr_func->print_current_perforce_level == NULL)
	456	return;
	457
	458	hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
1f7371b2	459	}
3bace359	460
cac9a199 RZ	461	static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
	462	{
	463	struct pp_hwmgr *hwmgr;
	464
	465	if (handle == NULL)
	466	return -EINVAL;
	467
	468	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	469
	470	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	471	hwmgr->hwmgr_func->set_fan_control_mode == NULL)
	472	return -EINVAL;
	473
	474	return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
	475	}
	476
	477	static int pp_dpm_get_fan_control_mode(void *handle)
	478	{
	479	struct pp_hwmgr *hwmgr;
	480
	481	if (handle == NULL)
	482	return -EINVAL;
	483
	484	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	485
	486	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	487	hwmgr->hwmgr_func->get_fan_control_mode == NULL)
	488	return -EINVAL;
	489
	490	return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
	491	}
	492
	493	static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
	494	{
	495	struct pp_hwmgr *hwmgr;
	496
	497	if (handle == NULL)
	498	return -EINVAL;
	499
	500	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	501
	502	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	503	hwmgr->hwmgr_func->set_fan_speed_percent == NULL)
	504	return -EINVAL;
	505
	506	return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
	507	}
	508
	509	static int pp_dpm_get_fan_speed_percent(void handle, uint32_t speed)
	510	{
	511	struct pp_hwmgr *hwmgr;
	512
	513	if (handle == NULL)
	514	return -EINVAL;
	515
	516	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	517
	518	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
	519	hwmgr->hwmgr_func->get_fan_speed_percent == NULL)
	520	return -EINVAL;
	521
	522	return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
	523	}
	524
525	static int pp_dpm_get_temperature(void *handle)
526	{
527	struct pp_hwmgr *hwmgr;
528
529	if (handle == NULL)
530	return -EINVAL;
531
532	hwmgr = ((struct pp_instance *)handle)->hwmgr;
533
534	if (hwmgr == NULL \|\| hwmgr->hwmgr_func == NULL \|\|
535	hwmgr->hwmgr_func->get_temperature == NULL)
536	return -EINVAL;
537
538	return hwmgr->hwmgr_func->get_temperature(hwmgr);
539	}
577bbe01	540
1f7371b2	541	const struct amd_powerplay_funcs pp_dpm_funcs = {
cac9a199	542	.get_temperature = pp_dpm_get_temperature,
1f7371b2 AD	543	.load_firmware = pp_dpm_load_fw,
	544	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
	545	.force_performance_level = pp_dpm_force_performance_level,
	546	.get_performance_level = pp_dpm_get_performance_level,
	547	.get_current_power_state = pp_dpm_get_current_power_state,
	548	.get_sclk = pp_dpm_get_sclk,
	549	.get_mclk = pp_dpm_get_mclk,
	550	.powergate_vce = pp_dpm_powergate_vce,
	551	.powergate_uvd = pp_dpm_powergate_uvd,
	552	.dispatch_tasks = pp_dpm_dispatch_tasks,
	553	.print_current_performance_level = pp_debugfs_print_current_performance_level,
cac9a199 RZ	554	.set_fan_control_mode = pp_dpm_set_fan_control_mode,
	555	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
	556	.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
	557	.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
1f7371b2 AD	558	};
1f7371b2 AD	559
ac885b3a JZ	560	static int amd_pp_instance_init(struct amd_pp_init *pp_init,
	561	struct amd_powerplay *amd_pp)
	562	{
	563	int ret;
	564	struct pp_instance *handle;
	565
	566	handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
	567	if (handle == NULL)
	568	return -ENOMEM;
	569
a969e163 RZ	570	handle->pp_valid = PP_VALID;
a969e163 RZ	571
ac885b3a JZ	572	ret = smum_init(pp_init, handle);
ac885b3a JZ	573	if (ret)
3bace359 JZ	574	goto fail_smum;
	575
	576	ret = hwmgr_init(pp_init, handle);
	577	if (ret)
	578	goto fail_hwmgr;
ac885b3a	579
e92a0370 RZ	580	ret = eventmgr_init(handle);
	581	if (ret)
	582	goto fail_eventmgr;
	583
ac885b3a JZ	584	amd_pp->pp_handle = handle;
ac885b3a JZ	585	return 0;
3bace359	586
e92a0370 RZ	587	fail_eventmgr:
e92a0370 RZ	588	hwmgr_fini(handle->hwmgr);
3bace359 JZ	589	fail_hwmgr:
	590	smum_fini(handle->smu_mgr);
	591	fail_smum:
	592	kfree(handle);
	593	return ret;
ac885b3a JZ	594	}
	595
	596	static int amd_pp_instance_fini(void *handle)
	597	{
	598	struct pp_instance instance = (struct pp_instance )handle;
e92a0370	599
ac885b3a JZ	600	if (instance == NULL)
	601	return -EINVAL;
	602
e92a0370 RZ	603	eventmgr_fini(instance->eventmgr);
e92a0370 RZ	604
3bace359 JZ	605	hwmgr_fini(instance->hwmgr);
3bace359 JZ	606
ac885b3a JZ	607	smum_fini(instance->smu_mgr);
	608
	609	kfree(handle);
	610	return 0;
	611	}
	612
1f7371b2 AD	613	int amd_powerplay_init(struct amd_pp_init *pp_init,
	614	struct amd_powerplay *amd_pp)
	615	{
ac885b3a JZ	616	int ret;
ac885b3a JZ	617
1f7371b2 AD	618	if (pp_init == NULL \|\| amd_pp == NULL)
	619	return -EINVAL;
	620
ac885b3a JZ	621	ret = amd_pp_instance_init(pp_init, amd_pp);
	622
	623	if (ret)
	624	return ret;
	625
1f7371b2 AD	626	amd_pp->ip_funcs = &pp_ip_funcs;
	627	amd_pp->pp_funcs = &pp_dpm_funcs;
	628
	629	return 0;
	630	}
	631
	632	int amd_powerplay_fini(void *handle)
	633	{
ac885b3a JZ	634	amd_pp_instance_fini(handle);
ac885b3a JZ	635
1f7371b2 AD	636	return 0;
1f7371b2 AD	637	}
7fb72a1f RZ	638
	639	/* export this function to DAL */
	640
	641	int amd_powerplay_display_configuration_change(void handle, const void input)
	642	{
	643	struct pp_hwmgr *hwmgr;
	644	const struct amd_pp_display_configuration *display_config = input;
	645
a969e163	646	PP_CHECK((struct pp_instance *)handle);
7fb72a1f RZ	647
	648	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	649
	650	phm_store_dal_configuration_data(hwmgr, display_config);
e0b71a7e	651
7fb72a1f RZ	652	return 0;
7fb72a1f RZ	653	}
c4dd206b	654
1c9a9082 VP	655	int amd_powerplay_get_display_power_level(void *handle,
1c9a9082 VP	656	struct amd_pp_dal_clock_info *output)
c4dd206b VP	657	{
	658	struct pp_hwmgr *hwmgr;
	659
a969e163 RZ	660	PP_CHECK((struct pp_instance *)handle);
	661
	662	if (output == NULL)
c4dd206b VP	663	return -EINVAL;
	664
	665	hwmgr = ((struct pp_instance *)handle)->hwmgr;
	666
1c9a9082	667	return phm_get_dal_power_level(hwmgr, output);
c4dd206b	668	}