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1f7371b2 AD |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/types.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/gfp.h> | |
ac885b3a | 26 | #include <linux/slab.h> |
1f7371b2 AD |
27 | #include "amd_shared.h" |
28 | #include "amd_powerplay.h" | |
ac885b3a | 29 | #include "pp_instance.h" |
577bbe01 RZ |
30 | #include "power_state.h" |
31 | #include "eventmanager.h" | |
e273b041 | 32 | #include "pp_debug.h" |
1f7371b2 | 33 | |
a969e163 RZ |
34 | #define PP_CHECK(handle) \ |
35 | do { \ | |
36 | if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \ | |
37 | return -EINVAL; \ | |
38 | } while (0) | |
39 | ||
7383bcb9 RZ |
40 | #define PP_CHECK_HW(hwmgr) \ |
41 | do { \ | |
42 | if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \ | |
43 | return -EINVAL; \ | |
44 | } while (0) | |
45 | ||
1f7371b2 AD |
46 | static int pp_early_init(void *handle) |
47 | { | |
48 | return 0; | |
49 | } | |
50 | ||
51 | static int pp_sw_init(void *handle) | |
52 | { | |
3bace359 JZ |
53 | struct pp_instance *pp_handle; |
54 | struct pp_hwmgr *hwmgr; | |
55 | int ret = 0; | |
56 | ||
57 | if (handle == NULL) | |
58 | return -EINVAL; | |
59 | ||
60 | pp_handle = (struct pp_instance *)handle; | |
61 | hwmgr = pp_handle->hwmgr; | |
62 | ||
7383bcb9 RZ |
63 | PP_CHECK_HW(hwmgr); |
64 | ||
65 | if (hwmgr->pptable_func == NULL || | |
3bace359 JZ |
66 | hwmgr->pptable_func->pptable_init == NULL || |
67 | hwmgr->hwmgr_func->backend_init == NULL) | |
68 | return -EINVAL; | |
69 | ||
70 | ret = hwmgr->pptable_func->pptable_init(hwmgr); | |
e92a0370 | 71 | |
3bace359 JZ |
72 | if (ret == 0) |
73 | ret = hwmgr->hwmgr_func->backend_init(hwmgr); | |
74 | ||
9441f964 | 75 | if (ret) |
7383bcb9 | 76 | printk(KERN_ERR "amdgpu: powerplay initialization failed\n"); |
9441f964 | 77 | else |
7383bcb9 | 78 | printk(KERN_INFO "amdgpu: powerplay initialized\n"); |
9441f964 | 79 | |
3bace359 | 80 | return ret; |
1f7371b2 AD |
81 | } |
82 | ||
83 | static int pp_sw_fini(void *handle) | |
84 | { | |
3bace359 JZ |
85 | struct pp_instance *pp_handle; |
86 | struct pp_hwmgr *hwmgr; | |
87 | int ret = 0; | |
88 | ||
89 | if (handle == NULL) | |
90 | return -EINVAL; | |
91 | ||
92 | pp_handle = (struct pp_instance *)handle; | |
93 | hwmgr = pp_handle->hwmgr; | |
94 | ||
7383bcb9 RZ |
95 | PP_CHECK_HW(hwmgr); |
96 | ||
97 | if (hwmgr->hwmgr_func->backend_fini != NULL) | |
3bace359 JZ |
98 | ret = hwmgr->hwmgr_func->backend_fini(hwmgr); |
99 | ||
100 | return ret; | |
1f7371b2 AD |
101 | } |
102 | ||
103 | static int pp_hw_init(void *handle) | |
104 | { | |
ac885b3a JZ |
105 | struct pp_instance *pp_handle; |
106 | struct pp_smumgr *smumgr; | |
e92a0370 | 107 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
108 | int ret = 0; |
109 | ||
110 | if (handle == NULL) | |
111 | return -EINVAL; | |
112 | ||
113 | pp_handle = (struct pp_instance *)handle; | |
114 | smumgr = pp_handle->smu_mgr; | |
115 | ||
116 | if (smumgr == NULL || smumgr->smumgr_funcs == NULL || | |
117 | smumgr->smumgr_funcs->smu_init == NULL || | |
118 | smumgr->smumgr_funcs->start_smu == NULL) | |
119 | return -EINVAL; | |
120 | ||
121 | ret = smumgr->smumgr_funcs->smu_init(smumgr); | |
122 | if (ret) { | |
123 | printk(KERN_ERR "[ powerplay ] smc initialization failed\n"); | |
124 | return ret; | |
125 | } | |
126 | ||
127 | ret = smumgr->smumgr_funcs->start_smu(smumgr); | |
128 | if (ret) { | |
129 | printk(KERN_ERR "[ powerplay ] smc start failed\n"); | |
130 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
131 | return ret; | |
132 | } | |
e92a0370 | 133 | |
3bace359 | 134 | hw_init_power_state_table(pp_handle->hwmgr); |
e92a0370 | 135 | eventmgr = pp_handle->eventmgr; |
3bace359 | 136 | |
e92a0370 RZ |
137 | if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) |
138 | return -EINVAL; | |
139 | ||
140 | ret = eventmgr->pp_eventmgr_init(eventmgr); | |
1f7371b2 AD |
141 | return 0; |
142 | } | |
143 | ||
144 | static int pp_hw_fini(void *handle) | |
145 | { | |
ac885b3a JZ |
146 | struct pp_instance *pp_handle; |
147 | struct pp_smumgr *smumgr; | |
e92a0370 | 148 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
149 | |
150 | if (handle == NULL) | |
151 | return -EINVAL; | |
152 | ||
153 | pp_handle = (struct pp_instance *)handle; | |
e92a0370 RZ |
154 | eventmgr = pp_handle->eventmgr; |
155 | ||
156 | if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL) | |
157 | eventmgr->pp_eventmgr_fini(eventmgr); | |
158 | ||
ac885b3a JZ |
159 | smumgr = pp_handle->smu_mgr; |
160 | ||
161 | if (smumgr != NULL || smumgr->smumgr_funcs != NULL || | |
162 | smumgr->smumgr_funcs->smu_fini != NULL) | |
163 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
164 | ||
1f7371b2 AD |
165 | return 0; |
166 | } | |
167 | ||
168 | static bool pp_is_idle(void *handle) | |
169 | { | |
170 | return 0; | |
171 | } | |
172 | ||
173 | static int pp_wait_for_idle(void *handle) | |
174 | { | |
175 | return 0; | |
176 | } | |
177 | ||
178 | static int pp_sw_reset(void *handle) | |
179 | { | |
180 | return 0; | |
181 | } | |
182 | ||
183 | static void pp_print_status(void *handle) | |
184 | { | |
185 | ||
186 | } | |
187 | ||
188 | static int pp_set_clockgating_state(void *handle, | |
189 | enum amd_clockgating_state state) | |
190 | { | |
03e3905f EH |
191 | struct pp_hwmgr *hwmgr; |
192 | uint32_t msg_id, pp_state; | |
193 | ||
194 | if (handle == NULL) | |
195 | return -EINVAL; | |
196 | ||
197 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
198 | ||
7383bcb9 | 199 | PP_CHECK_HW(hwmgr); |
03e3905f | 200 | |
7383bcb9 RZ |
201 | if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { |
202 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
538333f0 | 203 | return 0; |
7383bcb9 | 204 | } |
538333f0 | 205 | |
03e3905f EH |
206 | if (state == AMD_CG_STATE_UNGATE) |
207 | pp_state = 0; | |
208 | else | |
209 | pp_state = PP_STATE_CG | PP_STATE_LS; | |
210 | ||
211 | /* Enable/disable GFX blocks clock gating through SMU */ | |
212 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
213 | PP_BLOCK_GFX_CG, | |
214 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
215 | pp_state); | |
216 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
217 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
218 | PP_BLOCK_GFX_3D, | |
219 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
220 | pp_state); | |
221 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
222 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
223 | PP_BLOCK_GFX_RLC, | |
224 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
225 | pp_state); | |
226 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
227 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
228 | PP_BLOCK_GFX_CP, | |
229 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
230 | pp_state); | |
231 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
232 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
233 | PP_BLOCK_GFX_MG, | |
234 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
235 | pp_state); | |
236 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
237 | ||
238 | /* Enable/disable System blocks clock gating through SMU */ | |
239 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
240 | PP_BLOCK_SYS_BIF, | |
241 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
242 | pp_state); | |
243 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
244 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
245 | PP_BLOCK_SYS_BIF, | |
246 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
247 | pp_state); | |
248 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
249 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
250 | PP_BLOCK_SYS_MC, | |
251 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
252 | pp_state); | |
253 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
254 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
255 | PP_BLOCK_SYS_ROM, | |
256 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
257 | pp_state); | |
258 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
259 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
260 | PP_BLOCK_SYS_DRM, | |
261 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
262 | pp_state); | |
263 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
264 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
265 | PP_BLOCK_SYS_HDP, | |
266 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
267 | pp_state); | |
268 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
269 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
270 | PP_BLOCK_SYS_SDMA, | |
271 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
272 | pp_state); | |
273 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
274 | ||
1f7371b2 AD |
275 | return 0; |
276 | } | |
277 | ||
278 | static int pp_set_powergating_state(void *handle, | |
279 | enum amd_powergating_state state) | |
280 | { | |
65f85e7d EH |
281 | struct pp_hwmgr *hwmgr; |
282 | ||
283 | if (handle == NULL) | |
284 | return -EINVAL; | |
285 | ||
286 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
287 | ||
7383bcb9 RZ |
288 | PP_CHECK_HW(hwmgr); |
289 | ||
290 | if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) { | |
291 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
292 | return 0; | |
293 | } | |
65f85e7d EH |
294 | |
295 | /* Enable/disable GFX per cu powergating through SMU */ | |
296 | return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr, | |
297 | state == AMD_PG_STATE_GATE ? true : false); | |
1f7371b2 AD |
298 | } |
299 | ||
300 | static int pp_suspend(void *handle) | |
301 | { | |
577bbe01 RZ |
302 | struct pp_instance *pp_handle; |
303 | struct pp_eventmgr *eventmgr; | |
304 | struct pem_event_data event_data = { {0} }; | |
305 | ||
306 | if (handle == NULL) | |
307 | return -EINVAL; | |
308 | ||
309 | pp_handle = (struct pp_instance *)handle; | |
310 | eventmgr = pp_handle->eventmgr; | |
311 | pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); | |
1f7371b2 AD |
312 | return 0; |
313 | } | |
314 | ||
315 | static int pp_resume(void *handle) | |
316 | { | |
577bbe01 RZ |
317 | struct pp_instance *pp_handle; |
318 | struct pp_eventmgr *eventmgr; | |
319 | struct pem_event_data event_data = { {0} }; | |
e0b71a7e RZ |
320 | struct pp_smumgr *smumgr; |
321 | int ret; | |
577bbe01 RZ |
322 | |
323 | if (handle == NULL) | |
324 | return -EINVAL; | |
325 | ||
326 | pp_handle = (struct pp_instance *)handle; | |
e0b71a7e RZ |
327 | smumgr = pp_handle->smu_mgr; |
328 | ||
329 | if (smumgr == NULL || smumgr->smumgr_funcs == NULL || | |
330 | smumgr->smumgr_funcs->start_smu == NULL) | |
331 | return -EINVAL; | |
332 | ||
333 | ret = smumgr->smumgr_funcs->start_smu(smumgr); | |
334 | if (ret) { | |
335 | printk(KERN_ERR "[ powerplay ] smc start failed\n"); | |
336 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
337 | return ret; | |
338 | } | |
339 | ||
577bbe01 RZ |
340 | eventmgr = pp_handle->eventmgr; |
341 | pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); | |
e0b71a7e | 342 | |
1f7371b2 AD |
343 | return 0; |
344 | } | |
345 | ||
346 | const struct amd_ip_funcs pp_ip_funcs = { | |
347 | .early_init = pp_early_init, | |
348 | .late_init = NULL, | |
349 | .sw_init = pp_sw_init, | |
350 | .sw_fini = pp_sw_fini, | |
351 | .hw_init = pp_hw_init, | |
352 | .hw_fini = pp_hw_fini, | |
353 | .suspend = pp_suspend, | |
354 | .resume = pp_resume, | |
355 | .is_idle = pp_is_idle, | |
356 | .wait_for_idle = pp_wait_for_idle, | |
357 | .soft_reset = pp_sw_reset, | |
358 | .print_status = pp_print_status, | |
359 | .set_clockgating_state = pp_set_clockgating_state, | |
360 | .set_powergating_state = pp_set_powergating_state, | |
361 | }; | |
362 | ||
363 | static int pp_dpm_load_fw(void *handle) | |
364 | { | |
365 | return 0; | |
366 | } | |
367 | ||
368 | static int pp_dpm_fw_loading_complete(void *handle) | |
369 | { | |
370 | return 0; | |
371 | } | |
372 | ||
373 | static int pp_dpm_force_performance_level(void *handle, | |
374 | enum amd_dpm_forced_level level) | |
375 | { | |
577bbe01 RZ |
376 | struct pp_instance *pp_handle; |
377 | struct pp_hwmgr *hwmgr; | |
378 | ||
379 | if (handle == NULL) | |
380 | return -EINVAL; | |
381 | ||
382 | pp_handle = (struct pp_instance *)handle; | |
383 | ||
384 | hwmgr = pp_handle->hwmgr; | |
385 | ||
7383bcb9 RZ |
386 | PP_CHECK_HW(hwmgr); |
387 | ||
388 | if (hwmgr->hwmgr_func->force_dpm_level == NULL) { | |
389 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
390 | return 0; | |
391 | } | |
577bbe01 RZ |
392 | |
393 | hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); | |
394 | ||
1f7371b2 AD |
395 | return 0; |
396 | } | |
577bbe01 | 397 | |
1f7371b2 AD |
398 | static enum amd_dpm_forced_level pp_dpm_get_performance_level( |
399 | void *handle) | |
400 | { | |
577bbe01 RZ |
401 | struct pp_hwmgr *hwmgr; |
402 | ||
403 | if (handle == NULL) | |
404 | return -EINVAL; | |
405 | ||
406 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
407 | ||
408 | if (hwmgr == NULL) | |
409 | return -EINVAL; | |
410 | ||
411 | return (((struct pp_instance *)handle)->hwmgr->dpm_level); | |
1f7371b2 | 412 | } |
577bbe01 | 413 | |
1f7371b2 AD |
414 | static int pp_dpm_get_sclk(void *handle, bool low) |
415 | { | |
577bbe01 RZ |
416 | struct pp_hwmgr *hwmgr; |
417 | ||
418 | if (handle == NULL) | |
419 | return -EINVAL; | |
420 | ||
421 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
422 | ||
7383bcb9 RZ |
423 | PP_CHECK_HW(hwmgr); |
424 | ||
425 | if (hwmgr->hwmgr_func->get_sclk == NULL) { | |
426 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
427 | return 0; | |
428 | } | |
577bbe01 RZ |
429 | |
430 | return hwmgr->hwmgr_func->get_sclk(hwmgr, low); | |
1f7371b2 | 431 | } |
577bbe01 | 432 | |
1f7371b2 AD |
433 | static int pp_dpm_get_mclk(void *handle, bool low) |
434 | { | |
577bbe01 RZ |
435 | struct pp_hwmgr *hwmgr; |
436 | ||
437 | if (handle == NULL) | |
438 | return -EINVAL; | |
439 | ||
440 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
441 | ||
7383bcb9 RZ |
442 | PP_CHECK_HW(hwmgr); |
443 | ||
444 | if (hwmgr->hwmgr_func->get_mclk == NULL) { | |
445 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
446 | return 0; | |
447 | } | |
577bbe01 RZ |
448 | |
449 | return hwmgr->hwmgr_func->get_mclk(hwmgr, low); | |
1f7371b2 | 450 | } |
577bbe01 | 451 | |
1f7371b2 AD |
452 | static int pp_dpm_powergate_vce(void *handle, bool gate) |
453 | { | |
577bbe01 RZ |
454 | struct pp_hwmgr *hwmgr; |
455 | ||
456 | if (handle == NULL) | |
457 | return -EINVAL; | |
458 | ||
459 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
460 | ||
7383bcb9 RZ |
461 | PP_CHECK_HW(hwmgr); |
462 | ||
463 | if (hwmgr->hwmgr_func->powergate_vce == NULL) { | |
464 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
465 | return 0; | |
466 | } | |
577bbe01 RZ |
467 | |
468 | return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); | |
1f7371b2 | 469 | } |
577bbe01 | 470 | |
1f7371b2 AD |
471 | static int pp_dpm_powergate_uvd(void *handle, bool gate) |
472 | { | |
577bbe01 RZ |
473 | struct pp_hwmgr *hwmgr; |
474 | ||
475 | if (handle == NULL) | |
476 | return -EINVAL; | |
477 | ||
478 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
479 | ||
7383bcb9 RZ |
480 | PP_CHECK_HW(hwmgr); |
481 | ||
482 | if (hwmgr->hwmgr_func->powergate_uvd == NULL) { | |
483 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
484 | return 0; | |
485 | } | |
577bbe01 RZ |
486 | |
487 | return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); | |
488 | } | |
489 | ||
490 | static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) | |
491 | { | |
492 | switch (state) { | |
493 | case POWER_STATE_TYPE_BATTERY: | |
494 | return PP_StateUILabel_Battery; | |
495 | case POWER_STATE_TYPE_BALANCED: | |
496 | return PP_StateUILabel_Balanced; | |
497 | case POWER_STATE_TYPE_PERFORMANCE: | |
498 | return PP_StateUILabel_Performance; | |
499 | default: | |
500 | return PP_StateUILabel_None; | |
501 | } | |
1f7371b2 AD |
502 | } |
503 | ||
504 | int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output) | |
505 | { | |
577bbe01 RZ |
506 | int ret = 0; |
507 | struct pp_instance *pp_handle; | |
508 | struct pem_event_data data = { {0} }; | |
509 | ||
510 | pp_handle = (struct pp_instance *)handle; | |
511 | ||
512 | if (pp_handle == NULL) | |
513 | return -EINVAL; | |
514 | ||
515 | switch (event_id) { | |
516 | case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: | |
517 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
518 | break; | |
519 | case AMD_PP_EVENT_ENABLE_USER_STATE: | |
520 | { | |
521 | enum amd_pm_state_type ps; | |
522 | ||
523 | if (input == NULL) | |
524 | return -EINVAL; | |
525 | ps = *(unsigned long *)input; | |
526 | ||
527 | data.requested_ui_label = power_state_convert(ps); | |
528 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
dc26a2a2 | 529 | break; |
577bbe01 | 530 | } |
dc26a2a2 RZ |
531 | case AMD_PP_EVENT_COMPLETE_INIT: |
532 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
533 | break; | |
577bbe01 RZ |
534 | default: |
535 | break; | |
536 | } | |
537 | return ret; | |
1f7371b2 | 538 | } |
577bbe01 | 539 | |
1f7371b2 AD |
540 | enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) |
541 | { | |
577bbe01 RZ |
542 | struct pp_hwmgr *hwmgr; |
543 | struct pp_power_state *state; | |
544 | ||
545 | if (handle == NULL) | |
546 | return -EINVAL; | |
547 | ||
548 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
549 | ||
550 | if (hwmgr == NULL || hwmgr->current_ps == NULL) | |
551 | return -EINVAL; | |
552 | ||
553 | state = hwmgr->current_ps; | |
554 | ||
555 | switch (state->classification.ui_label) { | |
556 | case PP_StateUILabel_Battery: | |
557 | return POWER_STATE_TYPE_BATTERY; | |
558 | case PP_StateUILabel_Balanced: | |
559 | return POWER_STATE_TYPE_BALANCED; | |
560 | case PP_StateUILabel_Performance: | |
561 | return POWER_STATE_TYPE_PERFORMANCE; | |
562 | default: | |
f3898ea1 EH |
563 | if (state->classification.flags & PP_StateClassificationFlag_Boot) |
564 | return POWER_STATE_TYPE_INTERNAL_BOOT; | |
565 | else | |
566 | return POWER_STATE_TYPE_DEFAULT; | |
577bbe01 | 567 | } |
1f7371b2 | 568 | } |
577bbe01 | 569 | |
1f7371b2 AD |
570 | static void |
571 | pp_debugfs_print_current_performance_level(void *handle, | |
572 | struct seq_file *m) | |
573 | { | |
577bbe01 RZ |
574 | struct pp_hwmgr *hwmgr; |
575 | ||
576 | if (handle == NULL) | |
577 | return; | |
578 | ||
579 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
580 | ||
7383bcb9 RZ |
581 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL) |
582 | return; | |
583 | ||
584 | if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) { | |
585 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
577bbe01 | 586 | return; |
7383bcb9 | 587 | } |
577bbe01 RZ |
588 | |
589 | hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m); | |
1f7371b2 | 590 | } |
3bace359 | 591 | |
cac9a199 RZ |
592 | static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) |
593 | { | |
594 | struct pp_hwmgr *hwmgr; | |
595 | ||
596 | if (handle == NULL) | |
597 | return -EINVAL; | |
598 | ||
599 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
600 | ||
7383bcb9 RZ |
601 | PP_CHECK_HW(hwmgr); |
602 | ||
603 | if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) { | |
604 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
605 | return 0; | |
606 | } | |
cac9a199 RZ |
607 | |
608 | return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); | |
609 | } | |
610 | ||
611 | static int pp_dpm_get_fan_control_mode(void *handle) | |
612 | { | |
613 | struct pp_hwmgr *hwmgr; | |
614 | ||
615 | if (handle == NULL) | |
616 | return -EINVAL; | |
617 | ||
618 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
619 | ||
7383bcb9 RZ |
620 | PP_CHECK_HW(hwmgr); |
621 | ||
622 | if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) { | |
623 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
624 | return 0; | |
625 | } | |
cac9a199 RZ |
626 | |
627 | return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); | |
628 | } | |
629 | ||
630 | static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) | |
631 | { | |
632 | struct pp_hwmgr *hwmgr; | |
633 | ||
634 | if (handle == NULL) | |
635 | return -EINVAL; | |
636 | ||
637 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
638 | ||
7383bcb9 RZ |
639 | PP_CHECK_HW(hwmgr); |
640 | ||
641 | if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) { | |
642 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
643 | return 0; | |
644 | } | |
cac9a199 RZ |
645 | |
646 | return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent); | |
647 | } | |
648 | ||
649 | static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) | |
650 | { | |
651 | struct pp_hwmgr *hwmgr; | |
652 | ||
653 | if (handle == NULL) | |
654 | return -EINVAL; | |
655 | ||
656 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
657 | ||
7383bcb9 RZ |
658 | PP_CHECK_HW(hwmgr); |
659 | ||
660 | if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) { | |
661 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
662 | return 0; | |
663 | } | |
cac9a199 RZ |
664 | |
665 | return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); | |
666 | } | |
667 | ||
668 | static int pp_dpm_get_temperature(void *handle) | |
669 | { | |
670 | struct pp_hwmgr *hwmgr; | |
671 | ||
672 | if (handle == NULL) | |
673 | return -EINVAL; | |
674 | ||
675 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
676 | ||
7383bcb9 RZ |
677 | PP_CHECK_HW(hwmgr); |
678 | ||
679 | if (hwmgr->hwmgr_func->get_temperature == NULL) { | |
680 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
681 | return 0; | |
682 | } | |
cac9a199 RZ |
683 | |
684 | return hwmgr->hwmgr_func->get_temperature(hwmgr); | |
685 | } | |
577bbe01 | 686 | |
f3898ea1 EH |
687 | static int pp_dpm_get_pp_num_states(void *handle, |
688 | struct pp_states_info *data) | |
689 | { | |
690 | struct pp_hwmgr *hwmgr; | |
691 | int i; | |
692 | ||
693 | if (!handle) | |
694 | return -EINVAL; | |
695 | ||
696 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
697 | ||
698 | if (hwmgr == NULL || hwmgr->ps == NULL) | |
699 | return -EINVAL; | |
700 | ||
701 | data->nums = hwmgr->num_ps; | |
702 | ||
703 | for (i = 0; i < hwmgr->num_ps; i++) { | |
704 | struct pp_power_state *state = (struct pp_power_state *) | |
705 | ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); | |
706 | switch (state->classification.ui_label) { | |
707 | case PP_StateUILabel_Battery: | |
708 | data->states[i] = POWER_STATE_TYPE_BATTERY; | |
709 | break; | |
710 | case PP_StateUILabel_Balanced: | |
711 | data->states[i] = POWER_STATE_TYPE_BALANCED; | |
712 | break; | |
713 | case PP_StateUILabel_Performance: | |
714 | data->states[i] = POWER_STATE_TYPE_PERFORMANCE; | |
715 | break; | |
716 | default: | |
717 | if (state->classification.flags & PP_StateClassificationFlag_Boot) | |
718 | data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT; | |
719 | else | |
720 | data->states[i] = POWER_STATE_TYPE_DEFAULT; | |
721 | } | |
722 | } | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
727 | static int pp_dpm_get_pp_table(void *handle, char **table) | |
728 | { | |
729 | struct pp_hwmgr *hwmgr; | |
730 | ||
731 | if (!handle) | |
732 | return -EINVAL; | |
733 | ||
734 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
735 | ||
7383bcb9 RZ |
736 | PP_CHECK_HW(hwmgr); |
737 | ||
738 | if (hwmgr->hwmgr_func->get_pp_table == NULL) { | |
739 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
740 | return 0; | |
741 | } | |
f3898ea1 EH |
742 | |
743 | return hwmgr->hwmgr_func->get_pp_table(hwmgr, table); | |
744 | } | |
745 | ||
746 | static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) | |
747 | { | |
748 | struct pp_hwmgr *hwmgr; | |
749 | ||
750 | if (!handle) | |
751 | return -EINVAL; | |
752 | ||
753 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
754 | ||
7383bcb9 RZ |
755 | PP_CHECK_HW(hwmgr); |
756 | ||
757 | if (hwmgr->hwmgr_func->set_pp_table == NULL) { | |
758 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
759 | return 0; | |
760 | } | |
f3898ea1 EH |
761 | |
762 | return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size); | |
763 | } | |
764 | ||
765 | static int pp_dpm_force_clock_level(void *handle, | |
766 | enum pp_clock_type type, int level) | |
767 | { | |
768 | struct pp_hwmgr *hwmgr; | |
769 | ||
770 | if (!handle) | |
771 | return -EINVAL; | |
772 | ||
773 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
774 | ||
7383bcb9 RZ |
775 | PP_CHECK_HW(hwmgr); |
776 | ||
777 | if (hwmgr->hwmgr_func->force_clock_level == NULL) { | |
778 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
779 | return 0; | |
780 | } | |
f3898ea1 EH |
781 | |
782 | return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level); | |
783 | } | |
784 | ||
785 | static int pp_dpm_print_clock_levels(void *handle, | |
786 | enum pp_clock_type type, char *buf) | |
787 | { | |
788 | struct pp_hwmgr *hwmgr; | |
789 | ||
790 | if (!handle) | |
791 | return -EINVAL; | |
792 | ||
793 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
794 | ||
7383bcb9 | 795 | PP_CHECK_HW(hwmgr); |
f3898ea1 | 796 | |
7383bcb9 RZ |
797 | if (hwmgr->hwmgr_func->print_clock_levels == NULL) { |
798 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
799 | return 0; | |
800 | } | |
f3898ea1 EH |
801 | return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf); |
802 | } | |
803 | ||
1f7371b2 | 804 | const struct amd_powerplay_funcs pp_dpm_funcs = { |
cac9a199 | 805 | .get_temperature = pp_dpm_get_temperature, |
1f7371b2 AD |
806 | .load_firmware = pp_dpm_load_fw, |
807 | .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, | |
808 | .force_performance_level = pp_dpm_force_performance_level, | |
809 | .get_performance_level = pp_dpm_get_performance_level, | |
810 | .get_current_power_state = pp_dpm_get_current_power_state, | |
811 | .get_sclk = pp_dpm_get_sclk, | |
812 | .get_mclk = pp_dpm_get_mclk, | |
813 | .powergate_vce = pp_dpm_powergate_vce, | |
814 | .powergate_uvd = pp_dpm_powergate_uvd, | |
815 | .dispatch_tasks = pp_dpm_dispatch_tasks, | |
816 | .print_current_performance_level = pp_debugfs_print_current_performance_level, | |
cac9a199 RZ |
817 | .set_fan_control_mode = pp_dpm_set_fan_control_mode, |
818 | .get_fan_control_mode = pp_dpm_get_fan_control_mode, | |
819 | .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, | |
820 | .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, | |
f3898ea1 EH |
821 | .get_pp_num_states = pp_dpm_get_pp_num_states, |
822 | .get_pp_table = pp_dpm_get_pp_table, | |
823 | .set_pp_table = pp_dpm_set_pp_table, | |
824 | .force_clock_level = pp_dpm_force_clock_level, | |
825 | .print_clock_levels = pp_dpm_print_clock_levels, | |
1f7371b2 AD |
826 | }; |
827 | ||
ac885b3a JZ |
828 | static int amd_pp_instance_init(struct amd_pp_init *pp_init, |
829 | struct amd_powerplay *amd_pp) | |
830 | { | |
831 | int ret; | |
832 | struct pp_instance *handle; | |
833 | ||
834 | handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL); | |
835 | if (handle == NULL) | |
836 | return -ENOMEM; | |
837 | ||
a969e163 RZ |
838 | handle->pp_valid = PP_VALID; |
839 | ||
ac885b3a JZ |
840 | ret = smum_init(pp_init, handle); |
841 | if (ret) | |
3bace359 JZ |
842 | goto fail_smum; |
843 | ||
844 | ret = hwmgr_init(pp_init, handle); | |
845 | if (ret) | |
846 | goto fail_hwmgr; | |
ac885b3a | 847 | |
e92a0370 RZ |
848 | ret = eventmgr_init(handle); |
849 | if (ret) | |
850 | goto fail_eventmgr; | |
851 | ||
ac885b3a JZ |
852 | amd_pp->pp_handle = handle; |
853 | return 0; | |
3bace359 | 854 | |
e92a0370 RZ |
855 | fail_eventmgr: |
856 | hwmgr_fini(handle->hwmgr); | |
3bace359 JZ |
857 | fail_hwmgr: |
858 | smum_fini(handle->smu_mgr); | |
859 | fail_smum: | |
860 | kfree(handle); | |
861 | return ret; | |
ac885b3a JZ |
862 | } |
863 | ||
864 | static int amd_pp_instance_fini(void *handle) | |
865 | { | |
866 | struct pp_instance *instance = (struct pp_instance *)handle; | |
e92a0370 | 867 | |
ac885b3a JZ |
868 | if (instance == NULL) |
869 | return -EINVAL; | |
870 | ||
e92a0370 RZ |
871 | eventmgr_fini(instance->eventmgr); |
872 | ||
3bace359 JZ |
873 | hwmgr_fini(instance->hwmgr); |
874 | ||
ac885b3a JZ |
875 | smum_fini(instance->smu_mgr); |
876 | ||
877 | kfree(handle); | |
878 | return 0; | |
879 | } | |
880 | ||
1f7371b2 AD |
881 | int amd_powerplay_init(struct amd_pp_init *pp_init, |
882 | struct amd_powerplay *amd_pp) | |
883 | { | |
ac885b3a JZ |
884 | int ret; |
885 | ||
1f7371b2 AD |
886 | if (pp_init == NULL || amd_pp == NULL) |
887 | return -EINVAL; | |
888 | ||
ac885b3a JZ |
889 | ret = amd_pp_instance_init(pp_init, amd_pp); |
890 | ||
891 | if (ret) | |
892 | return ret; | |
893 | ||
1f7371b2 AD |
894 | amd_pp->ip_funcs = &pp_ip_funcs; |
895 | amd_pp->pp_funcs = &pp_dpm_funcs; | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
900 | int amd_powerplay_fini(void *handle) | |
901 | { | |
ac885b3a JZ |
902 | amd_pp_instance_fini(handle); |
903 | ||
1f7371b2 AD |
904 | return 0; |
905 | } | |
7fb72a1f RZ |
906 | |
907 | /* export this function to DAL */ | |
908 | ||
155f1127 DR |
909 | int amd_powerplay_display_configuration_change(void *handle, |
910 | const struct amd_pp_display_configuration *display_config) | |
7fb72a1f RZ |
911 | { |
912 | struct pp_hwmgr *hwmgr; | |
7fb72a1f | 913 | |
a969e163 | 914 | PP_CHECK((struct pp_instance *)handle); |
7fb72a1f RZ |
915 | |
916 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
917 | ||
918 | phm_store_dal_configuration_data(hwmgr, display_config); | |
e0b71a7e | 919 | |
7fb72a1f RZ |
920 | return 0; |
921 | } | |
c4dd206b | 922 | |
1c9a9082 | 923 | int amd_powerplay_get_display_power_level(void *handle, |
47329134 | 924 | struct amd_pp_simple_clock_info *output) |
c4dd206b VP |
925 | { |
926 | struct pp_hwmgr *hwmgr; | |
927 | ||
a969e163 RZ |
928 | PP_CHECK((struct pp_instance *)handle); |
929 | ||
930 | if (output == NULL) | |
c4dd206b VP |
931 | return -EINVAL; |
932 | ||
933 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
934 | ||
1c9a9082 | 935 | return phm_get_dal_power_level(hwmgr, output); |
c4dd206b | 936 | } |
e273b041 RZ |
937 | |
938 | int amd_powerplay_get_current_clocks(void *handle, | |
155f1127 | 939 | struct amd_pp_clock_info *clocks) |
e273b041 RZ |
940 | { |
941 | struct pp_hwmgr *hwmgr; | |
942 | struct amd_pp_simple_clock_info simple_clocks; | |
943 | struct pp_clock_info hw_clocks; | |
e273b041 | 944 | |
fa9e6991 RZ |
945 | PP_CHECK((struct pp_instance *)handle); |
946 | ||
947 | if (clocks == NULL) | |
e273b041 RZ |
948 | return -EINVAL; |
949 | ||
950 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
951 | ||
952 | phm_get_dal_power_level(hwmgr, &simple_clocks); | |
953 | ||
954 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { | |
955 | if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment)) | |
956 | PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1); | |
957 | } else { | |
958 | if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity)) | |
959 | PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1); | |
960 | } | |
961 | ||
962 | clocks->min_engine_clock = hw_clocks.min_eng_clk; | |
963 | clocks->max_engine_clock = hw_clocks.max_eng_clk; | |
964 | clocks->min_memory_clock = hw_clocks.min_mem_clk; | |
965 | clocks->max_memory_clock = hw_clocks.max_mem_clk; | |
966 | clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; | |
967 | clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; | |
968 | ||
969 | clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; | |
970 | clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; | |
971 | ||
972 | clocks->max_clocks_state = simple_clocks.level; | |
973 | ||
974 | if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { | |
975 | clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; | |
976 | clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; | |
977 | } | |
978 | ||
979 | return 0; | |
980 | ||
981 | } | |
982 | ||
983 | int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) | |
984 | { | |
985 | int result = -1; | |
986 | ||
987 | struct pp_hwmgr *hwmgr; | |
988 | ||
fa9e6991 RZ |
989 | PP_CHECK((struct pp_instance *)handle); |
990 | ||
991 | if (clocks == NULL) | |
e273b041 RZ |
992 | return -EINVAL; |
993 | ||
994 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
995 | ||
996 | result = phm_get_clock_by_type(hwmgr, type, clocks); | |
997 | ||
998 | return result; | |
999 | } | |
1000 | ||
155f1127 DR |
1001 | int amd_powerplay_get_display_mode_validation_clocks(void *handle, |
1002 | struct amd_pp_simple_clock_info *clocks) | |
e273b041 RZ |
1003 | { |
1004 | int result = -1; | |
e273b041 RZ |
1005 | struct pp_hwmgr *hwmgr; |
1006 | ||
fa9e6991 RZ |
1007 | PP_CHECK((struct pp_instance *)handle); |
1008 | ||
1009 | if (clocks == NULL) | |
e273b041 RZ |
1010 | return -EINVAL; |
1011 | ||
1012 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
1013 | ||
1014 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) | |
1015 | result = phm_get_max_high_clocks(hwmgr, clocks); | |
1016 | ||
1017 | return result; | |
1018 | } | |
1019 |