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drm/amdgpu: drop allocation flag masks
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / uvd_v4_2.c
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a2e73f56
AD		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König <christian.koenig@amd.com>
23 */
24
25#include <linux/firmware.h>
26#include <drm/drmP.h>
27#include "amdgpu.h"
28#include "amdgpu_uvd.h"
29#include "cikd.h"
30
31#include "uvd/uvd_4_2_d.h"
32#include "uvd/uvd_4_2_sh_mask.h"
33
34#include "oss/oss_2_0_d.h"
35#include "oss/oss_2_0_sh_mask.h"
36
37static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
38static void uvd_v4_2_init_cg(struct amdgpu_device *adev);
39static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
40static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
41static int uvd_v4_2_start(struct amdgpu_device *adev);
42static void uvd_v4_2_stop(struct amdgpu_device *adev);
43
44/**
45 * uvd_v4_2_ring_get_rptr - get read pointer
46 *
47 * @ring: amdgpu_ring pointer
48 *
49 * Returns the current hardware read pointer
50 */
51static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
52{
53 struct amdgpu_device *adev = ring->adev;
54
55 return RREG32(mmUVD_RBC_RB_RPTR);
56}
57
58/**
59 * uvd_v4_2_ring_get_wptr - get write pointer
60 *
61 * @ring: amdgpu_ring pointer
62 *
63 * Returns the current hardware write pointer
64 */
65static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
66{
67 struct amdgpu_device *adev = ring->adev;
68
69 return RREG32(mmUVD_RBC_RB_WPTR);
70}
71
72/**
73 * uvd_v4_2_ring_set_wptr - set write pointer
74 *
75 * @ring: amdgpu_ring pointer
76 *
77 * Commits the write pointer to the hardware
78 */
79static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
80{
81 struct amdgpu_device *adev = ring->adev;
82
83 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
84}
85
86static int uvd_v4_2_early_init(struct amdgpu_device *adev)
87{
88 uvd_v4_2_set_ring_funcs(adev);
89 uvd_v4_2_set_irq_funcs(adev);
90
91 return 0;
92}
93
94static int uvd_v4_2_sw_init(struct amdgpu_device *adev)
95{
96 struct amdgpu_ring *ring;
97 int r;
98
99 /* UVD TRAP */
100 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
101 if (r)
102 return r;
103
104 r = amdgpu_uvd_sw_init(adev);
105 if (r)
106 return r;
107
108 r = amdgpu_uvd_resume(adev);
109 if (r)
110 return r;
111
112 ring = &adev->uvd.ring;
113 sprintf(ring->name, "uvd");
114 r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
115 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
116
117 return r;
118}
119
120static int uvd_v4_2_sw_fini(struct amdgpu_device *adev)
121{
122 int r;
123
124 r = amdgpu_uvd_suspend(adev);
125 if (r)
126 return r;
127
128 r = amdgpu_uvd_sw_fini(adev);
129 if (r)
130 return r;
131
132 return r;
133}
134
135/**
136 * uvd_v4_2_hw_init - start and test UVD block
137 *
138 * @adev: amdgpu_device pointer
139 *
140 * Initialize the hardware, boot up the VCPU and do some testing
141 */
142static int uvd_v4_2_hw_init(struct amdgpu_device *adev)
143{
144 struct amdgpu_ring *ring = &adev->uvd.ring;
145 uint32_t tmp;
146 int r;
147
148 /* raise clocks while booting up the VCPU */
149 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
150
151 r = uvd_v4_2_start(adev);
152 if (r)
153 goto done;
154
155 ring->ready = true;
156 r = amdgpu_ring_test_ring(ring);
157 if (r) {
158 ring->ready = false;
159 goto done;
160 }
161
162 r = amdgpu_ring_lock(ring, 10);
163 if (r) {
164 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
165 goto done;
166 }
167
168 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
169 amdgpu_ring_write(ring, tmp);
170 amdgpu_ring_write(ring, 0xFFFFF);
171
172 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
173 amdgpu_ring_write(ring, tmp);
174 amdgpu_ring_write(ring, 0xFFFFF);
175
176 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
177 amdgpu_ring_write(ring, tmp);
178 amdgpu_ring_write(ring, 0xFFFFF);
179
180 /* Clear timeout status bits */
181 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
182 amdgpu_ring_write(ring, 0x8);
183
184 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
185 amdgpu_ring_write(ring, 3);
186
187 amdgpu_ring_unlock_commit(ring);
188
189done:
190 /* lower clocks again */
191 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
192
193 if (!r)
194 DRM_INFO("UVD initialized successfully.\n");
195
196 return r;
197}
198
199/**
200 * uvd_v4_2_hw_fini - stop the hardware block
201 *
202 * @adev: amdgpu_device pointer
203 *
204 * Stop the UVD block, mark ring as not ready any more
205 */
206static int uvd_v4_2_hw_fini(struct amdgpu_device *adev)
207{
208 struct amdgpu_ring *ring = &adev->uvd.ring;
209
210 uvd_v4_2_stop(adev);
211 ring->ready = false;
212
213 return 0;
214}
215
216static int uvd_v4_2_suspend(struct amdgpu_device *adev)
217{
218 int r;
219
220 r = uvd_v4_2_hw_fini(adev);
221 if (r)
222 return r;
223
224 r = amdgpu_uvd_suspend(adev);
225 if (r)
226 return r;
227
228 return r;
229}
230
231static int uvd_v4_2_resume(struct amdgpu_device *adev)
232{
233 int r;
234
235 r = amdgpu_uvd_resume(adev);
236 if (r)
237 return r;
238
239 r = uvd_v4_2_hw_init(adev);
240 if (r)
241 return r;
242
243 return r;
244}
245
246/**
247 * uvd_v4_2_start - start UVD block
248 *
249 * @adev: amdgpu_device pointer
250 *
251 * Setup and start the UVD block
252 */
253static int uvd_v4_2_start(struct amdgpu_device *adev)
254{
255 struct amdgpu_ring *ring = &adev->uvd.ring;
256 uint32_t rb_bufsz;
257 int i, j, r;
258
259 /* disable byte swapping */
260 u32 lmi_swap_cntl = 0;
261 u32 mp_swap_cntl = 0;
262
263 uvd_v4_2_mc_resume(adev);
264
265 /* disable clock gating */
266 WREG32(mmUVD_CGC_GATE, 0);
267
268 /* disable interupt */
269 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
270
271 /* Stall UMC and register bus before resetting VCPU */
272 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
273 mdelay(1);
274
275 /* put LMI, VCPU, RBC etc... into reset */
276 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
277 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
278 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
279 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
280 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
281 mdelay(5);
282
283 /* take UVD block out of reset */
284 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
285 mdelay(5);
286
287 /* initialize UVD memory controller */
288 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
289 (1 << 21) | (1 << 9) | (1 << 20));
290
291#ifdef __BIG_ENDIAN
292 /* swap (8 in 32) RB and IB */
293 lmi_swap_cntl = 0xa;
294 mp_swap_cntl = 0;
295#endif
296 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
297 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
298
299 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
300 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
301 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
302 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
303 WREG32(mmUVD_MPC_SET_ALU, 0);
304 WREG32(mmUVD_MPC_SET_MUX, 0x88);
305
306 /* take all subblocks out of reset, except VCPU */
307 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
308 mdelay(5);
309
310 /* enable VCPU clock */
311 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
312
313 /* enable UMC */
314 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
315
316 /* boot up the VCPU */
317 WREG32(mmUVD_SOFT_RESET, 0);
318 mdelay(10);
319
320 for (i = 0; i < 10; ++i) {
321 uint32_t status;
322 for (j = 0; j < 100; ++j) {
323 status = RREG32(mmUVD_STATUS);
324 if (status & 2)
325 break;
326 mdelay(10);
327 }
328 r = 0;
329 if (status & 2)
330 break;
331
332 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
333 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
334 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
335 mdelay(10);
336 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
337 mdelay(10);
338 r = -1;
339 }
340
341 if (r) {
342 DRM_ERROR("UVD not responding, giving up!!!\n");
343 return r;
344 }
345
346 /* enable interupt */
347 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
348
349 /* force RBC into idle state */
350 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
351
352 /* Set the write pointer delay */
353 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
354
355 /* programm the 4GB memory segment for rptr and ring buffer */
356 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
357 (0x7 << 16) | (0x1 << 31));
358
359 /* Initialize the ring buffer's read and write pointers */
360 WREG32(mmUVD_RBC_RB_RPTR, 0x0);
361
362 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
363 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
364
365 /* set the ring address */
366 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
367
368 /* Set ring buffer size */
369 rb_bufsz = order_base_2(ring->ring_size);
370 rb_bufsz = (0x1 << 8) | rb_bufsz;
371 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
372
373 return 0;
374}
375
376/**
377 * uvd_v4_2_stop - stop UVD block
378 *
379 * @adev: amdgpu_device pointer
380 *
381 * stop the UVD block
382 */
383static void uvd_v4_2_stop(struct amdgpu_device *adev)
384{
385 /* force RBC into idle state */
386 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
387
388 /* Stall UMC and register bus before resetting VCPU */
389 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
390 mdelay(1);
391
392 /* put VCPU into reset */
393 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
394 mdelay(5);
395
396 /* disable VCPU clock */
397 WREG32(mmUVD_VCPU_CNTL, 0x0);
398
399 /* Unstall UMC and register bus */
400 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
401}
402
403/**
404 * uvd_v4_2_ring_emit_fence - emit an fence & trap command
405 *
406 * @ring: amdgpu_ring pointer
407 * @fence: fence to emit
408 *
409 * Write a fence and a trap command to the ring.
410 */
411static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
412 bool write64bit)
413{
414 WARN_ON(write64bit);
415
416 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
417 amdgpu_ring_write(ring, seq);
418 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
419 amdgpu_ring_write(ring, addr & 0xffffffff);
420 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
421 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
422 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
423 amdgpu_ring_write(ring, 0);
424
425 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
426 amdgpu_ring_write(ring, 0);
427 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
428 amdgpu_ring_write(ring, 0);
429 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
430 amdgpu_ring_write(ring, 2);
431}
432
433/**
434 * uvd_v4_2_ring_emit_semaphore - emit semaphore command
435 *
436 * @ring: amdgpu_ring pointer
437 * @semaphore: semaphore to emit commands for
438 * @emit_wait: true if we should emit a wait command
439 *
440 * Emit a semaphore command (either wait or signal) to the UVD ring.
441 */
442static bool uvd_v4_2_ring_emit_semaphore(struct amdgpu_ring *ring,
443 struct amdgpu_semaphore *semaphore,
444 bool emit_wait)
445{
446 uint64_t addr = semaphore->gpu_addr;
447
448 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
449 amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
450
451 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
452 amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
453
454 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
455 amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
456
457 return true;
458}
459
460/**
461 * uvd_v4_2_ring_test_ring - register write test
462 *
463 * @ring: amdgpu_ring pointer
464 *
465 * Test if we can successfully write to the context register
466 */
467static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
468{
469 struct amdgpu_device *adev = ring->adev;
470 uint32_t tmp = 0;
471 unsigned i;
472 int r;
473
474 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
475 r = amdgpu_ring_lock(ring, 3);
476 if (r) {
477 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
478 ring->idx, r);
479 return r;
480 }
481 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
482 amdgpu_ring_write(ring, 0xDEADBEEF);
483 amdgpu_ring_unlock_commit(ring);
484 for (i = 0; i < adev->usec_timeout; i++) {
485 tmp = RREG32(mmUVD_CONTEXT_ID);
486 if (tmp == 0xDEADBEEF)
487 break;
488 DRM_UDELAY(1);
489 }
490
491 if (i < adev->usec_timeout) {
492 DRM_INFO("ring test on %d succeeded in %d usecs\n",
493 ring->idx, i);
494 } else {
495 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
496 ring->idx, tmp);
497 r = -EINVAL;
498 }
499 return r;
500}
501
502/**
503 * uvd_v4_2_ring_emit_ib - execute indirect buffer
504 *
505 * @ring: amdgpu_ring pointer
506 * @ib: indirect buffer to execute
507 *
508 * Write ring commands to execute the indirect buffer
509 */
510static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
511 struct amdgpu_ib *ib)
512{
513 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
514 amdgpu_ring_write(ring, ib->gpu_addr);
515 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
516 amdgpu_ring_write(ring, ib->length_dw);
517}
518
519/**
520 * uvd_v4_2_ring_test_ib - test ib execution
521 *
522 * @ring: amdgpu_ring pointer
523 *
524 * Test if we can successfully execute an IB
525 */
526static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring)
527{
528 struct amdgpu_device *adev = ring->adev;
529 struct amdgpu_fence *fence = NULL;
530 int r;
531
532 r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
533 if (r) {
534 DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r);
535 return r;
536 }
537
538 r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
539 if (r) {
540 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
541 goto error;
542 }
543
544 r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);
545 if (r) {
546 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
547 goto error;
548 }
549
550 r = amdgpu_fence_wait(fence, false);
551 if (r) {
552 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
553 goto error;
554 }
555 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
556error:
557 amdgpu_fence_unref(&fence);
558 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
559 return r;
560}
561
562/**
563 * uvd_v4_2_mc_resume - memory controller programming
564 *
565 * @adev: amdgpu_device pointer
566 *
567 * Let the UVD memory controller know it's offsets
568 */
569static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
570{
571 uint64_t addr;
572 uint32_t size;
573
574 /* programm the VCPU memory controller bits 0-27 */
575 addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
576 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
577 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
578 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
579
580 addr += size;
581 size = AMDGPU_UVD_STACK_SIZE >> 3;
582 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
583 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
584
585 addr += size;
586 size = AMDGPU_UVD_HEAP_SIZE >> 3;
587 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
588 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
589
590 /* bits 28-31 */
591 addr = (adev->uvd.gpu_addr >> 28) & 0xF;
592 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
593
594 /* bits 32-39 */
595 addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
596 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
597
598 uvd_v4_2_init_cg(adev);
599}
600
601static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
602 bool enable)
603{
604 u32 orig, data;
605
606 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) {
607 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
608 data = 0xfff;
609 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
610
611 orig = data = RREG32(mmUVD_CGC_CTRL);
612 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
613 if (orig != data)
614 WREG32(mmUVD_CGC_CTRL, data);
615 } else {
616 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
617 data &= ~0xfff;
618 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
619
620 orig = data = RREG32(mmUVD_CGC_CTRL);
621 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
622 if (orig != data)
623 WREG32(mmUVD_CGC_CTRL, data);
624 }
625}
626
627static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
628 bool sw_mode)
629{
630 u32 tmp, tmp2;
631
632 tmp = RREG32(mmUVD_CGC_CTRL);
633 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
634 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
635 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
636 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
637
638 if (sw_mode) {
639 tmp &= ~0x7ffff800;
640 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
641 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
642 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
643 } else {
644 tmp |= 0x7ffff800;
645 tmp2 = 0;
646 }
647
648 WREG32(mmUVD_CGC_CTRL, tmp);
649 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
650}
651
652static void uvd_v4_2_init_cg(struct amdgpu_device *adev)
653{
654 bool hw_mode = true;
655
656 if (hw_mode) {
657 uvd_v4_2_set_dcm(adev, false);
658 } else {
659 u32 tmp = RREG32(mmUVD_CGC_CTRL);
660 tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
661 WREG32(mmUVD_CGC_CTRL, tmp);
662 }
663}
664
665static bool uvd_v4_2_is_idle(struct amdgpu_device *adev)
666{
667 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
668}
669
670static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev)
671{
672 unsigned i;
673
674 for (i = 0; i < adev->usec_timeout; i++) {
675 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
676 return 0;
677 }
678 return -ETIMEDOUT;
679}
680
681static int uvd_v4_2_soft_reset(struct amdgpu_device *adev)
682{
683 uvd_v4_2_stop(adev);
684
685 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
686 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
687 mdelay(5);
688
689 return uvd_v4_2_start(adev);
690}
691
692static void uvd_v4_2_print_status(struct amdgpu_device *adev)
693{
694 dev_info(adev->dev, "UVD 4.2 registers\n");
695 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
696 RREG32(mmUVD_SEMA_ADDR_LOW));
697 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
698 RREG32(mmUVD_SEMA_ADDR_HIGH));
699 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n",
700 RREG32(mmUVD_SEMA_CMD));
701 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
702 RREG32(mmUVD_GPCOM_VCPU_CMD));
703 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
704 RREG32(mmUVD_GPCOM_VCPU_DATA0));
705 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
706 RREG32(mmUVD_GPCOM_VCPU_DATA1));
707 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n",
708 RREG32(mmUVD_ENGINE_CNTL));
709 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
710 RREG32(mmUVD_UDEC_ADDR_CONFIG));
711 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
712 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
713 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
714 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
715 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n",
716 RREG32(mmUVD_SEMA_CNTL));
717 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n",
718 RREG32(mmUVD_LMI_EXT40_ADDR));
719 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n",
720 RREG32(mmUVD_CTX_INDEX));
721 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n",
722 RREG32(mmUVD_CTX_DATA));
723 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n",
724 RREG32(mmUVD_CGC_GATE));
725 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n",
726 RREG32(mmUVD_CGC_CTRL));
727 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n",
728 RREG32(mmUVD_LMI_CTRL2));
729 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n",
730 RREG32(mmUVD_MASTINT_EN));
731 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n",
732 RREG32(mmUVD_LMI_ADDR_EXT));
733 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n",
734 RREG32(mmUVD_LMI_CTRL));
735 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n",
736 RREG32(mmUVD_LMI_SWAP_CNTL));
737 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n",
738 RREG32(mmUVD_MP_SWAP_CNTL));
739 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n",
740 RREG32(mmUVD_MPC_SET_MUXA0));
741 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n",
742 RREG32(mmUVD_MPC_SET_MUXA1));
743 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n",
744 RREG32(mmUVD_MPC_SET_MUXB0));
745 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n",
746 RREG32(mmUVD_MPC_SET_MUXB1));
747 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n",
748 RREG32(mmUVD_MPC_SET_MUX));
749 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n",
750 RREG32(mmUVD_MPC_SET_ALU));
751 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
752 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
753 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
754 RREG32(mmUVD_VCPU_CACHE_SIZE0));
755 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
756 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
757 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
758 RREG32(mmUVD_VCPU_CACHE_SIZE1));
759 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
760 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
761 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
762 RREG32(mmUVD_VCPU_CACHE_SIZE2));
763 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n",
764 RREG32(mmUVD_VCPU_CNTL));
765 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n",
766 RREG32(mmUVD_SOFT_RESET));
767 dev_info(adev->dev, " UVD_RBC_IB_BASE=0x%08X\n",
768 RREG32(mmUVD_RBC_IB_BASE));
769 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n",
770 RREG32(mmUVD_RBC_IB_SIZE));
771 dev_info(adev->dev, " UVD_RBC_RB_BASE=0x%08X\n",
772 RREG32(mmUVD_RBC_RB_BASE));
773 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n",
774 RREG32(mmUVD_RBC_RB_RPTR));
775 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n",
776 RREG32(mmUVD_RBC_RB_WPTR));
777 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
778 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
779 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n",
780 RREG32(mmUVD_RBC_RB_CNTL));
781 dev_info(adev->dev, " UVD_STATUS=0x%08X\n",
782 RREG32(mmUVD_STATUS));
783 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
784 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
785 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
786 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
787 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
788 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
789 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
790 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
791 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
792 RREG32(mmUVD_CONTEXT_ID));
793}
794
795static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
796 struct amdgpu_irq_src *source,
797 unsigned type,
798 enum amdgpu_interrupt_state state)
799{
800 // TODO
801 return 0;
802}
803
804static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
805 struct amdgpu_irq_src *source,
806 struct amdgpu_iv_entry *entry)
807{
808 DRM_DEBUG("IH: UVD TRAP\n");
809 amdgpu_fence_process(&adev->uvd.ring);
810 return 0;
811}
812
813static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev,
814 enum amdgpu_clockgating_state state)
815{
816 bool gate = false;
817
818 if (state == AMDGPU_CG_STATE_GATE)
819 gate = true;
820
821 uvd_v4_2_enable_mgcg(adev, gate);
822
823 return 0;
824}
825
826static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev,
827 enum amdgpu_powergating_state state)
828{
829 /* This doesn't actually powergate the UVD block.
830 * That's done in the dpm code via the SMC. This
831 * just re-inits the block as necessary. The actual
832 * gating still happens in the dpm code. We should
833 * revisit this when there is a cleaner line between
834 * the smc and the hw blocks
835 */
836 if (state == AMDGPU_PG_STATE_GATE) {
837 uvd_v4_2_stop(adev);
838 return 0;
839 } else {
840 return uvd_v4_2_start(adev);
841 }
842}
843
844const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs = {
845 .early_init = uvd_v4_2_early_init,
846 .late_init = NULL,
847 .sw_init = uvd_v4_2_sw_init,
848 .sw_fini = uvd_v4_2_sw_fini,
849 .hw_init = uvd_v4_2_hw_init,
850 .hw_fini = uvd_v4_2_hw_fini,
851 .suspend = uvd_v4_2_suspend,
852 .resume = uvd_v4_2_resume,
853 .is_idle = uvd_v4_2_is_idle,
854 .wait_for_idle = uvd_v4_2_wait_for_idle,
855 .soft_reset = uvd_v4_2_soft_reset,
856 .print_status = uvd_v4_2_print_status,
857 .set_clockgating_state = uvd_v4_2_set_clockgating_state,
858 .set_powergating_state = uvd_v4_2_set_powergating_state,
859};
860
861static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
862 .get_rptr = uvd_v4_2_ring_get_rptr,
863 .get_wptr = uvd_v4_2_ring_get_wptr,
864 .set_wptr = uvd_v4_2_ring_set_wptr,
865 .parse_cs = amdgpu_uvd_ring_parse_cs,
866 .emit_ib = uvd_v4_2_ring_emit_ib,
867 .emit_fence = uvd_v4_2_ring_emit_fence,
868 .emit_semaphore = uvd_v4_2_ring_emit_semaphore,
869 .test_ring = uvd_v4_2_ring_test_ring,
870 .test_ib = uvd_v4_2_ring_test_ib,
871 .is_lockup = amdgpu_ring_test_lockup,
872};
873
874static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
875{
876 adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;
877}
878
879static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
880 .set = uvd_v4_2_set_interrupt_state,
881 .process = uvd_v4_2_process_interrupt,
882};
883
884static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
885{
886 adev->uvd.irq.num_types = 1;
887 adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;
888}
Linux 6.x block layer and io_uring tree(s)