[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vm.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#ifndef __AMDGPU_VM_H__
#define __AMDGPU_VM_H__

#include <linux/idr.h>
#include <linux/kfifo.h>
#include <linux/rbtree.h>
#include <drm/gpu_scheduler.h>
#include <drm/drm_file.h>

#include "amdgpu_sync.h"
#include "amdgpu_ring.h"
#include "amdgpu_ids.h"

struct amdgpu_bo_va;
struct amdgpu_job;
struct amdgpu_bo_list_entry;

/*
 * GPUVM handling
 */

/* Maximum number of PTEs the hardware can write with one command */
#define AMDGPU_VM_MAX_UPDATE_SIZE	0x3FFFF

/* number of entries in page table */
#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)

/* PTBs (Page Table Blocks) need to be aligned to 32K */
#define AMDGPU_VM_PTB_ALIGN_SIZE   32768

#define AMDGPU_PTE_VALID	(1ULL << 0)
#define AMDGPU_PTE_SYSTEM	(1ULL << 1)
#define AMDGPU_PTE_SNOOPED	(1ULL << 2)

/* VI only */
#define AMDGPU_PTE_EXECUTABLE	(1ULL << 4)

#define AMDGPU_PTE_READABLE	(1ULL << 5)
#define AMDGPU_PTE_WRITEABLE	(1ULL << 6)

#define AMDGPU_PTE_FRAG(x)	((x & 0x1fULL) << 7)

/* TILED for VEGA10, reserved for older ASICs  */
#define AMDGPU_PTE_PRT		(1ULL << 51)

/* PDE is handled as PTE for VEGA10 */
#define AMDGPU_PDE_PTE		(1ULL << 54)

/* PTE is handled as PDE for VEGA10 (Translate Further) */
#define AMDGPU_PTE_TF		(1ULL << 56)

/* PDE Block Fragment Size for VEGA10 */
#define AMDGPU_PDE_BFS(a)	((uint64_t)a << 59)


/* For GFX9 */
#define AMDGPU_PTE_MTYPE(a)    ((uint64_t)a << 57)
#define AMDGPU_PTE_MTYPE_MASK	AMDGPU_PTE_MTYPE(3ULL)

#define AMDGPU_MTYPE_NC 0
#define AMDGPU_MTYPE_CC 2

#define AMDGPU_PTE_DEFAULT_ATC  (AMDGPU_PTE_SYSTEM      \
                                | AMDGPU_PTE_SNOOPED    \
                                | AMDGPU_PTE_EXECUTABLE \
                                | AMDGPU_PTE_READABLE   \
                                | AMDGPU_PTE_WRITEABLE  \
                                | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))

/* How to programm VM fault handling */
#define AMDGPU_VM_FAULT_STOP_NEVER	0
#define AMDGPU_VM_FAULT_STOP_FIRST	1
#define AMDGPU_VM_FAULT_STOP_ALWAYS	2

/* max number of VMHUB */
#define AMDGPU_MAX_VMHUBS			2
#define AMDGPU_GFXHUB				0
#define AMDGPU_MMHUB				1

/* hardcode that limit for now */
#define AMDGPU_VA_RESERVED_SIZE			(1ULL << 20)

/* VA hole for 48bit addresses on Vega10 */
#define AMDGPU_VA_HOLE_START			0x0000800000000000ULL
#define AMDGPU_VA_HOLE_END			0xffff800000000000ULL

/*
 * Hardware is programmed as if the hole doesn't exists with start and end
 * address values.
 *
 * This mask is used to remove the upper 16bits of the VA and so come up with
 * the linear addr value.
 */
#define AMDGPU_VA_HOLE_MASK			0x0000ffffffffffffULL

/* max vmids dedicated for process */
#define AMDGPU_VM_MAX_RESERVED_VMID	1

#define AMDGPU_VM_CONTEXT_GFX 0
#define AMDGPU_VM_CONTEXT_COMPUTE 1

/* See vm_update_mode */
#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)

/* VMPT level enumerate, and the hiberachy is:
 * PDB2->PDB1->PDB0->PTB
 */
enum amdgpu_vm_level {
	AMDGPU_VM_PDB2,
	AMDGPU_VM_PDB1,
	AMDGPU_VM_PDB0,
	AMDGPU_VM_PTB
};

/* base structure for tracking BO usage in a VM */
struct amdgpu_vm_bo_base {
	/* constant after initialization */
	struct amdgpu_vm		*vm;
	struct amdgpu_bo		*bo;

	/* protected by bo being reserved */
	struct list_head		bo_list;

	/* protected by spinlock */
	struct list_head		vm_status;

	/* protected by the BO being reserved */
	bool				moved;
};

struct amdgpu_vm_pt {
	struct amdgpu_vm_bo_base	base;
	bool				huge;

	/* array of page tables, one for each directory entry */
	struct amdgpu_vm_pt		*entries;
};

/* provided by hw blocks that can write ptes, e.g., sdma */
struct amdgpu_vm_pte_funcs {
	/* number of dw to reserve per operation */
	unsigned	copy_pte_num_dw;

	/* copy pte entries from GART */
	void (*copy_pte)(struct amdgpu_ib *ib,
			 uint64_t pe, uint64_t src,
			 unsigned count);

	/* write pte one entry at a time with addr mapping */
	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
			  uint64_t value, unsigned count,
			  uint32_t incr);
	/* for linear pte/pde updates without addr mapping */
	void (*set_pte_pde)(struct amdgpu_ib *ib,
			    uint64_t pe,
			    uint64_t addr, unsigned count,
			    uint32_t incr, uint64_t flags);
};

#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
#define AMDGPU_VM_FAULT_ADDR(fault)  ((u64)(fault) & 0xfffffffff000ULL)


struct amdgpu_task_info {
	char	process_name[TASK_COMM_LEN];
	char	task_name[TASK_COMM_LEN];
	pid_t	pid;
	pid_t	tgid;
};

struct amdgpu_vm {
	/* tree of virtual addresses mapped */
	struct rb_root_cached	va;

	/* BOs who needs a validation */
	struct list_head	evicted;

	/* PT BOs which relocated and their parent need an update */
	struct list_head	relocated;

	/* BOs moved, but not yet updated in the PT */
	struct list_head	moved;
	spinlock_t		moved_lock;

	/* All BOs of this VM not currently in the state machine */
	struct list_head	idle;

	/* BO mappings freed, but not yet updated in the PT */
	struct list_head	freed;

	/* contains the page directory */
	struct amdgpu_vm_pt     root;
	struct dma_fence	*last_update;

	/* Scheduler entity for page table updates */
	struct drm_sched_entity	entity;

	unsigned int		pasid;
	/* dedicated to vm */
	struct amdgpu_vmid	*reserved_vmid[AMDGPU_MAX_VMHUBS];

	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
	bool                    use_cpu_for_update;

	/* Flag to indicate ATS support from PTE for GFX9 */
	bool			pte_support_ats;

	/* Up to 128 pending retry page faults */
	DECLARE_KFIFO(faults, u64, 128);

	/* Limit non-retry fault storms */
	unsigned int		fault_credit;

	/* Points to the KFD process VM info */
	struct amdkfd_process_info *process_info;

	/* List node in amdkfd_process_info.vm_list_head */
	struct list_head	vm_list_node;

	/* Valid while the PD is reserved or fenced */
	uint64_t		pd_phys_addr;

	/* Some basic info about the task */
	struct amdgpu_task_info task_info;
};

struct amdgpu_vm_manager {
	/* Handling of VMIDs */
	struct amdgpu_vmid_mgr			id_mgr[AMDGPU_MAX_VMHUBS];

	/* Handling of VM fences */
	u64					fence_context;
	unsigned				seqno[AMDGPU_MAX_RINGS];

	uint64_t				max_pfn;
	uint32_t				num_level;
	uint32_t				block_size;
	uint32_t				fragment_size;
	enum amdgpu_vm_level			root_level;
	/* vram base address for page table entry  */
	u64					vram_base_offset;
	/* vm pte handling */
	const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
	struct amdgpu_ring                      *vm_pte_rings[AMDGPU_MAX_RINGS];
	unsigned				vm_pte_num_rings;
	atomic_t				vm_pte_next_ring;

	/* partial resident texture handling */
	spinlock_t				prt_lock;
	atomic_t				num_prt_users;

	/* controls how VM page tables are updated for Graphics and Compute.
	 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
	 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
	 */
	int					vm_update_mode;

	/* PASID to VM mapping, will be used in interrupt context to
	 * look up VM of a page fault
	 */
	struct idr				pasid_idr;
	spinlock_t				pasid_lock;
};

#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))

void amdgpu_vm_manager_init(struct amdgpu_device *adev);
void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
		   int vm_context, unsigned int pasid);
int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
				  unsigned int pasid);
void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
			 struct list_head *validated,
			 struct amdgpu_bo_list_entry *entry);
bool amdgpu_vm_ready(struct amdgpu_vm *vm);
int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
			      int (*callback)(void *p, struct amdgpu_bo *bo),
			      void *param);
int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
			struct amdgpu_vm *vm,
			uint64_t saddr, uint64_t size);
int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
int amdgpu_vm_update_directories(struct amdgpu_device *adev,
				 struct amdgpu_vm *vm);
int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
			  struct amdgpu_vm *vm,
			  struct dma_fence **fence);
int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
			   struct amdgpu_vm *vm);
int amdgpu_vm_bo_update(struct amdgpu_device *adev,
			struct amdgpu_bo_va *bo_va,
			bool clear);
void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
			     struct amdgpu_bo *bo, bool evicted);
struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
				       struct amdgpu_bo *bo);
struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
				      struct amdgpu_vm *vm,
				      struct amdgpu_bo *bo);
int amdgpu_vm_bo_map(struct amdgpu_device *adev,
		     struct amdgpu_bo_va *bo_va,
		     uint64_t addr, uint64_t offset,
		     uint64_t size, uint64_t flags);
int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
			     struct amdgpu_bo_va *bo_va,
			     uint64_t addr, uint64_t offset,
			     uint64_t size, uint64_t flags);
int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
		       struct amdgpu_bo_va *bo_va,
		       uint64_t addr);
int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
				struct amdgpu_vm *vm,
				uint64_t saddr, uint64_t size);
struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
							 uint64_t addr);
void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
		      struct amdgpu_bo_va *bo_va);
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
			   uint32_t fragment_size_default, unsigned max_level,
			   unsigned max_bits);
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
				  struct amdgpu_job *job);
void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);

void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
			 struct amdgpu_task_info *task_info);

void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);

#endif
Commit	Line	Data
073440d2 CK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Christian König
	23	*/
	24	#ifndef __AMDGPU_VM_H__
	25	#define __AMDGPU_VM_H__
	26
02208441	27	#include <linux/idr.h>
1b1f42d8 LS	28	#include <linux/kfifo.h>
	29	#include <linux/rbtree.h>
	30	#include <drm/gpu_scheduler.h>
61b100e9	31	#include <drm/drm_file.h>
073440d2	32
073440d2 CK	33	#include "amdgpu_sync.h"
073440d2 CK	34	#include "amdgpu_ring.h"
620f774f	35	#include "amdgpu_ids.h"
073440d2 CK	36
	37	struct amdgpu_bo_va;
	38	struct amdgpu_job;
	39	struct amdgpu_bo_list_entry;
	40
	41	/*
	42	* GPUVM handling
	43	*/
	44
073440d2 CK	45	/* Maximum number of PTEs the hardware can write with one command */
	46	#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
	47
	48	/* number of entries in page table */
36b32a68	49	#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
073440d2 CK	50
	51	/* PTBs (Page Table Blocks) need to be aligned to 32K */
	52	#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
	53
35ba15f0 CK	54	#define AMDGPU_PTE_VALID (1ULL << 0)
	55	#define AMDGPU_PTE_SYSTEM (1ULL << 1)
	56	#define AMDGPU_PTE_SNOOPED (1ULL << 2)
073440d2 CK	57
073440d2 CK	58	/* VI only */
35ba15f0	59	#define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
073440d2	60
35ba15f0 CK	61	#define AMDGPU_PTE_READABLE (1ULL << 5)
35ba15f0 CK	62	#define AMDGPU_PTE_WRITEABLE (1ULL << 6)
073440d2	63
982a1348	64	#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
073440d2	65
d0766e98 ZJ	66	/* TILED for VEGA10, reserved for older ASICs */
d0766e98 ZJ	67	#define AMDGPU_PTE_PRT (1ULL << 51)
284710fa	68
cf2f0a37 AD	69	/* PDE is handled as PTE for VEGA10 */
	70	#define AMDGPU_PDE_PTE (1ULL << 54)
	71
6a42fd6f CK	72	/* PTE is handled as PDE for VEGA10 (Translate Further) */
	73	#define AMDGPU_PTE_TF (1ULL << 56)
	74
	75	/* PDE Block Fragment Size for VEGA10 */
	76	#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
	77
959a2091 YZ	78
959a2091 YZ	79	/* For GFX9 */
ca02061c AD	80	#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
	81	#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
	82
959a2091	83	#define AMDGPU_MTYPE_NC 0
6d16dac8 YZ	84	#define AMDGPU_MTYPE_CC 2
	85
	86	#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
	87	\| AMDGPU_PTE_SNOOPED \
	88	\| AMDGPU_PTE_EXECUTABLE \
	89	\| AMDGPU_PTE_READABLE \
	90	\| AMDGPU_PTE_WRITEABLE \
	91	\| AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))
	92
073440d2 CK	93	/* How to programm VM fault handling */
	94	#define AMDGPU_VM_FAULT_STOP_NEVER 0
	95	#define AMDGPU_VM_FAULT_STOP_FIRST 1
	96	#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
	97
eb60ef2b CK	98	/* max number of VMHUB */
	99	#define AMDGPU_MAX_VMHUBS 2
	100	#define AMDGPU_GFXHUB 0
	101	#define AMDGPU_MMHUB 1
	102
	103	/* hardcode that limit for now */
18d09e63	104	#define AMDGPU_VA_RESERVED_SIZE (1ULL << 20)
ff4cd389	105
bb7939b2 CK	106	/* VA hole for 48bit addresses on Vega10 */
	107	#define AMDGPU_VA_HOLE_START 0x0000800000000000ULL
	108	#define AMDGPU_VA_HOLE_END 0xffff800000000000ULL
	109
	110	/*
	111	* Hardware is programmed as if the hole doesn't exists with start and end
	112	* address values.
	113	*
	114	* This mask is used to remove the upper 16bits of the VA and so come up with
	115	* the linear addr value.
	116	*/
	117	#define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL
	118
c3505770 CZ	119	/* max vmids dedicated for process */
c3505770 CZ	120	#define AMDGPU_VM_MAX_RESERVED_VMID 1
eb60ef2b	121
9a4b7d4c HK	122	#define AMDGPU_VM_CONTEXT_GFX 0
	123	#define AMDGPU_VM_CONTEXT_COMPUTE 1
	124
	125	/* See vm_update_mode */
	126	#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
	127	#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
	128
196f7489 CZ	129	/* VMPT level enumerate, and the hiberachy is:
	130	* PDB2->PDB1->PDB0->PTB
	131	*/
	132	enum amdgpu_vm_level {
	133	AMDGPU_VM_PDB2,
	134	AMDGPU_VM_PDB1,
	135	AMDGPU_VM_PDB0,
	136	AMDGPU_VM_PTB
	137	};
	138
ec681545 CK	139	/* base structure for tracking BO usage in a VM */
	140	struct amdgpu_vm_bo_base {
	141	/* constant after initialization */
	142	struct amdgpu_vm *vm;
	143	struct amdgpu_bo *bo;
	144
	145	/* protected by bo being reserved */
	146	struct list_head bo_list;
	147
	148	/* protected by spinlock */
	149	struct list_head vm_status;
3d7d4d3a CK	150
	151	/* protected by the BO being reserved */
	152	bool moved;
ec681545	153	};
9a4b7d4c	154
073440d2	155	struct amdgpu_vm_pt {
3f3333f8	156	struct amdgpu_vm_bo_base base;
78eb2f0c	157	bool huge;
67003a15 CK	158
67003a15 CK	159	/* array of page tables, one for each directory entry */
3f3333f8	160	struct amdgpu_vm_pt *entries;
073440d2 CK	161	};
073440d2 CK	162
4473e1db HR	163	/* provided by hw blocks that can write ptes, e.g., sdma */
	164	struct amdgpu_vm_pte_funcs {
	165	/* number of dw to reserve per operation */
	166	unsigned copy_pte_num_dw;
	167
	168	/* copy pte entries from GART */
	169	void (copy_pte)(struct amdgpu_ib ib,
	170	uint64_t pe, uint64_t src,
	171	unsigned count);
	172
	173	/* write pte one entry at a time with addr mapping */
	174	void (write_pte)(struct amdgpu_ib ib, uint64_t pe,
	175	uint64_t value, unsigned count,
	176	uint32_t incr);
	177	/* for linear pte/pde updates without addr mapping */
	178	void (set_pte_pde)(struct amdgpu_ib ib,
	179	uint64_t pe,
	180	uint64_t addr, unsigned count,
	181	uint32_t incr, uint64_t flags);
	182	};
	183
a2f14820 FK	184	#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) \| (addr))
	185	#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
	186	#define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL)
	187
2aa37bf5 AG	188
	189	struct amdgpu_task_info {
	190	char process_name[TASK_COMM_LEN];
	191	char task_name[TASK_COMM_LEN];
	192	pid_t pid;
	193	pid_t tgid;
	194	};
	195
073440d2 CK	196	struct amdgpu_vm {
073440d2 CK	197	/* tree of virtual addresses mapped */
f808c13f	198	struct rb_root_cached va;
073440d2	199
3f3333f8 CK	200	/* BOs who needs a validation */
	201	struct list_head evicted;
	202
ea09729c CK	203	/* PT BOs which relocated and their parent need an update */
	204	struct list_head relocated;
	205
073440d2	206	/* BOs moved, but not yet updated in the PT */
27c7b9ae	207	struct list_head moved;
af4c0f65	208	spinlock_t moved_lock;
073440d2	209
806f043f CK	210	/* All BOs of this VM not currently in the state machine */
	211	struct list_head idle;
	212
073440d2 CK	213	/* BO mappings freed, but not yet updated in the PT */
	214	struct list_head freed;
	215
	216	/* contains the page directory */
67003a15	217	struct amdgpu_vm_pt root;
d5884513	218	struct dma_fence *last_update;
073440d2	219
073440d2	220	/* Scheduler entity for page table updates */
1b1f42d8	221	struct drm_sched_entity entity;
073440d2	222
02208441	223	unsigned int pasid;
36bbf3bf	224	/* dedicated to vm */
620f774f	225	struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
9a4b7d4c HK	226
	227	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
	228	bool use_cpu_for_update;
51ac7eec YZ	229
	230	/* Flag to indicate ATS support from PTE for GFX9 */
	231	bool pte_support_ats;
a2f14820	232
c98171cc	233	/* Up to 128 pending retry page faults */
a2f14820	234	DECLARE_KFIFO(faults, u64, 128);
c98171cc FK	235
	236	/* Limit non-retry fault storms */
	237	unsigned int fault_credit;
5b21d3e5 FK	238
	239	/* Points to the KFD process VM info */
	240	struct amdkfd_process_info *process_info;
	241
	242	/* List node in amdkfd_process_info.vm_list_head */
	243	struct list_head vm_list_node;
	244
	245	/* Valid while the PD is reserved or fenced */
	246	uint64_t pd_phys_addr;
2aa37bf5 AG	247
	248	/* Some basic info about the task */
	249	struct amdgpu_task_info task_info;
073440d2 CK	250	};
073440d2 CK	251
073440d2 CK	252	struct amdgpu_vm_manager {
073440d2 CK	253	/* Handling of VMIDs */
620f774f	254	struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
073440d2 CK	255
	256	/* Handling of VM fences */
	257	u64 fence_context;
	258	unsigned seqno[AMDGPU_MAX_RINGS];
	259
22770e5a	260	uint64_t max_pfn;
8437a097	261	uint32_t num_level;
36b32a68	262	uint32_t block_size;
e618d306	263	uint32_t fragment_size;
196f7489	264	enum amdgpu_vm_level root_level;
073440d2 CK	265	/* vram base address for page table entry */
073440d2 CK	266	u64 vram_base_offset;
073440d2 CK	267	/* vm pte handling */
	268	const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
	269	struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
	270	unsigned vm_pte_num_rings;
	271	atomic_t vm_pte_next_ring;
284710fa CK	272
	273	/* partial resident texture handling */
	274	spinlock_t prt_lock;
451bc8eb	275	atomic_t num_prt_users;
9a4b7d4c HK	276
	277	/* controls how VM page tables are updated for Graphics and Compute.
	278	* BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
	279	* BIT1[= 0] Compute updated by SDMA [= 1] by CPU
	280	*/
	281	int vm_update_mode;
02208441 FK	282
	283	/* PASID to VM mapping, will be used in interrupt context to
	284	* look up VM of a page fault
	285	*/
	286	struct idr pasid_idr;
	287	spinlock_t pasid_lock;
073440d2 CK	288	};
073440d2 CK	289
4473e1db HR	290	#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
	291	#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
	292	#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
	293
073440d2 CK	294	void amdgpu_vm_manager_init(struct amdgpu_device *adev);
073440d2 CK	295	void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
9a4b7d4c	296	int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm,
02208441	297	int vm_context, unsigned int pasid);
b236fa1d	298	int amdgpu_vm_make_compute(struct amdgpu_device adev, struct amdgpu_vm vm);
073440d2	299	void amdgpu_vm_fini(struct amdgpu_device adev, struct amdgpu_vm vm);
c98171cc FK	300	bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
c98171cc FK	301	unsigned int pasid);
073440d2 CK	302	void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
	303	struct list_head *validated,
	304	struct amdgpu_bo_list_entry *entry);
3f3333f8	305	bool amdgpu_vm_ready(struct amdgpu_vm *vm);
073440d2 CK	306	int amdgpu_vm_validate_pt_bos(struct amdgpu_device adev, struct amdgpu_vm vm,
	307	int (callback)(void p, struct amdgpu_bo *bo),
	308	void *param);
663e4577 CK	309	int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
	310	struct amdgpu_vm *vm,
	311	uint64_t saddr, uint64_t size);
8fdf074f	312	int amdgpu_vm_flush(struct amdgpu_ring ring, struct amdgpu_job job, bool need_pipe_sync);
194d2161 CK	313	int amdgpu_vm_update_directories(struct amdgpu_device *adev,
194d2161 CK	314	struct amdgpu_vm *vm);
073440d2	315	int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
f3467818 NH	316	struct amdgpu_vm *vm,
f3467818 NH	317	struct dma_fence **fence);
73fb16e7	318	int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
4e55eb38	319	struct amdgpu_vm *vm);
073440d2 CK	320	int amdgpu_vm_bo_update(struct amdgpu_device *adev,
	321	struct amdgpu_bo_va *bo_va,
	322	bool clear);
	323	void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
3f3333f8	324	struct amdgpu_bo *bo, bool evicted);
073440d2 CK	325	struct amdgpu_bo_va amdgpu_vm_bo_find(struct amdgpu_vm vm,
	326	struct amdgpu_bo *bo);
	327	struct amdgpu_bo_va amdgpu_vm_bo_add(struct amdgpu_device adev,
	328	struct amdgpu_vm *vm,
	329	struct amdgpu_bo *bo);
	330	int amdgpu_vm_bo_map(struct amdgpu_device *adev,
	331	struct amdgpu_bo_va *bo_va,
	332	uint64_t addr, uint64_t offset,
268c3001	333	uint64_t size, uint64_t flags);
80f95c57 CK	334	int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
	335	struct amdgpu_bo_va *bo_va,
	336	uint64_t addr, uint64_t offset,
	337	uint64_t size, uint64_t flags);
073440d2 CK	338	int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
	339	struct amdgpu_bo_va *bo_va,
	340	uint64_t addr);
dc54d3d1 CK	341	int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
	342	struct amdgpu_vm *vm,
	343	uint64_t saddr, uint64_t size);
aebc5e6f CK	344	struct amdgpu_bo_va_mapping amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm vm,
aebc5e6f CK	345	uint64_t addr);
8ab19ea6	346	void amdgpu_vm_bo_trace_cs(struct amdgpu_vm vm, struct ww_acquire_ctx ticket);
073440d2 CK	347	void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
073440d2 CK	348	struct amdgpu_bo_va *bo_va);
fdd5faaa	349	void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
f3368128 CK	350	uint32_t fragment_size_default, unsigned max_level,
f3368128 CK	351	unsigned max_bits);
cfbcacf4	352	int amdgpu_vm_ioctl(struct drm_device dev, void data, struct drm_file *filp);
b9bf33d5 CZ	353	bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
b9bf33d5 CZ	354	struct amdgpu_job *job);
e59c0205	355	void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
073440d2	356
2aa37bf5 AG	357	void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
	358	struct amdgpu_task_info *task_info);
	359
	360	void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
	361
073440d2	362	#endif