[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vm.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#ifndef __AMDGPU_VM_H__
#define __AMDGPU_VM_H__

#include <linux/rbtree.h>
#include <linux/idr.h>

#include "gpu_scheduler.h"
#include "amdgpu_sync.h"
#include "amdgpu_ring.h"

struct amdgpu_bo_va;
struct amdgpu_job;
struct amdgpu_bo_list_entry;

/*
 * GPUVM handling
 */

/* maximum number of VMIDs */
#define AMDGPU_NUM_VM	16

/* Maximum number of PTEs the hardware can write with one command */
#define AMDGPU_VM_MAX_UPDATE_SIZE	0x3FFFF

/* number of entries in page table */
#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)

/* PTBs (Page Table Blocks) need to be aligned to 32K */
#define AMDGPU_VM_PTB_ALIGN_SIZE   32768

#define AMDGPU_PTE_VALID	(1ULL << 0)
#define AMDGPU_PTE_SYSTEM	(1ULL << 1)
#define AMDGPU_PTE_SNOOPED	(1ULL << 2)

/* VI only */
#define AMDGPU_PTE_EXECUTABLE	(1ULL << 4)

#define AMDGPU_PTE_READABLE	(1ULL << 5)
#define AMDGPU_PTE_WRITEABLE	(1ULL << 6)

#define AMDGPU_PTE_FRAG(x)	((x & 0x1fULL) << 7)

/* TILED for VEGA10, reserved for older ASICs  */
#define AMDGPU_PTE_PRT		(1ULL << 51)

/* PDE is handled as PTE for VEGA10 */
#define AMDGPU_PDE_PTE		(1ULL << 54)

/* VEGA10 only */
#define AMDGPU_PTE_MTYPE(a)    ((uint64_t)a << 57)
#define AMDGPU_PTE_MTYPE_MASK	AMDGPU_PTE_MTYPE(3ULL)

/* For Raven */
#define AMDGPU_MTYPE_CC 2

#define AMDGPU_PTE_DEFAULT_ATC  (AMDGPU_PTE_SYSTEM      \
                                | AMDGPU_PTE_SNOOPED    \
                                | AMDGPU_PTE_EXECUTABLE \
                                | AMDGPU_PTE_READABLE   \
                                | AMDGPU_PTE_WRITEABLE  \
                                | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))

/* How to programm VM fault handling */
#define AMDGPU_VM_FAULT_STOP_NEVER	0
#define AMDGPU_VM_FAULT_STOP_FIRST	1
#define AMDGPU_VM_FAULT_STOP_ALWAYS	2

/* max number of VMHUB */
#define AMDGPU_MAX_VMHUBS			2
#define AMDGPU_GFXHUB				0
#define AMDGPU_MMHUB				1

/* hardcode that limit for now */
#define AMDGPU_VA_RESERVED_SIZE			(8ULL << 20)

/* VA hole for 48bit addresses on Vega10 */
#define AMDGPU_VA_HOLE_START			0x0000800000000000ULL
#define AMDGPU_VA_HOLE_END			0xffff800000000000ULL

/*
 * Hardware is programmed as if the hole doesn't exists with start and end
 * address values.
 *
 * This mask is used to remove the upper 16bits of the VA and so come up with
 * the linear addr value.
 */
#define AMDGPU_VA_HOLE_MASK			0x0000ffffffffffffULL

/* max vmids dedicated for process */
#define AMDGPU_VM_MAX_RESERVED_VMID	1

#define AMDGPU_VM_CONTEXT_GFX 0
#define AMDGPU_VM_CONTEXT_COMPUTE 1

/* See vm_update_mode */
#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)

/* base structure for tracking BO usage in a VM */
struct amdgpu_vm_bo_base {
	/* constant after initialization */
	struct amdgpu_vm		*vm;
	struct amdgpu_bo		*bo;

	/* protected by bo being reserved */
	struct list_head		bo_list;

	/* protected by spinlock */
	struct list_head		vm_status;

	/* protected by the BO being reserved */
	bool				moved;
};

struct amdgpu_vm_pt {
	struct amdgpu_vm_bo_base	base;
	uint64_t			addr;

	/* array of page tables, one for each directory entry */
	struct amdgpu_vm_pt		*entries;
	unsigned			last_entry_used;
};

#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
#define AMDGPU_VM_FAULT_ADDR(fault)  ((u64)(fault) & 0xfffffffff000ULL)

struct amdgpu_vm {
	/* tree of virtual addresses mapped */
	struct rb_root_cached	va;

	/* protecting invalidated */
	spinlock_t		status_lock;

	/* BOs who needs a validation */
	struct list_head	evicted;

	/* PT BOs which relocated and their parent need an update */
	struct list_head	relocated;

	/* BOs moved, but not yet updated in the PT */
	struct list_head	moved;

	/* BO mappings freed, but not yet updated in the PT */
	struct list_head	freed;

	/* contains the page directory */
	struct amdgpu_vm_pt     root;
	struct dma_fence	*last_update;

	/* protecting freed */
	spinlock_t		freed_lock;

	/* Scheduler entity for page table updates */
	struct amd_sched_entity	entity;

	/* client id and PASID (TODO: replace client_id with PASID) */
	u64                     client_id;
	unsigned int		pasid;
	/* dedicated to vm */
	struct amdgpu_vm_id	*reserved_vmid[AMDGPU_MAX_VMHUBS];

	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
	bool                    use_cpu_for_update;

	/* Flag to indicate ATS support from PTE for GFX9 */
	bool			pte_support_ats;

	/* Up to 128 pending retry page faults */
	DECLARE_KFIFO(faults, u64, 128);

	/* Limit non-retry fault storms */
	unsigned int		fault_credit;
};

struct amdgpu_vm_id {
	struct list_head	list;
	struct amdgpu_sync	active;
	struct dma_fence		*last_flush;
	atomic64_t		owner;

	uint64_t		pd_gpu_addr;
	/* last flushed PD/PT update */
	struct dma_fence		*flushed_updates;

	uint32_t                current_gpu_reset_count;

	uint32_t		gds_base;
	uint32_t		gds_size;
	uint32_t		gws_base;
	uint32_t		gws_size;
	uint32_t		oa_base;
	uint32_t		oa_size;
};

struct amdgpu_vm_id_manager {
	struct mutex		lock;
	unsigned		num_ids;
	struct list_head	ids_lru;
	struct amdgpu_vm_id	ids[AMDGPU_NUM_VM];
	atomic_t		reserved_vmid_num;
};

struct amdgpu_vm_manager {
	/* Handling of VMIDs */
	struct amdgpu_vm_id_manager		id_mgr[AMDGPU_MAX_VMHUBS];

	/* Handling of VM fences */
	u64					fence_context;
	unsigned				seqno[AMDGPU_MAX_RINGS];

	uint64_t				max_pfn;
	uint32_t				num_level;
	uint32_t				block_size;
	uint32_t				fragment_size;
	/* vram base address for page table entry  */
	u64					vram_base_offset;
	/* vm pte handling */
	const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
	struct amdgpu_ring                      *vm_pte_rings[AMDGPU_MAX_RINGS];
	unsigned				vm_pte_num_rings;
	atomic_t				vm_pte_next_ring;
	/* client id counter */
	atomic64_t				client_counter;

	/* partial resident texture handling */
	spinlock_t				prt_lock;
	atomic_t				num_prt_users;

	/* controls how VM page tables are updated for Graphics and Compute.
	 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
	 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
	 */
	int					vm_update_mode;

	/* PASID to VM mapping, will be used in interrupt context to
	 * look up VM of a page fault
	 */
	struct idr				pasid_idr;
	spinlock_t				pasid_lock;
};

int amdgpu_vm_alloc_pasid(unsigned int bits);
void amdgpu_vm_free_pasid(unsigned int pasid);
void amdgpu_vm_manager_init(struct amdgpu_device *adev);
void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
		   int vm_context, unsigned int pasid);
void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
				  unsigned int pasid);
void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
			 struct list_head *validated,
			 struct amdgpu_bo_list_entry *entry);
bool amdgpu_vm_ready(struct amdgpu_vm *vm);
int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
			      int (*callback)(void *p, struct amdgpu_bo *bo),
			      void *param);
int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
			struct amdgpu_vm *vm,
			uint64_t saddr, uint64_t size);
int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
		      struct amdgpu_sync *sync, struct dma_fence *fence,
		      struct amdgpu_job *job);
int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
			unsigned vmid);
void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev);
int amdgpu_vm_update_directories(struct amdgpu_device *adev,
				 struct amdgpu_vm *vm);
int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
			  struct amdgpu_vm *vm,
			  struct dma_fence **fence);
int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
			   struct amdgpu_vm *vm);
int amdgpu_vm_bo_update(struct amdgpu_device *adev,
			struct amdgpu_bo_va *bo_va,
			bool clear);
void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
			     struct amdgpu_bo *bo, bool evicted);
struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
				       struct amdgpu_bo *bo);
struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
				      struct amdgpu_vm *vm,
				      struct amdgpu_bo *bo);
int amdgpu_vm_bo_map(struct amdgpu_device *adev,
		     struct amdgpu_bo_va *bo_va,
		     uint64_t addr, uint64_t offset,
		     uint64_t size, uint64_t flags);
int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
			     struct amdgpu_bo_va *bo_va,
			     uint64_t addr, uint64_t offset,
			     uint64_t size, uint64_t flags);
int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
		       struct amdgpu_bo_va *bo_va,
		       uint64_t addr);
int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
				struct amdgpu_vm *vm,
				uint64_t saddr, uint64_t size);
struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
							 uint64_t addr);
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
		      struct amdgpu_bo_va *bo_va);
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
			   uint32_t fragment_size_default, unsigned max_level,
			   unsigned max_bits);
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
				  struct amdgpu_job *job);
void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);

#endif
Commit	Line	Data
073440d2 CK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Christian König
	23	*/
	24	#ifndef __AMDGPU_VM_H__
	25	#define __AMDGPU_VM_H__
	26
	27	#include <linux/rbtree.h>
02208441	28	#include <linux/idr.h>
073440d2 CK	29
	30	#include "gpu_scheduler.h"
	31	#include "amdgpu_sync.h"
	32	#include "amdgpu_ring.h"
	33
	34	struct amdgpu_bo_va;
	35	struct amdgpu_job;
	36	struct amdgpu_bo_list_entry;
	37
	38	/*
	39	* GPUVM handling
	40	*/
	41
	42	/* maximum number of VMIDs */
	43	#define AMDGPU_NUM_VM 16
	44
	45	/* Maximum number of PTEs the hardware can write with one command */
	46	#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
	47
	48	/* number of entries in page table */
36b32a68	49	#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
073440d2 CK	50
	51	/* PTBs (Page Table Blocks) need to be aligned to 32K */
	52	#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
	53
35ba15f0 CK	54	#define AMDGPU_PTE_VALID (1ULL << 0)
	55	#define AMDGPU_PTE_SYSTEM (1ULL << 1)
	56	#define AMDGPU_PTE_SNOOPED (1ULL << 2)
073440d2 CK	57
073440d2 CK	58	/* VI only */
35ba15f0	59	#define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
073440d2	60
35ba15f0 CK	61	#define AMDGPU_PTE_READABLE (1ULL << 5)
35ba15f0 CK	62	#define AMDGPU_PTE_WRITEABLE (1ULL << 6)
073440d2	63
982a1348	64	#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
073440d2	65
d0766e98 ZJ	66	/* TILED for VEGA10, reserved for older ASICs */
d0766e98 ZJ	67	#define AMDGPU_PTE_PRT (1ULL << 51)
284710fa	68
cf2f0a37 AD	69	/* PDE is handled as PTE for VEGA10 */
	70	#define AMDGPU_PDE_PTE (1ULL << 54)
	71
ca02061c AD	72	/* VEGA10 only */
	73	#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
	74	#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
	75
6d16dac8 YZ	76	/* For Raven */
	77	#define AMDGPU_MTYPE_CC 2
	78
	79	#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
	80	\| AMDGPU_PTE_SNOOPED \
	81	\| AMDGPU_PTE_EXECUTABLE \
	82	\| AMDGPU_PTE_READABLE \
	83	\| AMDGPU_PTE_WRITEABLE \
	84	\| AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))
	85
073440d2 CK	86	/* How to programm VM fault handling */
	87	#define AMDGPU_VM_FAULT_STOP_NEVER 0
	88	#define AMDGPU_VM_FAULT_STOP_FIRST 1
	89	#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
	90
eb60ef2b CK	91	/* max number of VMHUB */
	92	#define AMDGPU_MAX_VMHUBS 2
	93	#define AMDGPU_GFXHUB 0
	94	#define AMDGPU_MMHUB 1
	95
	96	/* hardcode that limit for now */
ff4cd389 CK	97	#define AMDGPU_VA_RESERVED_SIZE (8ULL << 20)
ff4cd389 CK	98
bb7939b2 CK	99	/* VA hole for 48bit addresses on Vega10 */
	100	#define AMDGPU_VA_HOLE_START 0x0000800000000000ULL
	101	#define AMDGPU_VA_HOLE_END 0xffff800000000000ULL
	102
	103	/*
	104	* Hardware is programmed as if the hole doesn't exists with start and end
	105	* address values.
	106	*
	107	* This mask is used to remove the upper 16bits of the VA and so come up with
	108	* the linear addr value.
	109	*/
	110	#define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL
	111
c3505770 CZ	112	/* max vmids dedicated for process */
c3505770 CZ	113	#define AMDGPU_VM_MAX_RESERVED_VMID 1
eb60ef2b	114
9a4b7d4c HK	115	#define AMDGPU_VM_CONTEXT_GFX 0
	116	#define AMDGPU_VM_CONTEXT_COMPUTE 1
	117
	118	/* See vm_update_mode */
	119	#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
	120	#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
	121
ec681545 CK	122	/* base structure for tracking BO usage in a VM */
	123	struct amdgpu_vm_bo_base {
	124	/* constant after initialization */
	125	struct amdgpu_vm *vm;
	126	struct amdgpu_bo *bo;
	127
	128	/* protected by bo being reserved */
	129	struct list_head bo_list;
	130
	131	/* protected by spinlock */
	132	struct list_head vm_status;
3d7d4d3a CK	133
	134	/* protected by the BO being reserved */
	135	bool moved;
ec681545	136	};
9a4b7d4c	137
073440d2	138	struct amdgpu_vm_pt {
3f3333f8 CK	139	struct amdgpu_vm_bo_base base;
3f3333f8 CK	140	uint64_t addr;
67003a15 CK	141
67003a15 CK	142	/* array of page tables, one for each directory entry */
3f3333f8 CK	143	struct amdgpu_vm_pt *entries;
3f3333f8 CK	144	unsigned last_entry_used;
073440d2 CK	145	};
073440d2 CK	146
a2f14820 FK	147	#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) \| (addr))
	148	#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
	149	#define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL)
	150
073440d2 CK	151	struct amdgpu_vm {
073440d2 CK	152	/* tree of virtual addresses mapped */
f808c13f	153	struct rb_root_cached va;
073440d2 CK	154
	155	/* protecting invalidated */
	156	spinlock_t status_lock;
	157
3f3333f8 CK	158	/* BOs who needs a validation */
	159	struct list_head evicted;
	160
ea09729c CK	161	/* PT BOs which relocated and their parent need an update */
	162	struct list_head relocated;
	163
073440d2	164	/* BOs moved, but not yet updated in the PT */
27c7b9ae	165	struct list_head moved;
073440d2	166
073440d2 CK	167	/* BO mappings freed, but not yet updated in the PT */
	168	struct list_head freed;
	169
	170	/* contains the page directory */
67003a15	171	struct amdgpu_vm_pt root;
d5884513	172	struct dma_fence *last_update;
073440d2	173
073440d2 CK	174	/* protecting freed */
	175	spinlock_t freed_lock;
	176
	177	/* Scheduler entity for page table updates */
	178	struct amd_sched_entity entity;
	179
02208441	180	/* client id and PASID (TODO: replace client_id with PASID) */
073440d2	181	u64 client_id;
02208441	182	unsigned int pasid;
36bbf3bf CZ	183	/* dedicated to vm */
36bbf3bf CZ	184	struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS];
9a4b7d4c HK	185
	186	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
	187	bool use_cpu_for_update;
51ac7eec YZ	188
	189	/* Flag to indicate ATS support from PTE for GFX9 */
	190	bool pte_support_ats;
a2f14820	191
c98171cc	192	/* Up to 128 pending retry page faults */
a2f14820	193	DECLARE_KFIFO(faults, u64, 128);
c98171cc FK	194
	195	/* Limit non-retry fault storms */
	196	unsigned int fault_credit;
073440d2 CK	197	};
	198
	199	struct amdgpu_vm_id {
	200	struct list_head list;
073440d2	201	struct amdgpu_sync active;
220196b3	202	struct dma_fence *last_flush;
073440d2 CK	203	atomic64_t owner;
	204
	205	uint64_t pd_gpu_addr;
	206	/* last flushed PD/PT update */
220196b3	207	struct dma_fence *flushed_updates;
073440d2 CK	208
	209	uint32_t current_gpu_reset_count;
	210
	211	uint32_t gds_base;
	212	uint32_t gds_size;
	213	uint32_t gws_base;
	214	uint32_t gws_size;
	215	uint32_t oa_base;
	216	uint32_t oa_size;
	217	};
	218
7645670d CK	219	struct amdgpu_vm_id_manager {
	220	struct mutex lock;
	221	unsigned num_ids;
	222	struct list_head ids_lru;
	223	struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
c3505770	224	atomic_t reserved_vmid_num;
7645670d CK	225	};
7645670d CK	226
073440d2 CK	227	struct amdgpu_vm_manager {
073440d2 CK	228	/* Handling of VMIDs */
7645670d	229	struct amdgpu_vm_id_manager id_mgr[AMDGPU_MAX_VMHUBS];
073440d2 CK	230
	231	/* Handling of VM fences */
	232	u64 fence_context;
	233	unsigned seqno[AMDGPU_MAX_RINGS];
	234
22770e5a	235	uint64_t max_pfn;
8437a097	236	uint32_t num_level;
36b32a68	237	uint32_t block_size;
e618d306	238	uint32_t fragment_size;
073440d2 CK	239	/* vram base address for page table entry */
073440d2 CK	240	u64 vram_base_offset;
073440d2 CK	241	/* vm pte handling */
	242	const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
	243	struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
	244	unsigned vm_pte_num_rings;
	245	atomic_t vm_pte_next_ring;
	246	/* client id counter */
	247	atomic64_t client_counter;
284710fa CK	248
	249	/* partial resident texture handling */
	250	spinlock_t prt_lock;
451bc8eb	251	atomic_t num_prt_users;
9a4b7d4c HK	252
	253	/* controls how VM page tables are updated for Graphics and Compute.
	254	* BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
	255	* BIT1[= 0] Compute updated by SDMA [= 1] by CPU
	256	*/
	257	int vm_update_mode;
02208441 FK	258
	259	/* PASID to VM mapping, will be used in interrupt context to
	260	* look up VM of a page fault
	261	*/
	262	struct idr pasid_idr;
	263	spinlock_t pasid_lock;
073440d2 CK	264	};
073440d2 CK	265
02208441 FK	266	int amdgpu_vm_alloc_pasid(unsigned int bits);
02208441 FK	267	void amdgpu_vm_free_pasid(unsigned int pasid);
073440d2 CK	268	void amdgpu_vm_manager_init(struct amdgpu_device *adev);
073440d2 CK	269	void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
9a4b7d4c	270	int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm,
02208441	271	int vm_context, unsigned int pasid);
073440d2	272	void amdgpu_vm_fini(struct amdgpu_device adev, struct amdgpu_vm vm);
c98171cc FK	273	bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
c98171cc FK	274	unsigned int pasid);
073440d2 CK	275	void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
	276	struct list_head *validated,
	277	struct amdgpu_bo_list_entry *entry);
3f3333f8	278	bool amdgpu_vm_ready(struct amdgpu_vm *vm);
073440d2 CK	279	int amdgpu_vm_validate_pt_bos(struct amdgpu_device adev, struct amdgpu_vm vm,
	280	int (callback)(void p, struct amdgpu_bo *bo),
	281	void *param);
663e4577 CK	282	int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
	283	struct amdgpu_vm *vm,
	284	uint64_t saddr, uint64_t size);
073440d2	285	int amdgpu_vm_grab_id(struct amdgpu_vm vm, struct amdgpu_ring ring,
220196b3	286	struct amdgpu_sync sync, struct dma_fence fence,
073440d2	287	struct amdgpu_job *job);
8fdf074f	288	int amdgpu_vm_flush(struct amdgpu_ring ring, struct amdgpu_job job, bool need_pipe_sync);
7645670d CK	289	void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
7645670d CK	290	unsigned vmid);
32601d48	291	void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev);
194d2161 CK	292	int amdgpu_vm_update_directories(struct amdgpu_device *adev,
194d2161 CK	293	struct amdgpu_vm *vm);
073440d2	294	int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
f3467818 NH	295	struct amdgpu_vm *vm,
f3467818 NH	296	struct dma_fence **fence);
73fb16e7	297	int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
4e55eb38	298	struct amdgpu_vm *vm);
073440d2 CK	299	int amdgpu_vm_bo_update(struct amdgpu_device *adev,
	300	struct amdgpu_bo_va *bo_va,
	301	bool clear);
	302	void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
3f3333f8	303	struct amdgpu_bo *bo, bool evicted);
073440d2 CK	304	struct amdgpu_bo_va amdgpu_vm_bo_find(struct amdgpu_vm vm,
	305	struct amdgpu_bo *bo);
	306	struct amdgpu_bo_va amdgpu_vm_bo_add(struct amdgpu_device adev,
	307	struct amdgpu_vm *vm,
	308	struct amdgpu_bo *bo);
	309	int amdgpu_vm_bo_map(struct amdgpu_device *adev,
	310	struct amdgpu_bo_va *bo_va,
	311	uint64_t addr, uint64_t offset,
268c3001	312	uint64_t size, uint64_t flags);
80f95c57 CK	313	int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
	314	struct amdgpu_bo_va *bo_va,
	315	uint64_t addr, uint64_t offset,
	316	uint64_t size, uint64_t flags);
073440d2 CK	317	int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
	318	struct amdgpu_bo_va *bo_va,
	319	uint64_t addr);
dc54d3d1 CK	320	int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
	321	struct amdgpu_vm *vm,
	322	uint64_t saddr, uint64_t size);
aebc5e6f CK	323	struct amdgpu_bo_va_mapping amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm vm,
aebc5e6f CK	324	uint64_t addr);
073440d2 CK	325	void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
073440d2 CK	326	struct amdgpu_bo_va *bo_va);
fdd5faaa	327	void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
f3368128 CK	328	uint32_t fragment_size_default, unsigned max_level,
f3368128 CK	329	unsigned max_bits);
cfbcacf4	330	int amdgpu_vm_ioctl(struct drm_device dev, void data, struct drm_file *filp);
b9bf33d5 CZ	331	bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
b9bf33d5 CZ	332	struct amdgpu_job *job);
e59c0205	333	void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
073440d2 CK	334
073440d2 CK	335	#endif