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073440d2 CK |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Christian König | |
23 | */ | |
24 | #ifndef __AMDGPU_VM_H__ | |
25 | #define __AMDGPU_VM_H__ | |
26 | ||
02208441 | 27 | #include <linux/idr.h> |
1b1f42d8 LS |
28 | #include <linux/kfifo.h> |
29 | #include <linux/rbtree.h> | |
30 | #include <drm/gpu_scheduler.h> | |
073440d2 | 31 | |
073440d2 CK |
32 | #include "amdgpu_sync.h" |
33 | #include "amdgpu_ring.h" | |
34 | ||
35 | struct amdgpu_bo_va; | |
36 | struct amdgpu_job; | |
37 | struct amdgpu_bo_list_entry; | |
38 | ||
39 | /* | |
40 | * GPUVM handling | |
41 | */ | |
42 | ||
43 | /* maximum number of VMIDs */ | |
44 | #define AMDGPU_NUM_VM 16 | |
45 | ||
46 | /* Maximum number of PTEs the hardware can write with one command */ | |
47 | #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF | |
48 | ||
49 | /* number of entries in page table */ | |
36b32a68 | 50 | #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) |
073440d2 CK |
51 | |
52 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ | |
53 | #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 | |
54 | ||
35ba15f0 CK |
55 | #define AMDGPU_PTE_VALID (1ULL << 0) |
56 | #define AMDGPU_PTE_SYSTEM (1ULL << 1) | |
57 | #define AMDGPU_PTE_SNOOPED (1ULL << 2) | |
073440d2 CK |
58 | |
59 | /* VI only */ | |
35ba15f0 | 60 | #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) |
073440d2 | 61 | |
35ba15f0 CK |
62 | #define AMDGPU_PTE_READABLE (1ULL << 5) |
63 | #define AMDGPU_PTE_WRITEABLE (1ULL << 6) | |
073440d2 | 64 | |
982a1348 | 65 | #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) |
073440d2 | 66 | |
d0766e98 ZJ |
67 | /* TILED for VEGA10, reserved for older ASICs */ |
68 | #define AMDGPU_PTE_PRT (1ULL << 51) | |
284710fa | 69 | |
cf2f0a37 AD |
70 | /* PDE is handled as PTE for VEGA10 */ |
71 | #define AMDGPU_PDE_PTE (1ULL << 54) | |
72 | ||
ca02061c AD |
73 | /* VEGA10 only */ |
74 | #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) | |
75 | #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) | |
76 | ||
6d16dac8 YZ |
77 | /* For Raven */ |
78 | #define AMDGPU_MTYPE_CC 2 | |
79 | ||
80 | #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ | |
81 | | AMDGPU_PTE_SNOOPED \ | |
82 | | AMDGPU_PTE_EXECUTABLE \ | |
83 | | AMDGPU_PTE_READABLE \ | |
84 | | AMDGPU_PTE_WRITEABLE \ | |
85 | | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC)) | |
86 | ||
073440d2 CK |
87 | /* How to programm VM fault handling */ |
88 | #define AMDGPU_VM_FAULT_STOP_NEVER 0 | |
89 | #define AMDGPU_VM_FAULT_STOP_FIRST 1 | |
90 | #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 | |
91 | ||
eb60ef2b CK |
92 | /* max number of VMHUB */ |
93 | #define AMDGPU_MAX_VMHUBS 2 | |
94 | #define AMDGPU_GFXHUB 0 | |
95 | #define AMDGPU_MMHUB 1 | |
96 | ||
97 | /* hardcode that limit for now */ | |
ff4cd389 CK |
98 | #define AMDGPU_VA_RESERVED_SIZE (8ULL << 20) |
99 | ||
bb7939b2 CK |
100 | /* VA hole for 48bit addresses on Vega10 */ |
101 | #define AMDGPU_VA_HOLE_START 0x0000800000000000ULL | |
102 | #define AMDGPU_VA_HOLE_END 0xffff800000000000ULL | |
103 | ||
104 | /* | |
105 | * Hardware is programmed as if the hole doesn't exists with start and end | |
106 | * address values. | |
107 | * | |
108 | * This mask is used to remove the upper 16bits of the VA and so come up with | |
109 | * the linear addr value. | |
110 | */ | |
111 | #define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL | |
112 | ||
c3505770 CZ |
113 | /* max vmids dedicated for process */ |
114 | #define AMDGPU_VM_MAX_RESERVED_VMID 1 | |
eb60ef2b | 115 | |
9a4b7d4c HK |
116 | #define AMDGPU_VM_CONTEXT_GFX 0 |
117 | #define AMDGPU_VM_CONTEXT_COMPUTE 1 | |
118 | ||
119 | /* See vm_update_mode */ | |
120 | #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) | |
121 | #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) | |
122 | ||
196f7489 CZ |
123 | /* VMPT level enumerate, and the hiberachy is: |
124 | * PDB2->PDB1->PDB0->PTB | |
125 | */ | |
126 | enum amdgpu_vm_level { | |
127 | AMDGPU_VM_PDB2, | |
128 | AMDGPU_VM_PDB1, | |
129 | AMDGPU_VM_PDB0, | |
130 | AMDGPU_VM_PTB | |
131 | }; | |
132 | ||
ec681545 CK |
133 | /* base structure for tracking BO usage in a VM */ |
134 | struct amdgpu_vm_bo_base { | |
135 | /* constant after initialization */ | |
136 | struct amdgpu_vm *vm; | |
137 | struct amdgpu_bo *bo; | |
138 | ||
139 | /* protected by bo being reserved */ | |
140 | struct list_head bo_list; | |
141 | ||
142 | /* protected by spinlock */ | |
143 | struct list_head vm_status; | |
3d7d4d3a CK |
144 | |
145 | /* protected by the BO being reserved */ | |
146 | bool moved; | |
ec681545 | 147 | }; |
9a4b7d4c | 148 | |
073440d2 | 149 | struct amdgpu_vm_pt { |
3f3333f8 | 150 | struct amdgpu_vm_bo_base base; |
78eb2f0c | 151 | bool huge; |
67003a15 CK |
152 | |
153 | /* array of page tables, one for each directory entry */ | |
3f3333f8 | 154 | struct amdgpu_vm_pt *entries; |
073440d2 CK |
155 | }; |
156 | ||
a2f14820 FK |
157 | #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr)) |
158 | #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48) | |
159 | #define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL) | |
160 | ||
073440d2 CK |
161 | struct amdgpu_vm { |
162 | /* tree of virtual addresses mapped */ | |
f808c13f | 163 | struct rb_root_cached va; |
073440d2 CK |
164 | |
165 | /* protecting invalidated */ | |
166 | spinlock_t status_lock; | |
167 | ||
3f3333f8 CK |
168 | /* BOs who needs a validation */ |
169 | struct list_head evicted; | |
170 | ||
ea09729c CK |
171 | /* PT BOs which relocated and their parent need an update */ |
172 | struct list_head relocated; | |
173 | ||
073440d2 | 174 | /* BOs moved, but not yet updated in the PT */ |
27c7b9ae | 175 | struct list_head moved; |
073440d2 | 176 | |
073440d2 CK |
177 | /* BO mappings freed, but not yet updated in the PT */ |
178 | struct list_head freed; | |
179 | ||
180 | /* contains the page directory */ | |
67003a15 | 181 | struct amdgpu_vm_pt root; |
d5884513 | 182 | struct dma_fence *last_update; |
073440d2 | 183 | |
073440d2 CK |
184 | /* protecting freed */ |
185 | spinlock_t freed_lock; | |
186 | ||
187 | /* Scheduler entity for page table updates */ | |
1b1f42d8 | 188 | struct drm_sched_entity entity; |
073440d2 | 189 | |
02208441 | 190 | /* client id and PASID (TODO: replace client_id with PASID) */ |
073440d2 | 191 | u64 client_id; |
02208441 | 192 | unsigned int pasid; |
36bbf3bf CZ |
193 | /* dedicated to vm */ |
194 | struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS]; | |
9a4b7d4c HK |
195 | |
196 | /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ | |
197 | bool use_cpu_for_update; | |
51ac7eec YZ |
198 | |
199 | /* Flag to indicate ATS support from PTE for GFX9 */ | |
200 | bool pte_support_ats; | |
a2f14820 | 201 | |
c98171cc | 202 | /* Up to 128 pending retry page faults */ |
a2f14820 | 203 | DECLARE_KFIFO(faults, u64, 128); |
c98171cc FK |
204 | |
205 | /* Limit non-retry fault storms */ | |
206 | unsigned int fault_credit; | |
073440d2 CK |
207 | }; |
208 | ||
209 | struct amdgpu_vm_id { | |
210 | struct list_head list; | |
073440d2 | 211 | struct amdgpu_sync active; |
220196b3 | 212 | struct dma_fence *last_flush; |
073440d2 CK |
213 | atomic64_t owner; |
214 | ||
215 | uint64_t pd_gpu_addr; | |
216 | /* last flushed PD/PT update */ | |
220196b3 | 217 | struct dma_fence *flushed_updates; |
073440d2 CK |
218 | |
219 | uint32_t current_gpu_reset_count; | |
220 | ||
221 | uint32_t gds_base; | |
222 | uint32_t gds_size; | |
223 | uint32_t gws_base; | |
224 | uint32_t gws_size; | |
225 | uint32_t oa_base; | |
226 | uint32_t oa_size; | |
227 | }; | |
228 | ||
7645670d CK |
229 | struct amdgpu_vm_id_manager { |
230 | struct mutex lock; | |
231 | unsigned num_ids; | |
232 | struct list_head ids_lru; | |
233 | struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; | |
c3505770 | 234 | atomic_t reserved_vmid_num; |
7645670d CK |
235 | }; |
236 | ||
073440d2 CK |
237 | struct amdgpu_vm_manager { |
238 | /* Handling of VMIDs */ | |
7645670d | 239 | struct amdgpu_vm_id_manager id_mgr[AMDGPU_MAX_VMHUBS]; |
073440d2 CK |
240 | |
241 | /* Handling of VM fences */ | |
242 | u64 fence_context; | |
243 | unsigned seqno[AMDGPU_MAX_RINGS]; | |
244 | ||
22770e5a | 245 | uint64_t max_pfn; |
8437a097 | 246 | uint32_t num_level; |
36b32a68 | 247 | uint32_t block_size; |
e618d306 | 248 | uint32_t fragment_size; |
196f7489 | 249 | enum amdgpu_vm_level root_level; |
073440d2 CK |
250 | /* vram base address for page table entry */ |
251 | u64 vram_base_offset; | |
073440d2 CK |
252 | /* vm pte handling */ |
253 | const struct amdgpu_vm_pte_funcs *vm_pte_funcs; | |
254 | struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; | |
255 | unsigned vm_pte_num_rings; | |
256 | atomic_t vm_pte_next_ring; | |
257 | /* client id counter */ | |
258 | atomic64_t client_counter; | |
284710fa CK |
259 | |
260 | /* partial resident texture handling */ | |
261 | spinlock_t prt_lock; | |
451bc8eb | 262 | atomic_t num_prt_users; |
9a4b7d4c HK |
263 | |
264 | /* controls how VM page tables are updated for Graphics and Compute. | |
265 | * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU | |
266 | * BIT1[= 0] Compute updated by SDMA [= 1] by CPU | |
267 | */ | |
268 | int vm_update_mode; | |
02208441 FK |
269 | |
270 | /* PASID to VM mapping, will be used in interrupt context to | |
271 | * look up VM of a page fault | |
272 | */ | |
273 | struct idr pasid_idr; | |
274 | spinlock_t pasid_lock; | |
073440d2 CK |
275 | }; |
276 | ||
02208441 FK |
277 | int amdgpu_vm_alloc_pasid(unsigned int bits); |
278 | void amdgpu_vm_free_pasid(unsigned int pasid); | |
073440d2 CK |
279 | void amdgpu_vm_manager_init(struct amdgpu_device *adev); |
280 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev); | |
9a4b7d4c | 281 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 282 | int vm_context, unsigned int pasid); |
073440d2 | 283 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
c98171cc FK |
284 | bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, |
285 | unsigned int pasid); | |
073440d2 CK |
286 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
287 | struct list_head *validated, | |
288 | struct amdgpu_bo_list_entry *entry); | |
3f3333f8 | 289 | bool amdgpu_vm_ready(struct amdgpu_vm *vm); |
073440d2 CK |
290 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
291 | int (*callback)(void *p, struct amdgpu_bo *bo), | |
292 | void *param); | |
663e4577 CK |
293 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, |
294 | struct amdgpu_vm *vm, | |
295 | uint64_t saddr, uint64_t size); | |
073440d2 | 296 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
220196b3 | 297 | struct amdgpu_sync *sync, struct dma_fence *fence, |
073440d2 | 298 | struct amdgpu_job *job); |
8fdf074f | 299 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); |
7645670d CK |
300 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
301 | unsigned vmid); | |
32601d48 | 302 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev); |
194d2161 CK |
303 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, |
304 | struct amdgpu_vm *vm); | |
073440d2 | 305 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, |
f3467818 NH |
306 | struct amdgpu_vm *vm, |
307 | struct dma_fence **fence); | |
73fb16e7 | 308 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 309 | struct amdgpu_vm *vm); |
073440d2 CK |
310 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, |
311 | struct amdgpu_bo_va *bo_va, | |
312 | bool clear); | |
313 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 314 | struct amdgpu_bo *bo, bool evicted); |
073440d2 CK |
315 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, |
316 | struct amdgpu_bo *bo); | |
317 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
318 | struct amdgpu_vm *vm, | |
319 | struct amdgpu_bo *bo); | |
320 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
321 | struct amdgpu_bo_va *bo_va, | |
322 | uint64_t addr, uint64_t offset, | |
268c3001 | 323 | uint64_t size, uint64_t flags); |
80f95c57 CK |
324 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, |
325 | struct amdgpu_bo_va *bo_va, | |
326 | uint64_t addr, uint64_t offset, | |
327 | uint64_t size, uint64_t flags); | |
073440d2 CK |
328 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, |
329 | struct amdgpu_bo_va *bo_va, | |
330 | uint64_t addr); | |
dc54d3d1 CK |
331 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, |
332 | struct amdgpu_vm *vm, | |
333 | uint64_t saddr, uint64_t size); | |
aebc5e6f CK |
334 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, |
335 | uint64_t addr); | |
073440d2 CK |
336 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, |
337 | struct amdgpu_bo_va *bo_va); | |
fdd5faaa | 338 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, |
f3368128 CK |
339 | uint32_t fragment_size_default, unsigned max_level, |
340 | unsigned max_bits); | |
cfbcacf4 | 341 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
b9bf33d5 CZ |
342 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
343 | struct amdgpu_job *job); | |
e59c0205 | 344 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); |
073440d2 CK |
345 | |
346 | #endif |