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073440d2 CK |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Christian König | |
23 | */ | |
24 | #ifndef __AMDGPU_VM_H__ | |
25 | #define __AMDGPU_VM_H__ | |
26 | ||
27 | #include <linux/rbtree.h> | |
28 | ||
29 | #include "gpu_scheduler.h" | |
30 | #include "amdgpu_sync.h" | |
31 | #include "amdgpu_ring.h" | |
32 | ||
33 | struct amdgpu_bo_va; | |
34 | struct amdgpu_job; | |
35 | struct amdgpu_bo_list_entry; | |
36 | ||
37 | /* | |
38 | * GPUVM handling | |
39 | */ | |
40 | ||
41 | /* maximum number of VMIDs */ | |
42 | #define AMDGPU_NUM_VM 16 | |
43 | ||
44 | /* Maximum number of PTEs the hardware can write with one command */ | |
45 | #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF | |
46 | ||
47 | /* number of entries in page table */ | |
36b32a68 | 48 | #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) |
073440d2 CK |
49 | |
50 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ | |
51 | #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 | |
52 | ||
53 | /* LOG2 number of continuous pages for the fragment field */ | |
6be7adb3 CK |
54 | #define AMDGPU_LOG2_PAGES_PER_FRAG(adev) \ |
55 | ((adev)->asic_type < CHIP_VEGA10 ? 4 : \ | |
56 | (adev)->vm_manager.block_size) | |
073440d2 | 57 | |
35ba15f0 CK |
58 | #define AMDGPU_PTE_VALID (1ULL << 0) |
59 | #define AMDGPU_PTE_SYSTEM (1ULL << 1) | |
60 | #define AMDGPU_PTE_SNOOPED (1ULL << 2) | |
073440d2 CK |
61 | |
62 | /* VI only */ | |
35ba15f0 | 63 | #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) |
073440d2 | 64 | |
35ba15f0 CK |
65 | #define AMDGPU_PTE_READABLE (1ULL << 5) |
66 | #define AMDGPU_PTE_WRITEABLE (1ULL << 6) | |
073440d2 | 67 | |
982a1348 | 68 | #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) |
073440d2 | 69 | |
d0766e98 ZJ |
70 | /* TILED for VEGA10, reserved for older ASICs */ |
71 | #define AMDGPU_PTE_PRT (1ULL << 51) | |
284710fa | 72 | |
cf2f0a37 AD |
73 | /* PDE is handled as PTE for VEGA10 */ |
74 | #define AMDGPU_PDE_PTE (1ULL << 54) | |
75 | ||
ca02061c AD |
76 | /* VEGA10 only */ |
77 | #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) | |
78 | #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) | |
79 | ||
073440d2 CK |
80 | /* How to programm VM fault handling */ |
81 | #define AMDGPU_VM_FAULT_STOP_NEVER 0 | |
82 | #define AMDGPU_VM_FAULT_STOP_FIRST 1 | |
83 | #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 | |
84 | ||
eb60ef2b CK |
85 | /* max number of VMHUB */ |
86 | #define AMDGPU_MAX_VMHUBS 2 | |
87 | #define AMDGPU_GFXHUB 0 | |
88 | #define AMDGPU_MMHUB 1 | |
89 | ||
90 | /* hardcode that limit for now */ | |
91 | #define AMDGPU_VA_RESERVED_SIZE (8 << 20) | |
c3505770 CZ |
92 | /* max vmids dedicated for process */ |
93 | #define AMDGPU_VM_MAX_RESERVED_VMID 1 | |
eb60ef2b | 94 | |
9a4b7d4c HK |
95 | #define AMDGPU_VM_CONTEXT_GFX 0 |
96 | #define AMDGPU_VM_CONTEXT_COMPUTE 1 | |
97 | ||
98 | /* See vm_update_mode */ | |
99 | #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) | |
100 | #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) | |
101 | ||
102 | ||
073440d2 CK |
103 | struct amdgpu_vm_pt { |
104 | struct amdgpu_bo *bo; | |
105 | uint64_t addr; | |
67003a15 CK |
106 | |
107 | /* array of page tables, one for each directory entry */ | |
108 | struct amdgpu_vm_pt *entries; | |
109 | unsigned last_entry_used; | |
073440d2 CK |
110 | }; |
111 | ||
112 | struct amdgpu_vm { | |
113 | /* tree of virtual addresses mapped */ | |
114 | struct rb_root va; | |
115 | ||
116 | /* protecting invalidated */ | |
117 | spinlock_t status_lock; | |
118 | ||
119 | /* BOs moved, but not yet updated in the PT */ | |
120 | struct list_head invalidated; | |
121 | ||
122 | /* BOs cleared in the PT because of a move */ | |
123 | struct list_head cleared; | |
124 | ||
125 | /* BO mappings freed, but not yet updated in the PT */ | |
126 | struct list_head freed; | |
127 | ||
128 | /* contains the page directory */ | |
67003a15 | 129 | struct amdgpu_vm_pt root; |
a24960f3 | 130 | struct dma_fence *last_dir_update; |
073440d2 CK |
131 | uint64_t last_eviction_counter; |
132 | ||
073440d2 CK |
133 | /* protecting freed */ |
134 | spinlock_t freed_lock; | |
135 | ||
136 | /* Scheduler entity for page table updates */ | |
137 | struct amd_sched_entity entity; | |
138 | ||
139 | /* client id */ | |
140 | u64 client_id; | |
36bbf3bf CZ |
141 | /* dedicated to vm */ |
142 | struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS]; | |
9a4b7d4c HK |
143 | |
144 | /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ | |
145 | bool use_cpu_for_update; | |
51ac7eec YZ |
146 | |
147 | /* Flag to indicate ATS support from PTE for GFX9 */ | |
148 | bool pte_support_ats; | |
073440d2 CK |
149 | }; |
150 | ||
151 | struct amdgpu_vm_id { | |
152 | struct list_head list; | |
073440d2 | 153 | struct amdgpu_sync active; |
220196b3 | 154 | struct dma_fence *last_flush; |
073440d2 CK |
155 | atomic64_t owner; |
156 | ||
157 | uint64_t pd_gpu_addr; | |
158 | /* last flushed PD/PT update */ | |
220196b3 | 159 | struct dma_fence *flushed_updates; |
073440d2 CK |
160 | |
161 | uint32_t current_gpu_reset_count; | |
162 | ||
163 | uint32_t gds_base; | |
164 | uint32_t gds_size; | |
165 | uint32_t gws_base; | |
166 | uint32_t gws_size; | |
167 | uint32_t oa_base; | |
168 | uint32_t oa_size; | |
169 | }; | |
170 | ||
7645670d CK |
171 | struct amdgpu_vm_id_manager { |
172 | struct mutex lock; | |
173 | unsigned num_ids; | |
174 | struct list_head ids_lru; | |
175 | struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; | |
c3505770 | 176 | atomic_t reserved_vmid_num; |
7645670d CK |
177 | }; |
178 | ||
073440d2 CK |
179 | struct amdgpu_vm_manager { |
180 | /* Handling of VMIDs */ | |
7645670d | 181 | struct amdgpu_vm_id_manager id_mgr[AMDGPU_MAX_VMHUBS]; |
073440d2 CK |
182 | |
183 | /* Handling of VM fences */ | |
184 | u64 fence_context; | |
185 | unsigned seqno[AMDGPU_MAX_RINGS]; | |
186 | ||
22770e5a | 187 | uint64_t max_pfn; |
8437a097 | 188 | uint32_t num_level; |
36b32a68 ZJ |
189 | uint64_t vm_size; |
190 | uint32_t block_size; | |
073440d2 CK |
191 | /* vram base address for page table entry */ |
192 | u64 vram_base_offset; | |
073440d2 CK |
193 | /* vm pte handling */ |
194 | const struct amdgpu_vm_pte_funcs *vm_pte_funcs; | |
195 | struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; | |
196 | unsigned vm_pte_num_rings; | |
197 | atomic_t vm_pte_next_ring; | |
198 | /* client id counter */ | |
199 | atomic64_t client_counter; | |
284710fa CK |
200 | |
201 | /* partial resident texture handling */ | |
202 | spinlock_t prt_lock; | |
451bc8eb | 203 | atomic_t num_prt_users; |
9a4b7d4c HK |
204 | |
205 | /* controls how VM page tables are updated for Graphics and Compute. | |
206 | * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU | |
207 | * BIT1[= 0] Compute updated by SDMA [= 1] by CPU | |
208 | */ | |
209 | int vm_update_mode; | |
073440d2 CK |
210 | }; |
211 | ||
212 | void amdgpu_vm_manager_init(struct amdgpu_device *adev); | |
213 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev); | |
9a4b7d4c HK |
214 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
215 | int vm_context); | |
073440d2 CK |
216 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
217 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, | |
218 | struct list_head *validated, | |
219 | struct amdgpu_bo_list_entry *entry); | |
220 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
221 | int (*callback)(void *p, struct amdgpu_bo *bo), | |
222 | void *param); | |
663e4577 CK |
223 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, |
224 | struct amdgpu_vm *vm, | |
225 | uint64_t saddr, uint64_t size); | |
073440d2 | 226 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
220196b3 | 227 | struct amdgpu_sync *sync, struct dma_fence *fence, |
073440d2 | 228 | struct amdgpu_job *job); |
8fdf074f | 229 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); |
7645670d CK |
230 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
231 | unsigned vmid); | |
32601d48 | 232 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev); |
194d2161 CK |
233 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, |
234 | struct amdgpu_vm *vm); | |
073440d2 | 235 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, |
f3467818 NH |
236 | struct amdgpu_vm *vm, |
237 | struct dma_fence **fence); | |
073440d2 CK |
238 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
239 | struct amdgpu_sync *sync); | |
240 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
241 | struct amdgpu_bo_va *bo_va, | |
242 | bool clear); | |
243 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
244 | struct amdgpu_bo *bo); | |
245 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
246 | struct amdgpu_bo *bo); | |
247 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
248 | struct amdgpu_vm *vm, | |
249 | struct amdgpu_bo *bo); | |
250 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
251 | struct amdgpu_bo_va *bo_va, | |
252 | uint64_t addr, uint64_t offset, | |
268c3001 | 253 | uint64_t size, uint64_t flags); |
80f95c57 CK |
254 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, |
255 | struct amdgpu_bo_va *bo_va, | |
256 | uint64_t addr, uint64_t offset, | |
257 | uint64_t size, uint64_t flags); | |
073440d2 CK |
258 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, |
259 | struct amdgpu_bo_va *bo_va, | |
260 | uint64_t addr); | |
dc54d3d1 CK |
261 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, |
262 | struct amdgpu_vm *vm, | |
263 | uint64_t saddr, uint64_t size); | |
073440d2 CK |
264 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, |
265 | struct amdgpu_bo_va *bo_va); | |
bab4fee7 | 266 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size); |
cfbcacf4 | 267 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
b9bf33d5 CZ |
268 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
269 | struct amdgpu_job *job); | |
e59c0205 | 270 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); |
073440d2 CK |
271 | |
272 | #endif |