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073440d2 CK |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Christian König | |
23 | */ | |
24 | #ifndef __AMDGPU_VM_H__ | |
25 | #define __AMDGPU_VM_H__ | |
26 | ||
02208441 | 27 | #include <linux/idr.h> |
1b1f42d8 LS |
28 | #include <linux/kfifo.h> |
29 | #include <linux/rbtree.h> | |
30 | #include <drm/gpu_scheduler.h> | |
61b100e9 | 31 | #include <drm/drm_file.h> |
f921661b | 32 | #include <drm/ttm/ttm_bo_driver.h> |
073440d2 | 33 | |
073440d2 CK |
34 | #include "amdgpu_sync.h" |
35 | #include "amdgpu_ring.h" | |
620f774f | 36 | #include "amdgpu_ids.h" |
073440d2 CK |
37 | |
38 | struct amdgpu_bo_va; | |
39 | struct amdgpu_job; | |
40 | struct amdgpu_bo_list_entry; | |
41 | ||
42 | /* | |
43 | * GPUVM handling | |
44 | */ | |
45 | ||
073440d2 CK |
46 | /* Maximum number of PTEs the hardware can write with one command */ |
47 | #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF | |
48 | ||
49 | /* number of entries in page table */ | |
36b32a68 | 50 | #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) |
073440d2 | 51 | |
35ba15f0 CK |
52 | #define AMDGPU_PTE_VALID (1ULL << 0) |
53 | #define AMDGPU_PTE_SYSTEM (1ULL << 1) | |
54 | #define AMDGPU_PTE_SNOOPED (1ULL << 2) | |
073440d2 CK |
55 | |
56 | /* VI only */ | |
35ba15f0 | 57 | #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) |
073440d2 | 58 | |
35ba15f0 CK |
59 | #define AMDGPU_PTE_READABLE (1ULL << 5) |
60 | #define AMDGPU_PTE_WRITEABLE (1ULL << 6) | |
073440d2 | 61 | |
982a1348 | 62 | #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) |
073440d2 | 63 | |
d0766e98 ZJ |
64 | /* TILED for VEGA10, reserved for older ASICs */ |
65 | #define AMDGPU_PTE_PRT (1ULL << 51) | |
284710fa | 66 | |
cf2f0a37 AD |
67 | /* PDE is handled as PTE for VEGA10 */ |
68 | #define AMDGPU_PDE_PTE (1ULL << 54) | |
69 | ||
6a42fd6f CK |
70 | /* PTE is handled as PDE for VEGA10 (Translate Further) */ |
71 | #define AMDGPU_PTE_TF (1ULL << 56) | |
72 | ||
73 | /* PDE Block Fragment Size for VEGA10 */ | |
74 | #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) | |
75 | ||
959a2091 YZ |
76 | |
77 | /* For GFX9 */ | |
ca02061c AD |
78 | #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) |
79 | #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) | |
80 | ||
959a2091 | 81 | #define AMDGPU_MTYPE_NC 0 |
6d16dac8 YZ |
82 | #define AMDGPU_MTYPE_CC 2 |
83 | ||
84 | #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ | |
85 | | AMDGPU_PTE_SNOOPED \ | |
86 | | AMDGPU_PTE_EXECUTABLE \ | |
87 | | AMDGPU_PTE_READABLE \ | |
88 | | AMDGPU_PTE_WRITEABLE \ | |
89 | | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC)) | |
90 | ||
073440d2 CK |
91 | /* How to programm VM fault handling */ |
92 | #define AMDGPU_VM_FAULT_STOP_NEVER 0 | |
93 | #define AMDGPU_VM_FAULT_STOP_FIRST 1 | |
94 | #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 | |
95 | ||
eb60ef2b CK |
96 | /* max number of VMHUB */ |
97 | #define AMDGPU_MAX_VMHUBS 2 | |
98 | #define AMDGPU_GFXHUB 0 | |
99 | #define AMDGPU_MMHUB 1 | |
100 | ||
101 | /* hardcode that limit for now */ | |
18d09e63 | 102 | #define AMDGPU_VA_RESERVED_SIZE (1ULL << 20) |
ff4cd389 | 103 | |
bb7939b2 CK |
104 | /* VA hole for 48bit addresses on Vega10 */ |
105 | #define AMDGPU_VA_HOLE_START 0x0000800000000000ULL | |
106 | #define AMDGPU_VA_HOLE_END 0xffff800000000000ULL | |
107 | ||
108 | /* | |
109 | * Hardware is programmed as if the hole doesn't exists with start and end | |
110 | * address values. | |
111 | * | |
112 | * This mask is used to remove the upper 16bits of the VA and so come up with | |
113 | * the linear addr value. | |
114 | */ | |
115 | #define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL | |
116 | ||
c3505770 CZ |
117 | /* max vmids dedicated for process */ |
118 | #define AMDGPU_VM_MAX_RESERVED_VMID 1 | |
eb60ef2b | 119 | |
9a4b7d4c HK |
120 | #define AMDGPU_VM_CONTEXT_GFX 0 |
121 | #define AMDGPU_VM_CONTEXT_COMPUTE 1 | |
122 | ||
123 | /* See vm_update_mode */ | |
124 | #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) | |
125 | #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) | |
126 | ||
196f7489 CZ |
127 | /* VMPT level enumerate, and the hiberachy is: |
128 | * PDB2->PDB1->PDB0->PTB | |
129 | */ | |
130 | enum amdgpu_vm_level { | |
131 | AMDGPU_VM_PDB2, | |
132 | AMDGPU_VM_PDB1, | |
133 | AMDGPU_VM_PDB0, | |
134 | AMDGPU_VM_PTB | |
135 | }; | |
136 | ||
ec681545 CK |
137 | /* base structure for tracking BO usage in a VM */ |
138 | struct amdgpu_vm_bo_base { | |
139 | /* constant after initialization */ | |
140 | struct amdgpu_vm *vm; | |
141 | struct amdgpu_bo *bo; | |
142 | ||
143 | /* protected by bo being reserved */ | |
144 | struct list_head bo_list; | |
145 | ||
146 | /* protected by spinlock */ | |
147 | struct list_head vm_status; | |
3d7d4d3a CK |
148 | |
149 | /* protected by the BO being reserved */ | |
150 | bool moved; | |
ec681545 | 151 | }; |
9a4b7d4c | 152 | |
073440d2 | 153 | struct amdgpu_vm_pt { |
3f3333f8 | 154 | struct amdgpu_vm_bo_base base; |
78eb2f0c | 155 | bool huge; |
67003a15 CK |
156 | |
157 | /* array of page tables, one for each directory entry */ | |
3f3333f8 | 158 | struct amdgpu_vm_pt *entries; |
073440d2 CK |
159 | }; |
160 | ||
4473e1db HR |
161 | /* provided by hw blocks that can write ptes, e.g., sdma */ |
162 | struct amdgpu_vm_pte_funcs { | |
163 | /* number of dw to reserve per operation */ | |
164 | unsigned copy_pte_num_dw; | |
165 | ||
166 | /* copy pte entries from GART */ | |
167 | void (*copy_pte)(struct amdgpu_ib *ib, | |
168 | uint64_t pe, uint64_t src, | |
169 | unsigned count); | |
170 | ||
171 | /* write pte one entry at a time with addr mapping */ | |
172 | void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, | |
173 | uint64_t value, unsigned count, | |
174 | uint32_t incr); | |
175 | /* for linear pte/pde updates without addr mapping */ | |
176 | void (*set_pte_pde)(struct amdgpu_ib *ib, | |
177 | uint64_t pe, | |
178 | uint64_t addr, unsigned count, | |
179 | uint32_t incr, uint64_t flags); | |
180 | }; | |
181 | ||
a2f14820 FK |
182 | #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr)) |
183 | #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48) | |
184 | #define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL) | |
185 | ||
2aa37bf5 AG |
186 | |
187 | struct amdgpu_task_info { | |
188 | char process_name[TASK_COMM_LEN]; | |
189 | char task_name[TASK_COMM_LEN]; | |
190 | pid_t pid; | |
191 | pid_t tgid; | |
192 | }; | |
193 | ||
073440d2 CK |
194 | struct amdgpu_vm { |
195 | /* tree of virtual addresses mapped */ | |
f808c13f | 196 | struct rb_root_cached va; |
073440d2 | 197 | |
3f3333f8 CK |
198 | /* BOs who needs a validation */ |
199 | struct list_head evicted; | |
200 | ||
ea09729c CK |
201 | /* PT BOs which relocated and their parent need an update */ |
202 | struct list_head relocated; | |
203 | ||
073440d2 | 204 | /* BOs moved, but not yet updated in the PT */ |
27c7b9ae | 205 | struct list_head moved; |
af4c0f65 | 206 | spinlock_t moved_lock; |
073440d2 | 207 | |
806f043f CK |
208 | /* All BOs of this VM not currently in the state machine */ |
209 | struct list_head idle; | |
210 | ||
073440d2 CK |
211 | /* BO mappings freed, but not yet updated in the PT */ |
212 | struct list_head freed; | |
213 | ||
214 | /* contains the page directory */ | |
67003a15 | 215 | struct amdgpu_vm_pt root; |
d5884513 | 216 | struct dma_fence *last_update; |
073440d2 | 217 | |
073440d2 | 218 | /* Scheduler entity for page table updates */ |
1b1f42d8 | 219 | struct drm_sched_entity entity; |
073440d2 | 220 | |
02208441 | 221 | unsigned int pasid; |
36bbf3bf | 222 | /* dedicated to vm */ |
620f774f | 223 | struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; |
9a4b7d4c HK |
224 | |
225 | /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ | |
226 | bool use_cpu_for_update; | |
51ac7eec YZ |
227 | |
228 | /* Flag to indicate ATS support from PTE for GFX9 */ | |
229 | bool pte_support_ats; | |
a2f14820 | 230 | |
c98171cc | 231 | /* Up to 128 pending retry page faults */ |
a2f14820 | 232 | DECLARE_KFIFO(faults, u64, 128); |
c98171cc FK |
233 | |
234 | /* Limit non-retry fault storms */ | |
235 | unsigned int fault_credit; | |
5b21d3e5 FK |
236 | |
237 | /* Points to the KFD process VM info */ | |
238 | struct amdkfd_process_info *process_info; | |
239 | ||
240 | /* List node in amdkfd_process_info.vm_list_head */ | |
241 | struct list_head vm_list_node; | |
242 | ||
243 | /* Valid while the PD is reserved or fenced */ | |
244 | uint64_t pd_phys_addr; | |
2aa37bf5 AG |
245 | |
246 | /* Some basic info about the task */ | |
247 | struct amdgpu_task_info task_info; | |
f921661b HR |
248 | |
249 | /* Store positions of group of BOs */ | |
250 | struct ttm_lru_bulk_move lru_bulk_move; | |
251 | /* mark whether can do the bulk move */ | |
252 | bool bulk_moveable; | |
073440d2 CK |
253 | }; |
254 | ||
073440d2 CK |
255 | struct amdgpu_vm_manager { |
256 | /* Handling of VMIDs */ | |
620f774f | 257 | struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; |
073440d2 CK |
258 | |
259 | /* Handling of VM fences */ | |
260 | u64 fence_context; | |
261 | unsigned seqno[AMDGPU_MAX_RINGS]; | |
262 | ||
22770e5a | 263 | uint64_t max_pfn; |
8437a097 | 264 | uint32_t num_level; |
36b32a68 | 265 | uint32_t block_size; |
e618d306 | 266 | uint32_t fragment_size; |
196f7489 | 267 | enum amdgpu_vm_level root_level; |
073440d2 CK |
268 | /* vram base address for page table entry */ |
269 | u64 vram_base_offset; | |
073440d2 | 270 | /* vm pte handling */ |
3798e9a6 CK |
271 | const struct amdgpu_vm_pte_funcs *vm_pte_funcs; |
272 | struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS]; | |
273 | unsigned vm_pte_num_rqs; | |
284710fa CK |
274 | |
275 | /* partial resident texture handling */ | |
276 | spinlock_t prt_lock; | |
451bc8eb | 277 | atomic_t num_prt_users; |
9a4b7d4c HK |
278 | |
279 | /* controls how VM page tables are updated for Graphics and Compute. | |
280 | * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU | |
281 | * BIT1[= 0] Compute updated by SDMA [= 1] by CPU | |
282 | */ | |
283 | int vm_update_mode; | |
02208441 FK |
284 | |
285 | /* PASID to VM mapping, will be used in interrupt context to | |
286 | * look up VM of a page fault | |
287 | */ | |
288 | struct idr pasid_idr; | |
289 | spinlock_t pasid_lock; | |
073440d2 CK |
290 | }; |
291 | ||
4473e1db HR |
292 | #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) |
293 | #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) | |
294 | #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) | |
295 | ||
073440d2 CK |
296 | void amdgpu_vm_manager_init(struct amdgpu_device *adev); |
297 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev); | |
9a4b7d4c | 298 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 299 | int vm_context, unsigned int pasid); |
1685b01a | 300 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid); |
073440d2 | 301 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
c98171cc FK |
302 | bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, |
303 | unsigned int pasid); | |
073440d2 CK |
304 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
305 | struct list_head *validated, | |
306 | struct amdgpu_bo_list_entry *entry); | |
3f3333f8 | 307 | bool amdgpu_vm_ready(struct amdgpu_vm *vm); |
073440d2 CK |
308 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
309 | int (*callback)(void *p, struct amdgpu_bo *bo), | |
310 | void *param); | |
663e4577 CK |
311 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, |
312 | struct amdgpu_vm *vm, | |
313 | uint64_t saddr, uint64_t size); | |
8fdf074f | 314 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); |
194d2161 CK |
315 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, |
316 | struct amdgpu_vm *vm); | |
073440d2 | 317 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, |
f3467818 NH |
318 | struct amdgpu_vm *vm, |
319 | struct dma_fence **fence); | |
73fb16e7 | 320 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 321 | struct amdgpu_vm *vm); |
073440d2 CK |
322 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, |
323 | struct amdgpu_bo_va *bo_va, | |
324 | bool clear); | |
325 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 326 | struct amdgpu_bo *bo, bool evicted); |
073440d2 CK |
327 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, |
328 | struct amdgpu_bo *bo); | |
329 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
330 | struct amdgpu_vm *vm, | |
331 | struct amdgpu_bo *bo); | |
332 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
333 | struct amdgpu_bo_va *bo_va, | |
334 | uint64_t addr, uint64_t offset, | |
268c3001 | 335 | uint64_t size, uint64_t flags); |
80f95c57 CK |
336 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, |
337 | struct amdgpu_bo_va *bo_va, | |
338 | uint64_t addr, uint64_t offset, | |
339 | uint64_t size, uint64_t flags); | |
073440d2 CK |
340 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, |
341 | struct amdgpu_bo_va *bo_va, | |
342 | uint64_t addr); | |
dc54d3d1 CK |
343 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, |
344 | struct amdgpu_vm *vm, | |
345 | uint64_t saddr, uint64_t size); | |
aebc5e6f CK |
346 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, |
347 | uint64_t addr); | |
8ab19ea6 | 348 | void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); |
073440d2 CK |
349 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, |
350 | struct amdgpu_bo_va *bo_va); | |
43370c4c | 351 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, |
f3368128 CK |
352 | uint32_t fragment_size_default, unsigned max_level, |
353 | unsigned max_bits); | |
cfbcacf4 | 354 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
b9bf33d5 CZ |
355 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
356 | struct amdgpu_job *job); | |
e59c0205 | 357 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); |
073440d2 | 358 | |
2aa37bf5 | 359 | void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, |
f921661b | 360 | struct amdgpu_task_info *task_info); |
2aa37bf5 AG |
361 | |
362 | void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); | |
363 | ||
f921661b HR |
364 | void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, |
365 | struct amdgpu_vm *vm); | |
366 | ||
073440d2 | 367 | #endif |