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drm/amdgpu: cleanup skipping IB test on KIQ
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vcn.c
CommitLineData
95d0906f
LL		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27#include <linux/firmware.h>
28#include <linux/module.h>
29#include <drm/drmP.h>
30#include <drm/drm.h>
31
32#include "amdgpu.h"
33#include "amdgpu_pm.h"
34#include "amdgpu_vcn.h"
35#include "soc15d.h"
36#include "soc15_common.h"
37
b1ebd7c0 38#include "vcn/vcn_1_0_offset.h"
bd5d5180 39#include "vcn/vcn_1_0_sh_mask.h"
95d0906f
LL		 40
41/* 1 second timeout */
42#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
43
44/* Firmware Names */
45#define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
86771d9a 46#define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
8b47cc9b 47#define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
95d0906f
LL		 48
49MODULE_FIRMWARE(FIRMWARE_RAVEN);
86771d9a 50MODULE_FIRMWARE(FIRMWARE_PICASSO);
8b47cc9b 51MODULE_FIRMWARE(FIRMWARE_RAVEN2);
95d0906f
LL		 52
53static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
54
55int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
56{
95d0906f
LL		 57 unsigned long bo_size;
58 const char *fw_name;
59 const struct common_firmware_header *hdr;
62d5b8e3 60 unsigned char fw_check;
95d0906f
LL		 61 int r;
62
63 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
64
65 switch (adev->asic_type) {
66 case CHIP_RAVEN:
741deade 67 if (adev->rev_id >= 8)
8b47cc9b 68 fw_name = FIRMWARE_RAVEN2;
741deade
AD		 69 else if (adev->pdev->device == 0x15d8)
70 fw_name = FIRMWARE_PICASSO;
8b47cc9b
FX		 71 else
72 fw_name = FIRMWARE_RAVEN;
95d0906f
LL		 73 break;
74 default:
75 return -EINVAL;
76 }
77
78 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
79 if (r) {
80 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
81 fw_name);
82 return r;
83 }
84
85 r = amdgpu_ucode_validate(adev->vcn.fw);
86 if (r) {
87 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
88 fw_name);
89 release_firmware(adev->vcn.fw);
90 adev->vcn.fw = NULL;
91 return r;
92 }
93
94 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
a0b2ac29 95 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
95d0906f 96
62d5b8e3
JZ		 97 /* Bit 20-23, it is encode major and non-zero for new naming convention.
98 * This field is part of version minor and DRM_DISABLED_FLAG in old naming
99 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
100 * is zero in old naming convention, this field is always zero so far.
101 * These four bits are used to tell which naming convention is present.
102 */
103 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
104 if (fw_check) {
105 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
106
107 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
108 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
109 enc_major = fw_check;
110 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
111 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
112 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
113 enc_major, enc_minor, dec_ver, vep, fw_rev);
114 } else {
115 unsigned int version_major, version_minor, family_id;
116
117 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
118 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
119 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
120 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
121 version_major, version_minor, family_id);
122 }
95d0906f 123
825da4d9 124 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
4d77c0f6
LG		 125 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
126 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
95d0906f
LL		 127 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
128 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
129 &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
130 if (r) {
131 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
132 return r;
133 }
134
95d0906f
LL		 135 return 0;
136}
137
138int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
139{
101c6fee
LL		 140 int i;
141
c9533d1b 142 kvfree(adev->vcn.saved_bo);
95d0906f 143
95d0906f
LL		 144 amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
145 &adev->vcn.gpu_addr,
146 (void **)&adev->vcn.cpu_addr);
147
148 amdgpu_ring_fini(&adev->vcn.ring_dec);
149
101c6fee
LL		 150 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
151 amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
152
0c5e4b3e
BZ		 153 amdgpu_ring_fini(&adev->vcn.ring_jpeg);
154
95d0906f
LL		 155 release_firmware(adev->vcn.fw);
156
157 return 0;
158}
159
160int amdgpu_vcn_suspend(struct amdgpu_device *adev)
161{
162 unsigned size;
163 void *ptr;
164
61ea6f58
RZ		 165 cancel_delayed_work_sync(&adev->vcn.idle_work);
166
95d0906f
LL		 167 if (adev->vcn.vcpu_bo == NULL)
168 return 0;
169
95d0906f
LL		 170 size = amdgpu_bo_size(adev->vcn.vcpu_bo);
171 ptr = adev->vcn.cpu_addr;
172
c9533d1b 173 adev->vcn.saved_bo = kvmalloc(size, GFP_KERNEL);
95d0906f
LL		 174 if (!adev->vcn.saved_bo)
175 return -ENOMEM;
176
177 memcpy_fromio(adev->vcn.saved_bo, ptr, size);
178
179 return 0;
180}
181
182int amdgpu_vcn_resume(struct amdgpu_device *adev)
183{
184 unsigned size;
185 void *ptr;
186
187 if (adev->vcn.vcpu_bo == NULL)
188 return -EINVAL;
189
190 size = amdgpu_bo_size(adev->vcn.vcpu_bo);
191 ptr = adev->vcn.cpu_addr;
192
193 if (adev->vcn.saved_bo != NULL) {
194 memcpy_toio(ptr, adev->vcn.saved_bo, size);
c9533d1b 195 kvfree(adev->vcn.saved_bo);
95d0906f
LL		 196 adev->vcn.saved_bo = NULL;
197 } else {
198 const struct common_firmware_header *hdr;
199 unsigned offset;
200
201 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
4d77c0f6
LG		 202 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
203 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
204 memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
205 le32_to_cpu(hdr->ucode_size_bytes));
206 size -= le32_to_cpu(hdr->ucode_size_bytes);
207 ptr += le32_to_cpu(hdr->ucode_size_bytes);
208 }
95d0906f
LL		 209 memset_io(ptr, 0, size);
210 }
211
212 return 0;
213}
214
bd5d5180 215static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
d30e63b1 216 struct dpg_pause_state *new_state)
bd5d5180
JZ		 217{
218 int ret_code;
219 uint32_t reg_data = 0;
220 uint32_t reg_data2 = 0;
221 struct amdgpu_ring *ring;
222
223 /* pause/unpause if state is changed */
224 if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
225 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
226 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
227 new_state->fw_based, new_state->jpeg);
228
229 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
d30e63b1 230 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
bd5d5180
JZ		 231
232 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
233 ret_code = 0;
234
235 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
236 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
d30e63b1
AD		 237 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
238 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
bd5d5180
JZ		 239
240 if (!ret_code) {
241 /* pause DPG non-jpeg */
242 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
243 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
244 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
d30e63b1
AD		 245 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
246 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
bd5d5180
JZ		 247
248 /* Restore */
249 ring = &adev->vcn.ring_enc[0];
250 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
251 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
252 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
253 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
d30e63b1 254 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
bd5d5180
JZ		 255
256 ring = &adev->vcn.ring_enc[1];
257 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
258 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
259 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
260 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
261 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
262
263 ring = &adev->vcn.ring_dec;
264 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
2dc4aa52 265 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2));
bd5d5180 266 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
d30e63b1
AD		 267 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
268 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
bd5d5180
JZ		 269 }
270 } else {
271 /* unpause dpg non-jpeg, no need to wait */
272 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
273 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
274 }
275 adev->vcn.pause_state.fw_based = new_state->fw_based;
276 }
277
278 /* pause/unpause if state is changed */
279 if (adev->vcn.pause_state.jpeg != new_state->jpeg) {
280 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
281 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
282 new_state->fw_based, new_state->jpeg);
283
284 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
d30e63b1 285 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
bd5d5180
JZ		 286
287 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
288 ret_code = 0;
289
290 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
291 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
d30e63b1
AD		 292 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
293 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
bd5d5180
JZ		 294
295 if (!ret_code) {
296 /* Make sure JPRG Snoop is disabled before sending the pause */
297 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
298 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
299 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
300
301 /* pause DPG jpeg */
302 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
303 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
304 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
305 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
306 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code);
307
308 /* Restore */
309 ring = &adev->vcn.ring_jpeg;
310 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
b17c5249
JZ		 311 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
312 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
313 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
bd5d5180 314 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
b17c5249 315 lower_32_bits(ring->gpu_addr));
bd5d5180 316 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
b17c5249 317 upper_32_bits(ring->gpu_addr));
bd5d5180
JZ		 318 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
319 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
b17c5249
JZ		 320 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
321 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
bd5d5180
JZ		 322
323 ring = &adev->vcn.ring_dec;
324 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
2dc4aa52 325 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2));
bd5d5180 326 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
d30e63b1
AD		 327 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
328 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
bd5d5180
JZ		 329 }
330 } else {
331 /* unpause dpg jpeg, no need to wait */
332 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
333 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
334 }
335 adev->vcn.pause_state.jpeg = new_state->jpeg;
336 }
337
338 return 0;
339}
340
3e1086cf
LL		 341static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
342{
343 struct amdgpu_device *adev =
344 container_of(work, struct amdgpu_device, vcn.idle_work.work);
bd5d5180
JZ		 345 unsigned int fences = 0;
346 unsigned int i;
646e906d
AD		 347
348 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
349 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
350 }
3e1086cf 351
bd5d5180
JZ		 352 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
353 struct dpg_pause_state new_state;
354
355 if (fences)
356 new_state.fw_based = VCN_DPG_STATE__PAUSE;
357 else
358 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
359
360 if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
361 new_state.jpeg = VCN_DPG_STATE__PAUSE;
362 else
363 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
364
365 amdgpu_vcn_pause_dpg_mode(adev, &new_state);
366 }
367
7b4e54a9 368 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
bd5d5180 369 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
7b4e54a9 370
3e1086cf 371 if (fences == 0) {
3fded222 372 amdgpu_gfx_off_ctrl(adev, true);
22cc6c5e 373 if (adev->pm.dpm_enabled)
3e1086cf 374 amdgpu_dpm_enable_uvd(adev, false);
22cc6c5e
RZ		 375 else
376 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
377 AMD_PG_STATE_GATE);
3e1086cf
LL		 378 } else {
379 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
380 }
381}
382
383void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
384{
385 struct amdgpu_device *adev = ring->adev;
386 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
387
c1ee15b3 388 if (set_clocks) {
3fded222 389 amdgpu_gfx_off_ctrl(adev, false);
22cc6c5e
RZ		 390 if (adev->pm.dpm_enabled)
391 amdgpu_dpm_enable_uvd(adev, true);
392 else
393 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
394 AMD_PG_STATE_UNGATE);
3e1086cf 395 }
bd5d5180
JZ		 396
397 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
398 struct dpg_pause_state new_state;
399
400 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
401 new_state.fw_based = VCN_DPG_STATE__PAUSE;
402 else
403 new_state.fw_based = adev->vcn.pause_state.fw_based;
404
405 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
406 new_state.jpeg = VCN_DPG_STATE__PAUSE;
407 else
408 new_state.jpeg = adev->vcn.pause_state.jpeg;
409
410 amdgpu_vcn_pause_dpg_mode(adev, &new_state);
411 }
3e1086cf
LL		 412}
413
414void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
415{
416 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
417}
418
8c303c01
LL		 419int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
420{
421 struct amdgpu_device *adev = ring->adev;
422 uint32_t tmp = 0;
423 unsigned i;
424 int r;
425
21cbe2f3 426 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);
8c303c01 427 r = amdgpu_ring_alloc(ring, 3);
dc9eeff8 428 if (r)
8c303c01 429 return r;
dc9eeff8 430
8c303c01 431 amdgpu_ring_write(ring,
21cbe2f3 432 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0));
8c303c01
LL		 433 amdgpu_ring_write(ring, 0xDEADBEEF);
434 amdgpu_ring_commit(ring);
435 for (i = 0; i < adev->usec_timeout; i++) {
21cbe2f3 436 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
8c303c01
LL		 437 if (tmp == 0xDEADBEEF)
438 break;
439 DRM_UDELAY(1);
440 }
441
dc9eeff8
CK		 442 if (i >= adev->usec_timeout)
443 r = -ETIMEDOUT;
444
8c303c01
LL		 445 return r;
446}
447
add9f9a8 448static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
4c6530fd 449 struct amdgpu_bo *bo,
add9f9a8 450 struct dma_fence **fence)
95d0906f 451{
add9f9a8
CK		 452 struct amdgpu_device *adev = ring->adev;
453 struct dma_fence *f = NULL;
95d0906f
LL		 454 struct amdgpu_job *job;
455 struct amdgpu_ib *ib;
95d0906f
LL		 456 uint64_t addr;
457 int i, r;
458
95d0906f
LL		 459 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
460 if (r)
461 goto err;
462
463 ib = &job->ibs[0];
464 addr = amdgpu_bo_gpu_offset(bo);
465 ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);
466 ib->ptr[1] = addr;
467 ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);
468 ib->ptr[3] = addr >> 32;
469 ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);
470 ib->ptr[5] = 0;
471 for (i = 6; i < 16; i += 2) {
472 ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);
473 ib->ptr[i+1] = 0;
474 }
475 ib->length_dw = 16;
476
ee913fd9 477 r = amdgpu_job_submit_direct(job, ring, &f);
4c6530fd
LL		 478 if (r)
479 goto err_free;
95d0906f 480
add9f9a8
CK		 481 amdgpu_bo_fence(bo, f, false);
482 amdgpu_bo_unreserve(bo);
483 amdgpu_bo_unref(&bo);
95d0906f
LL		 484
485 if (fence)
486 *fence = dma_fence_get(f);
95d0906f
LL		 487 dma_fence_put(f);
488
489 return 0;
490
491err_free:
492 amdgpu_job_free(job);
493
494err:
add9f9a8
CK		 495 amdgpu_bo_unreserve(bo);
496 amdgpu_bo_unref(&bo);
95d0906f
LL		 497 return r;
498}
499
500static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
501 struct dma_fence **fence)
502{
503 struct amdgpu_device *adev = ring->adev;
add9f9a8 504 struct amdgpu_bo *bo = NULL;
95d0906f
LL		 505 uint32_t *msg;
506 int r, i;
507
add9f9a8
CK		 508 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
509 AMDGPU_GEM_DOMAIN_VRAM,
510 &bo, NULL, (void **)&msg);
95d0906f
LL		 511 if (r)
512 return r;
513
2d8a425b 514 msg[0] = cpu_to_le32(0x00000028);
3b8f5ab3 515 msg[1] = cpu_to_le32(0x00000038);
2d8a425b 516 msg[2] = cpu_to_le32(0x00000001);
95d0906f 517 msg[3] = cpu_to_le32(0x00000000);
2d8a425b 518 msg[4] = cpu_to_le32(handle);
95d0906f 519 msg[5] = cpu_to_le32(0x00000000);
2d8a425b
LL		 520 msg[6] = cpu_to_le32(0x00000001);
521 msg[7] = cpu_to_le32(0x00000028);
3b8f5ab3 522 msg[8] = cpu_to_le32(0x00000010);
95d0906f 523 msg[9] = cpu_to_le32(0x00000000);
2d8a425b
LL		 524 msg[10] = cpu_to_le32(0x00000007);
525 msg[11] = cpu_to_le32(0x00000000);
3b8f5ab3
LL		 526 msg[12] = cpu_to_le32(0x00000780);
527 msg[13] = cpu_to_le32(0x00000440);
528 for (i = 14; i < 1024; ++i)
95d0906f
LL		 529 msg[i] = cpu_to_le32(0x0);
530
4c6530fd 531 return amdgpu_vcn_dec_send_msg(ring, bo, fence);
95d0906f
LL		 532}
533
534static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
4c6530fd 535 struct dma_fence **fence)
95d0906f
LL		 536{
537 struct amdgpu_device *adev = ring->adev;
add9f9a8 538 struct amdgpu_bo *bo = NULL;
95d0906f
LL		 539 uint32_t *msg;
540 int r, i;
541
add9f9a8
CK		 542 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
543 AMDGPU_GEM_DOMAIN_VRAM,
544 &bo, NULL, (void **)&msg);
95d0906f
LL		 545 if (r)
546 return r;
547
2d8a425b
LL		 548 msg[0] = cpu_to_le32(0x00000028);
549 msg[1] = cpu_to_le32(0x00000018);
550 msg[2] = cpu_to_le32(0x00000000);
551 msg[3] = cpu_to_le32(0x00000002);
552 msg[4] = cpu_to_le32(handle);
553 msg[5] = cpu_to_le32(0x00000000);
554 for (i = 6; i < 1024; ++i)
95d0906f
LL		 555 msg[i] = cpu_to_le32(0x0);
556
4c6530fd 557 return amdgpu_vcn_dec_send_msg(ring, bo, fence);
95d0906f
LL		 558}
559
95d0906f
LL		 560int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
561{
562 struct dma_fence *fence;
563 long r;
564
565 r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
566 if (r) {
567 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
568 goto error;
569 }
570
4c6530fd 571 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
95d0906f
LL		 572 if (r) {
573 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
574 goto error;
575 }
576
577 r = dma_fence_wait_timeout(fence, false, timeout);
578 if (r == 0) {
579 DRM_ERROR("amdgpu: IB test timed out.\n");
580 r = -ETIMEDOUT;
581 } else if (r < 0) {
582 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
583 } else {
9953b72f 584 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
95d0906f
LL		 585 r = 0;
586 }
587
588 dma_fence_put(fence);
589
590error:
591 return r;
592}
2d531d81 593
3e1086cf
LL		 594int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
595{
596 struct amdgpu_device *adev = ring->adev;
597 uint32_t rptr = amdgpu_ring_get_rptr(ring);
598 unsigned i;
599 int r;
600
601 r = amdgpu_ring_alloc(ring, 16);
dc9eeff8 602 if (r)
3e1086cf 603 return r;
dc9eeff8 604
c3bd3040 605 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
3e1086cf
LL		 606 amdgpu_ring_commit(ring);
607
608 for (i = 0; i < adev->usec_timeout; i++) {
609 if (amdgpu_ring_get_rptr(ring) != rptr)
610 break;
611 DRM_UDELAY(1);
612 }
613
dc9eeff8 614 if (i >= adev->usec_timeout)
3e1086cf 615 r = -ETIMEDOUT;
3e1086cf
LL		 616
617 return r;
618}
619
2d531d81
LL		 620static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
621 struct dma_fence **fence)
622{
25547cfd 623 const unsigned ib_size_dw = 16;
2d531d81
LL		 624 struct amdgpu_job *job;
625 struct amdgpu_ib *ib;
626 struct dma_fence *f = NULL;
627 uint64_t dummy;
628 int i, r;
629
630 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
631 if (r)
632 return r;
633
634 ib = &job->ibs[0];
2d531d81
LL		 635 dummy = ib->gpu_addr + 1024;
636
2d531d81 637 ib->length_dw = 0;
25547cfd
LL		 638 ib->ptr[ib->length_dw++] = 0x00000018;
639 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
2d531d81 640 ib->ptr[ib->length_dw++] = handle;
25547cfd
LL		 641 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
642 ib->ptr[ib->length_dw++] = dummy;
643 ib->ptr[ib->length_dw++] = 0x0000000b;
2d531d81 644
25547cfd
LL		 645 ib->ptr[ib->length_dw++] = 0x00000014;
646 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
647 ib->ptr[ib->length_dw++] = 0x0000001c;
2d531d81
LL		 648 ib->ptr[ib->length_dw++] = 0x00000000;
649 ib->ptr[ib->length_dw++] = 0x00000000;
650
25547cfd
LL		 651 ib->ptr[ib->length_dw++] = 0x00000008;
652 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
2d531d81
LL		 653
654 for (i = ib->length_dw; i < ib_size_dw; ++i)
655 ib->ptr[i] = 0x0;
656
ee913fd9 657 r = amdgpu_job_submit_direct(job, ring, &f);
2d531d81
LL		 658 if (r)
659 goto err;
660
2d531d81
LL		 661 if (fence)
662 *fence = dma_fence_get(f);
663 dma_fence_put(f);
25547cfd 664
2d531d81
LL		 665 return 0;
666
667err:
668 amdgpu_job_free(job);
669 return r;
670}
671
672static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
25547cfd 673 struct dma_fence **fence)
2d531d81 674{
25547cfd 675 const unsigned ib_size_dw = 16;
2d531d81
LL		 676 struct amdgpu_job *job;
677 struct amdgpu_ib *ib;
678 struct dma_fence *f = NULL;
25547cfd 679 uint64_t dummy;
2d531d81
LL		 680 int i, r;
681
682 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
683 if (r)
684 return r;
685
686 ib = &job->ibs[0];
25547cfd 687 dummy = ib->gpu_addr + 1024;
2d531d81 688
2d531d81 689 ib->length_dw = 0;
25547cfd
LL		 690 ib->ptr[ib->length_dw++] = 0x00000018;
691 ib->ptr[ib->length_dw++] = 0x00000001;
2d531d81 692 ib->ptr[ib->length_dw++] = handle;
25547cfd
LL		 693 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
694 ib->ptr[ib->length_dw++] = dummy;
695 ib->ptr[ib->length_dw++] = 0x0000000b;
2d531d81 696
25547cfd
LL		 697 ib->ptr[ib->length_dw++] = 0x00000014;
698 ib->ptr[ib->length_dw++] = 0x00000002;
699 ib->ptr[ib->length_dw++] = 0x0000001c;
2d531d81 700 ib->ptr[ib->length_dw++] = 0x00000000;
2d531d81
LL		 701 ib->ptr[ib->length_dw++] = 0x00000000;
702
25547cfd
LL		 703 ib->ptr[ib->length_dw++] = 0x00000008;
704 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
2d531d81
LL		 705
706 for (i = ib->length_dw; i < ib_size_dw; ++i)
707 ib->ptr[i] = 0x0;
708
ee913fd9 709 r = amdgpu_job_submit_direct(job, ring, &f);
25547cfd
LL		 710 if (r)
711 goto err;
2d531d81
LL		 712
713 if (fence)
714 *fence = dma_fence_get(f);
715 dma_fence_put(f);
25547cfd 716
2d531d81
LL		 717 return 0;
718
719err:
720 amdgpu_job_free(job);
721 return r;
722}
723
2d531d81
LL		 724int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
725{
726 struct dma_fence *fence = NULL;
727 long r;
728
729 r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
730 if (r) {
731 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
732 goto error;
733 }
734
25547cfd 735 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
2d531d81
LL		 736 if (r) {
737 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
738 goto error;
739 }
740
741 r = dma_fence_wait_timeout(fence, false, timeout);
742 if (r == 0) {
743 DRM_ERROR("amdgpu: IB test timed out.\n");
744 r = -ETIMEDOUT;
745 } else if (r < 0) {
746 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
747 } else {
9953b72f 748 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
2d531d81
LL		 749 r = 0;
750 }
751error:
752 dma_fence_put(fence);
753 return r;
754}
b1d37606
BZ		 755
756int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
757{
758 struct amdgpu_device *adev = ring->adev;
759 uint32_t tmp = 0;
760 unsigned i;
761 int r;
762
21cbe2f3 763 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);
b1d37606
BZ		 764 r = amdgpu_ring_alloc(ring, 3);
765
dc9eeff8 766 if (r)
b1d37606 767 return r;
b1d37606
BZ		 768
769 amdgpu_ring_write(ring,
21cbe2f3 770 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, 0));
b1d37606
BZ		 771 amdgpu_ring_write(ring, 0xDEADBEEF);
772 amdgpu_ring_commit(ring);
773
774 for (i = 0; i < adev->usec_timeout; i++) {
21cbe2f3 775 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
b1d37606
BZ		 776 if (tmp == 0xDEADBEEF)
777 break;
778 DRM_UDELAY(1);
779 }
780
dc9eeff8
CK		 781 if (i >= adev->usec_timeout)
782 r = -ETIMEDOUT;
b1d37606
BZ		 783
784 return r;
785}
6173040f
BZ		 786
787static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
788 struct dma_fence **fence)
789{
790 struct amdgpu_device *adev = ring->adev;
791 struct amdgpu_job *job;
792 struct amdgpu_ib *ib;
793 struct dma_fence *f = NULL;
794 const unsigned ib_size_dw = 16;
795 int i, r;
796
797 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
798 if (r)
799 return r;
800
801 ib = &job->ibs[0];
802
21cbe2f3 803 ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, PACKETJ_TYPE0);
6173040f
BZ		 804 ib->ptr[1] = 0xDEADBEEF;
805 for (i = 2; i < 16; i += 2) {
806 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
807 ib->ptr[i+1] = 0;
808 }
809 ib->length_dw = 16;
810
ee913fd9 811 r = amdgpu_job_submit_direct(job, ring, &f);
6173040f
BZ		 812 if (r)
813 goto err;
814
6173040f
BZ		 815 if (fence)
816 *fence = dma_fence_get(f);
817 dma_fence_put(f);
818
819 return 0;
820
821err:
822 amdgpu_job_free(job);
823 return r;
824}
825
826int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
827{
828 struct amdgpu_device *adev = ring->adev;
829 uint32_t tmp = 0;
830 unsigned i;
831 struct dma_fence *fence = NULL;
832 long r = 0;
833
834 r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence);
835 if (r) {
836 DRM_ERROR("amdgpu: failed to set jpeg register (%ld).\n", r);
837 goto error;
838 }
839
840 r = dma_fence_wait_timeout(fence, false, timeout);
841 if (r == 0) {
842 DRM_ERROR("amdgpu: IB test timed out.\n");
843 r = -ETIMEDOUT;
844 goto error;
845 } else if (r < 0) {
846 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
847 goto error;
848 } else
849 r = 0;
850
851 for (i = 0; i < adev->usec_timeout; i++) {
21cbe2f3 852 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
6173040f
BZ		 853 if (tmp == 0xDEADBEEF)
854 break;
855 DRM_UDELAY(1);
856 }
857
858 if (i < adev->usec_timeout)
859 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
860 else {
861 DRM_ERROR("ib test failed (0x%08X)\n", tmp);
862 r = -EINVAL;
863 }
864
865 dma_fence_put(fence);
866
867error:
868 return r;
869}
Linux 6.x block layer and io_uring tree(s)