Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Christian König <deathsimple@vodafone.de> | |
29 | */ | |
30 | ||
31 | #include <linux/firmware.h> | |
32 | #include <linux/module.h> | |
fdf2f6c5 | 33 | |
d38ceaf9 | 34 | #include <drm/drm.h> |
f89f8c6b | 35 | #include <drm/drm_drv.h> |
d38ceaf9 AD |
36 | |
37 | #include "amdgpu.h" | |
38 | #include "amdgpu_pm.h" | |
39 | #include "amdgpu_uvd.h" | |
a190f8dc | 40 | #include "amdgpu_cs.h" |
d38ceaf9 AD |
41 | #include "cikd.h" |
42 | #include "uvd/uvd_4_2_d.h" | |
43 | ||
8baaadba LM |
44 | #include "amdgpu_ras.h" |
45 | ||
d38ceaf9 | 46 | /* 1 second timeout */ |
08086635 | 47 | #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) |
4cb5877c CK |
48 | |
49 | /* Firmware versions for VI */ | |
50 | #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) | |
51 | #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) | |
52 | #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) | |
53 | #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) | |
54 | ||
8e008dd7 | 55 | /* Polaris10/11 firmware version */ |
4cb5877c | 56 | #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) |
d38ceaf9 AD |
57 | |
58 | /* Firmware Names */ | |
d1af7ac2 SJ |
59 | #ifdef CONFIG_DRM_AMDGPU_SI |
60 | #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin" | |
61 | #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin" | |
62 | #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin" | |
63 | #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin" | |
64 | #endif | |
d38ceaf9 | 65 | #ifdef CONFIG_DRM_AMDGPU_CIK |
ce206464 AD |
66 | #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" |
67 | #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" | |
68 | #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" | |
69 | #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" | |
70 | #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" | |
d38ceaf9 | 71 | #endif |
c65444fe JZ |
72 | #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" |
73 | #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" | |
974ee3db | 74 | #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" |
a39c8cea | 75 | #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" |
2cc0c0b5 | 76 | #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" |
925a51c4 | 77 | #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" |
c4642a47 | 78 | #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" |
ba8f7ad0 | 79 | #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" |
d38ceaf9 | 80 | |
09bfb891 | 81 | #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" |
2327e626 | 82 | #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" |
cac18c82 | 83 | #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" |
09bfb891 | 84 | |
9181dba6 JZ |
85 | /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ |
86 | #define UVD_GPCOM_VCPU_CMD 0x03c3 | |
87 | #define UVD_GPCOM_VCPU_DATA0 0x03c4 | |
88 | #define UVD_GPCOM_VCPU_DATA1 0x03c5 | |
89 | #define UVD_NO_OP 0x03ff | |
90 | #define UVD_BASE_SI 0x3800 | |
09bfb891 | 91 | |
ce0e124a | 92 | /* |
d38ceaf9 AD |
93 | * amdgpu_uvd_cs_ctx - Command submission parser context |
94 | * | |
95 | * Used for emulating virtual memory support on UVD 4.2. | |
96 | */ | |
97 | struct amdgpu_uvd_cs_ctx { | |
98 | struct amdgpu_cs_parser *parser; | |
f10984a3 SS |
99 | unsigned int reg, count; |
100 | unsigned int data0, data1; | |
101 | unsigned int idx; | |
cdc7893f | 102 | struct amdgpu_ib *ib; |
d38ceaf9 AD |
103 | |
104 | /* does the IB has a msg command */ | |
105 | bool has_msg_cmd; | |
106 | ||
107 | /* minimum buffer sizes */ | |
f10984a3 | 108 | unsigned int *buf_sizes; |
d38ceaf9 AD |
109 | }; |
110 | ||
d1af7ac2 SJ |
111 | #ifdef CONFIG_DRM_AMDGPU_SI |
112 | MODULE_FIRMWARE(FIRMWARE_TAHITI); | |
113 | MODULE_FIRMWARE(FIRMWARE_VERDE); | |
114 | MODULE_FIRMWARE(FIRMWARE_PITCAIRN); | |
115 | MODULE_FIRMWARE(FIRMWARE_OLAND); | |
116 | #endif | |
d38ceaf9 AD |
117 | #ifdef CONFIG_DRM_AMDGPU_CIK |
118 | MODULE_FIRMWARE(FIRMWARE_BONAIRE); | |
119 | MODULE_FIRMWARE(FIRMWARE_KABINI); | |
120 | MODULE_FIRMWARE(FIRMWARE_KAVERI); | |
121 | MODULE_FIRMWARE(FIRMWARE_HAWAII); | |
122 | MODULE_FIRMWARE(FIRMWARE_MULLINS); | |
123 | #endif | |
124 | MODULE_FIRMWARE(FIRMWARE_TONGA); | |
125 | MODULE_FIRMWARE(FIRMWARE_CARRIZO); | |
974ee3db | 126 | MODULE_FIRMWARE(FIRMWARE_FIJI); |
a39c8cea | 127 | MODULE_FIRMWARE(FIRMWARE_STONEY); |
2cc0c0b5 FC |
128 | MODULE_FIRMWARE(FIRMWARE_POLARIS10); |
129 | MODULE_FIRMWARE(FIRMWARE_POLARIS11); | |
c4642a47 | 130 | MODULE_FIRMWARE(FIRMWARE_POLARIS12); |
ba8f7ad0 | 131 | MODULE_FIRMWARE(FIRMWARE_VEGAM); |
d38ceaf9 | 132 | |
09bfb891 | 133 | MODULE_FIRMWARE(FIRMWARE_VEGA10); |
2327e626 | 134 | MODULE_FIRMWARE(FIRMWARE_VEGA12); |
cac18c82 | 135 | MODULE_FIRMWARE(FIRMWARE_VEGA20); |
09bfb891 | 136 | |
d38ceaf9 | 137 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work); |
68331d7c | 138 | static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo); |
139 | ||
140 | static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev, | |
141 | uint32_t size, | |
142 | struct amdgpu_bo **bo_ptr) | |
143 | { | |
144 | struct ttm_operation_ctx ctx = { true, false }; | |
145 | struct amdgpu_bo *bo = NULL; | |
146 | void *addr; | |
147 | int r; | |
148 | ||
149 | r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, | |
150 | AMDGPU_GEM_DOMAIN_GTT, | |
151 | &bo, NULL, &addr); | |
152 | if (r) | |
153 | return r; | |
154 | ||
155 | if (adev->uvd.address_64_bit) | |
156 | goto succ; | |
157 | ||
158 | amdgpu_bo_kunmap(bo); | |
159 | amdgpu_bo_unpin(bo); | |
160 | amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); | |
161 | amdgpu_uvd_force_into_uvd_segment(bo); | |
162 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
163 | if (r) | |
164 | goto err; | |
165 | r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); | |
166 | if (r) | |
167 | goto err_pin; | |
168 | r = amdgpu_bo_kmap(bo, &addr); | |
169 | if (r) | |
170 | goto err_kmap; | |
171 | succ: | |
172 | amdgpu_bo_unreserve(bo); | |
173 | *bo_ptr = bo; | |
174 | return 0; | |
175 | err_kmap: | |
176 | amdgpu_bo_unpin(bo); | |
177 | err_pin: | |
178 | err: | |
179 | amdgpu_bo_unreserve(bo); | |
180 | amdgpu_bo_unref(&bo); | |
181 | return r; | |
182 | } | |
d38ceaf9 AD |
183 | |
184 | int amdgpu_uvd_sw_init(struct amdgpu_device *adev) | |
185 | { | |
186 | unsigned long bo_size; | |
187 | const char *fw_name; | |
188 | const struct common_firmware_header *hdr; | |
f10984a3 | 189 | unsigned int family_id; |
10dd74ea | 190 | int i, j, r; |
d38ceaf9 | 191 | |
5c53d19b | 192 | INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); |
d38ceaf9 AD |
193 | |
194 | switch (adev->asic_type) { | |
d1af7ac2 SJ |
195 | #ifdef CONFIG_DRM_AMDGPU_SI |
196 | case CHIP_TAHITI: | |
197 | fw_name = FIRMWARE_TAHITI; | |
198 | break; | |
199 | case CHIP_VERDE: | |
200 | fw_name = FIRMWARE_VERDE; | |
201 | break; | |
202 | case CHIP_PITCAIRN: | |
203 | fw_name = FIRMWARE_PITCAIRN; | |
204 | break; | |
205 | case CHIP_OLAND: | |
206 | fw_name = FIRMWARE_OLAND; | |
207 | break; | |
208 | #endif | |
d38ceaf9 AD |
209 | #ifdef CONFIG_DRM_AMDGPU_CIK |
210 | case CHIP_BONAIRE: | |
211 | fw_name = FIRMWARE_BONAIRE; | |
212 | break; | |
213 | case CHIP_KABINI: | |
214 | fw_name = FIRMWARE_KABINI; | |
215 | break; | |
216 | case CHIP_KAVERI: | |
217 | fw_name = FIRMWARE_KAVERI; | |
218 | break; | |
219 | case CHIP_HAWAII: | |
220 | fw_name = FIRMWARE_HAWAII; | |
221 | break; | |
222 | case CHIP_MULLINS: | |
223 | fw_name = FIRMWARE_MULLINS; | |
224 | break; | |
225 | #endif | |
226 | case CHIP_TONGA: | |
227 | fw_name = FIRMWARE_TONGA; | |
228 | break; | |
974ee3db DZ |
229 | case CHIP_FIJI: |
230 | fw_name = FIRMWARE_FIJI; | |
231 | break; | |
d38ceaf9 AD |
232 | case CHIP_CARRIZO: |
233 | fw_name = FIRMWARE_CARRIZO; | |
234 | break; | |
a39c8cea SL |
235 | case CHIP_STONEY: |
236 | fw_name = FIRMWARE_STONEY; | |
237 | break; | |
2cc0c0b5 FC |
238 | case CHIP_POLARIS10: |
239 | fw_name = FIRMWARE_POLARIS10; | |
38d75817 | 240 | break; |
2cc0c0b5 FC |
241 | case CHIP_POLARIS11: |
242 | fw_name = FIRMWARE_POLARIS11; | |
c4642a47 | 243 | break; |
2327e626 AD |
244 | case CHIP_POLARIS12: |
245 | fw_name = FIRMWARE_POLARIS12; | |
246 | break; | |
09bfb891 LL |
247 | case CHIP_VEGA10: |
248 | fw_name = FIRMWARE_VEGA10; | |
249 | break; | |
2327e626 AD |
250 | case CHIP_VEGA12: |
251 | fw_name = FIRMWARE_VEGA12; | |
38d75817 | 252 | break; |
ba8f7ad0 LL |
253 | case CHIP_VEGAM: |
254 | fw_name = FIRMWARE_VEGAM; | |
255 | break; | |
cac18c82 FX |
256 | case CHIP_VEGA20: |
257 | fw_name = FIRMWARE_VEGA20; | |
258 | break; | |
d38ceaf9 AD |
259 | default: |
260 | return -EINVAL; | |
261 | } | |
262 | ||
b406477c | 263 | r = amdgpu_ucode_request(adev, &adev->uvd.fw, fw_name); |
d38ceaf9 AD |
264 | if (r) { |
265 | dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", | |
266 | fw_name); | |
b406477c | 267 | amdgpu_ucode_release(&adev->uvd.fw); |
d38ceaf9 AD |
268 | return r; |
269 | } | |
270 | ||
c0365541 AN |
271 | /* Set the default UVD handles that the firmware can handle */ |
272 | adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; | |
273 | ||
d38ceaf9 AD |
274 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; |
275 | family_id = le32_to_cpu(hdr->ucode_version) & 0xff; | |
dd06eecb JZ |
276 | |
277 | if (adev->asic_type < CHIP_VEGA20) { | |
f10984a3 | 278 | unsigned int version_major, version_minor; |
5c219927 | 279 | |
dd06eecb JZ |
280 | version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; |
281 | version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; | |
0b437e64 | 282 | DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n", |
dd06eecb | 283 | version_major, version_minor, family_id); |
5c219927 AD |
284 | |
285 | /* | |
286 | * Limit the number of UVD handles depending on microcode major | |
287 | * and minor versions. The firmware version which has 40 UVD | |
288 | * instances support is 1.80. So all subsequent versions should | |
289 | * also have the same support. | |
290 | */ | |
291 | if ((version_major > 0x01) || | |
292 | ((version_major == 0x01) && (version_minor >= 0x50))) | |
293 | adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; | |
294 | ||
295 | adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | | |
296 | (family_id << 8)); | |
297 | ||
298 | if ((adev->asic_type == CHIP_POLARIS10 || | |
299 | adev->asic_type == CHIP_POLARIS11) && | |
300 | (adev->uvd.fw_version < FW_1_66_16)) | |
7d98d416 | 301 | DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n", |
5c219927 | 302 | version_major, version_minor); |
dd06eecb JZ |
303 | } else { |
304 | unsigned int enc_major, enc_minor, dec_minor; | |
305 | ||
306 | dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; | |
307 | enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; | |
308 | enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; | |
0b437e64 | 309 | DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", |
dd06eecb | 310 | enc_major, enc_minor, dec_minor, family_id); |
d38ceaf9 | 311 | |
c0365541 AN |
312 | adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; |
313 | ||
5c219927 AD |
314 | adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); |
315 | } | |
8e008dd7 | 316 | |
09bfb891 | 317 | bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE |
c0365541 | 318 | + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; |
09bfb891 LL |
319 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) |
320 | bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); | |
321 | ||
10dd74ea | 322 | for (j = 0; j < adev->uvd.num_uvd_inst; j++) { |
f1e582eb AD |
323 | if (adev->uvd.harvest_config & (1 << j)) |
324 | continue; | |
10dd74ea | 325 | r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, |
58ab2c08 CK |
326 | AMDGPU_GEM_DOMAIN_VRAM | |
327 | AMDGPU_GEM_DOMAIN_GTT, | |
328 | &adev->uvd.inst[j].vcpu_bo, | |
329 | &adev->uvd.inst[j].gpu_addr, | |
330 | &adev->uvd.inst[j].cpu_addr); | |
10dd74ea JZ |
331 | if (r) { |
332 | dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); | |
333 | return r; | |
334 | } | |
5c675bf2 | 335 | } |
ead833ec | 336 | |
5c675bf2 CK |
337 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
338 | atomic_set(&adev->uvd.handles[i], 0); | |
339 | adev->uvd.filp[i] = NULL; | |
340 | } | |
341 | ||
d38ceaf9 | 342 | /* from uvd v5.0 HW addressing capacity increased to 64 bits */ |
2990a1fc | 343 | if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) |
d38ceaf9 AD |
344 | adev->uvd.address_64_bit = true; |
345 | ||
68331d7c | 346 | r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo); |
347 | if (r) | |
348 | return r; | |
349 | ||
4cb5877c CK |
350 | switch (adev->asic_type) { |
351 | case CHIP_TONGA: | |
352 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; | |
353 | break; | |
354 | case CHIP_CARRIZO: | |
355 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; | |
356 | break; | |
357 | case CHIP_FIJI: | |
358 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; | |
359 | break; | |
360 | case CHIP_STONEY: | |
361 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; | |
362 | break; | |
363 | default: | |
364 | adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; | |
365 | } | |
366 | ||
d38ceaf9 AD |
367 | return 0; |
368 | } | |
369 | ||
370 | int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) | |
371 | { | |
68331d7c | 372 | void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo); |
10dd74ea | 373 | int i, j; |
d38ceaf9 | 374 | |
cdc50176 | 375 | drm_sched_entity_destroy(&adev->uvd.entity); |
5c675bf2 | 376 | |
10dd74ea | 377 | for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { |
f1e582eb AD |
378 | if (adev->uvd.harvest_config & (1 << j)) |
379 | continue; | |
c9533d1b | 380 | kvfree(adev->uvd.inst[j].saved_bo); |
ead833ec | 381 | |
10dd74ea JZ |
382 | amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, |
383 | &adev->uvd.inst[j].gpu_addr, | |
384 | (void **)&adev->uvd.inst[j].cpu_addr); | |
d38ceaf9 | 385 | |
10dd74ea | 386 | amdgpu_ring_fini(&adev->uvd.inst[j].ring); |
4ff184d7 | 387 | |
10dd74ea JZ |
388 | for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) |
389 | amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); | |
390 | } | |
68331d7c | 391 | amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr); |
b406477c | 392 | amdgpu_ucode_release(&adev->uvd.fw); |
d38ceaf9 AD |
393 | |
394 | return 0; | |
395 | } | |
396 | ||
33d5bd07 ED |
397 | /** |
398 | * amdgpu_uvd_entity_init - init entity | |
399 | * | |
400 | * @adev: amdgpu_device pointer | |
8a0173cd | 401 | * @ring: amdgpu_ring pointer to check |
33d5bd07 | 402 | * |
037b98a2 | 403 | * Initialize the entity used for handle management in the kernel driver. |
33d5bd07 | 404 | */ |
037b98a2 | 405 | int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) |
33d5bd07 | 406 | { |
037b98a2 AD |
407 | if (ring == &adev->uvd.inst[0].ring) { |
408 | struct drm_gpu_scheduler *sched = &ring->sched; | |
409 | int r; | |
33d5bd07 | 410 | |
037b98a2 AD |
411 | r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, |
412 | &sched, 1, NULL); | |
413 | if (r) { | |
414 | DRM_ERROR("Failed setting up UVD kernel entity.\n"); | |
415 | return r; | |
416 | } | |
33d5bd07 ED |
417 | } |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
db998890 | 422 | int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev) |
d38ceaf9 | 423 | { |
f10984a3 | 424 | unsigned int size; |
3f99dd81 | 425 | void *ptr; |
f89f8c6b | 426 | int i, j, idx; |
d38ceaf9 | 427 | |
5c53d19b JZ |
428 | cancel_delayed_work_sync(&adev->uvd.idle_work); |
429 | ||
5c675bf2 CK |
430 | /* only valid for physical mode */ |
431 | if (adev->asic_type < CHIP_POLARIS10) { | |
432 | for (i = 0; i < adev->uvd.max_handles; ++i) | |
433 | if (atomic_read(&adev->uvd.handles[i])) | |
434 | break; | |
435 | ||
436 | if (i == adev->uvd.max_handles) | |
437 | return 0; | |
438 | } | |
439 | ||
10dd74ea | 440 | for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { |
f1e582eb AD |
441 | if (adev->uvd.harvest_config & (1 << j)) |
442 | continue; | |
10dd74ea JZ |
443 | if (adev->uvd.inst[j].vcpu_bo == NULL) |
444 | continue; | |
d38ceaf9 | 445 | |
10dd74ea JZ |
446 | size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); |
447 | ptr = adev->uvd.inst[j].cpu_addr; | |
d38ceaf9 | 448 | |
c9533d1b | 449 | adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); |
10dd74ea JZ |
450 | if (!adev->uvd.inst[j].saved_bo) |
451 | return -ENOMEM; | |
d38ceaf9 | 452 | |
c58a863b | 453 | if (drm_dev_enter(adev_to_drm(adev), &idx)) { |
f89f8c6b | 454 | /* re-write 0 since err_event_athub will corrupt VCPU buffer */ |
db998890 | 455 | if (amdgpu_ras_intr_triggered()) |
f89f8c6b AG |
456 | memset(adev->uvd.inst[j].saved_bo, 0, size); |
457 | else | |
458 | memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); | |
459 | ||
460 | drm_dev_exit(idx); | |
461 | } | |
10dd74ea | 462 | } |
76434f75 | 463 | |
db998890 ML |
464 | return 0; |
465 | } | |
466 | ||
467 | int amdgpu_uvd_suspend(struct amdgpu_device *adev) | |
468 | { | |
469 | if (amdgpu_ras_intr_triggered()) | |
76434f75 LM |
470 | DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); |
471 | ||
d38ceaf9 AD |
472 | return 0; |
473 | } | |
474 | ||
475 | int amdgpu_uvd_resume(struct amdgpu_device *adev) | |
476 | { | |
f10984a3 | 477 | unsigned int size; |
d38ceaf9 | 478 | void *ptr; |
f89f8c6b | 479 | int i, idx; |
d38ceaf9 | 480 | |
10dd74ea | 481 | for (i = 0; i < adev->uvd.num_uvd_inst; i++) { |
f1e582eb AD |
482 | if (adev->uvd.harvest_config & (1 << i)) |
483 | continue; | |
10dd74ea JZ |
484 | if (adev->uvd.inst[i].vcpu_bo == NULL) |
485 | return -EINVAL; | |
d38ceaf9 | 486 | |
10dd74ea JZ |
487 | size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); |
488 | ptr = adev->uvd.inst[i].cpu_addr; | |
d38ceaf9 | 489 | |
10dd74ea | 490 | if (adev->uvd.inst[i].saved_bo != NULL) { |
c58a863b | 491 | if (drm_dev_enter(adev_to_drm(adev), &idx)) { |
f89f8c6b AG |
492 | memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); |
493 | drm_dev_exit(idx); | |
494 | } | |
c9533d1b | 495 | kvfree(adev->uvd.inst[i].saved_bo); |
10dd74ea JZ |
496 | adev->uvd.inst[i].saved_bo = NULL; |
497 | } else { | |
498 | const struct common_firmware_header *hdr; | |
f10984a3 | 499 | unsigned int offset; |
10dd74ea JZ |
500 | |
501 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; | |
502 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
503 | offset = le32_to_cpu(hdr->ucode_array_offset_bytes); | |
c58a863b | 504 | if (drm_dev_enter(adev_to_drm(adev), &idx)) { |
f89f8c6b AG |
505 | memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, |
506 | le32_to_cpu(hdr->ucode_size_bytes)); | |
507 | drm_dev_exit(idx); | |
508 | } | |
10dd74ea JZ |
509 | size -= le32_to_cpu(hdr->ucode_size_bytes); |
510 | ptr += le32_to_cpu(hdr->ucode_size_bytes); | |
511 | } | |
512 | memset_io(ptr, 0, size); | |
513 | /* to restore uvd fence seq */ | |
514 | amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); | |
09bfb891 | 515 | } |
d23be4e3 | 516 | } |
d38ceaf9 AD |
517 | return 0; |
518 | } | |
519 | ||
520 | void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) | |
521 | { | |
5c675bf2 CK |
522 | struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; |
523 | int i, r; | |
d38ceaf9 | 524 | |
5c675bf2 CK |
525 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
526 | uint32_t handle = atomic_read(&adev->uvd.handles[i]); | |
d38ceaf9 | 527 | |
5c675bf2 CK |
528 | if (handle != 0 && adev->uvd.filp[i] == filp) { |
529 | struct dma_fence *fence; | |
10dd74ea | 530 | |
5c675bf2 CK |
531 | r = amdgpu_uvd_get_destroy_msg(ring, handle, false, |
532 | &fence); | |
533 | if (r) { | |
534 | DRM_ERROR("Error destroying UVD %d!\n", r); | |
535 | continue; | |
10dd74ea | 536 | } |
5c675bf2 CK |
537 | |
538 | dma_fence_wait(fence, false); | |
539 | dma_fence_put(fence); | |
540 | ||
541 | adev->uvd.filp[i] = NULL; | |
542 | atomic_set(&adev->uvd.handles[i], 0); | |
d38ceaf9 AD |
543 | } |
544 | } | |
545 | } | |
546 | ||
765e7fbf | 547 | static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) |
d38ceaf9 AD |
548 | { |
549 | int i; | |
f10984a3 | 550 | |
765e7fbf CK |
551 | for (i = 0; i < abo->placement.num_placement; ++i) { |
552 | abo->placements[i].fpfn = 0 >> PAGE_SHIFT; | |
553 | abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; | |
d38ceaf9 AD |
554 | } |
555 | } | |
556 | ||
80983e4d AD |
557 | static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) |
558 | { | |
559 | uint32_t lo, hi; | |
560 | uint64_t addr; | |
561 | ||
cdc7893f CK |
562 | lo = amdgpu_ib_get_value(ctx->ib, ctx->data0); |
563 | hi = amdgpu_ib_get_value(ctx->ib, ctx->data1); | |
80983e4d AD |
564 | addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); |
565 | ||
566 | return addr; | |
567 | } | |
568 | ||
d38ceaf9 AD |
569 | /** |
570 | * amdgpu_uvd_cs_pass1 - first parsing round | |
571 | * | |
572 | * @ctx: UVD parser context | |
573 | * | |
574 | * Make sure UVD message and feedback buffers are in VRAM and | |
575 | * nobody is violating an 256MB boundary. | |
576 | */ | |
577 | static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) | |
578 | { | |
19be5570 | 579 | struct ttm_operation_ctx tctx = { false, false }; |
d38ceaf9 AD |
580 | struct amdgpu_bo_va_mapping *mapping; |
581 | struct amdgpu_bo *bo; | |
80983e4d AD |
582 | uint32_t cmd; |
583 | uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); | |
d38ceaf9 AD |
584 | int r = 0; |
585 | ||
9cca0b8e CK |
586 | r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); |
587 | if (r) { | |
f10984a3 | 588 | DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); |
9cca0b8e | 589 | return r; |
d38ceaf9 AD |
590 | } |
591 | ||
592 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
593 | /* check if it's a message or feedback command */ | |
cdc7893f | 594 | cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; |
d38ceaf9 AD |
595 | if (cmd == 0x0 || cmd == 0x3) { |
596 | /* yes, force it into VRAM */ | |
597 | uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; | |
f10984a3 | 598 | |
c704ab18 | 599 | amdgpu_bo_placement_from_domain(bo, domain); |
d38ceaf9 AD |
600 | } |
601 | amdgpu_uvd_force_into_uvd_segment(bo); | |
602 | ||
19be5570 | 603 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); |
d38ceaf9 AD |
604 | } |
605 | ||
606 | return r; | |
607 | } | |
608 | ||
609 | /** | |
610 | * amdgpu_uvd_cs_msg_decode - handle UVD decode message | |
611 | * | |
ce0e124a | 612 | * @adev: amdgpu_device pointer |
d38ceaf9 | 613 | * @msg: pointer to message structure |
05a7e1cf | 614 | * @buf_sizes: placeholder to put the different buffer lengths |
d38ceaf9 AD |
615 | * |
616 | * Peek into the decode message and calculate the necessary buffer sizes. | |
617 | */ | |
8e008dd7 | 618 | static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, |
f10984a3 | 619 | unsigned int buf_sizes[]) |
d38ceaf9 | 620 | { |
f10984a3 SS |
621 | unsigned int stream_type = msg[4]; |
622 | unsigned int width = msg[6]; | |
623 | unsigned int height = msg[7]; | |
624 | unsigned int dpb_size = msg[9]; | |
625 | unsigned int pitch = msg[28]; | |
626 | unsigned int level = msg[57]; | |
d38ceaf9 | 627 | |
f10984a3 SS |
628 | unsigned int width_in_mb = width / 16; |
629 | unsigned int height_in_mb = ALIGN(height / 16, 2); | |
630 | unsigned int fs_in_mb = width_in_mb * height_in_mb; | |
d38ceaf9 | 631 | |
f10984a3 SS |
632 | unsigned int image_size, tmp, min_dpb_size, num_dpb_buffer; |
633 | unsigned int min_ctx_size = ~0; | |
d38ceaf9 AD |
634 | |
635 | image_size = width * height; | |
636 | image_size += image_size / 2; | |
637 | image_size = ALIGN(image_size, 1024); | |
638 | ||
639 | switch (stream_type) { | |
640 | case 0: /* H264 */ | |
f10984a3 | 641 | switch (level) { |
d38ceaf9 AD |
642 | case 30: |
643 | num_dpb_buffer = 8100 / fs_in_mb; | |
644 | break; | |
645 | case 31: | |
646 | num_dpb_buffer = 18000 / fs_in_mb; | |
647 | break; | |
648 | case 32: | |
649 | num_dpb_buffer = 20480 / fs_in_mb; | |
650 | break; | |
651 | case 41: | |
652 | num_dpb_buffer = 32768 / fs_in_mb; | |
653 | break; | |
654 | case 42: | |
655 | num_dpb_buffer = 34816 / fs_in_mb; | |
656 | break; | |
657 | case 50: | |
658 | num_dpb_buffer = 110400 / fs_in_mb; | |
659 | break; | |
660 | case 51: | |
661 | num_dpb_buffer = 184320 / fs_in_mb; | |
662 | break; | |
663 | default: | |
664 | num_dpb_buffer = 184320 / fs_in_mb; | |
665 | break; | |
666 | } | |
667 | num_dpb_buffer++; | |
668 | if (num_dpb_buffer > 17) | |
669 | num_dpb_buffer = 17; | |
670 | ||
671 | /* reference picture buffer */ | |
672 | min_dpb_size = image_size * num_dpb_buffer; | |
673 | ||
674 | /* macroblock context buffer */ | |
675 | min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
676 | ||
677 | /* IT surface buffer */ | |
678 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
679 | break; | |
680 | ||
681 | case 1: /* VC1 */ | |
682 | ||
683 | /* reference picture buffer */ | |
684 | min_dpb_size = image_size * 3; | |
685 | ||
686 | /* CONTEXT_BUFFER */ | |
687 | min_dpb_size += width_in_mb * height_in_mb * 128; | |
688 | ||
689 | /* IT surface buffer */ | |
690 | min_dpb_size += width_in_mb * 64; | |
691 | ||
692 | /* DB surface buffer */ | |
693 | min_dpb_size += width_in_mb * 128; | |
694 | ||
695 | /* BP */ | |
696 | tmp = max(width_in_mb, height_in_mb); | |
697 | min_dpb_size += ALIGN(tmp * 7 * 16, 64); | |
698 | break; | |
699 | ||
700 | case 3: /* MPEG2 */ | |
701 | ||
702 | /* reference picture buffer */ | |
703 | min_dpb_size = image_size * 3; | |
704 | break; | |
705 | ||
706 | case 4: /* MPEG4 */ | |
707 | ||
708 | /* reference picture buffer */ | |
709 | min_dpb_size = image_size * 3; | |
710 | ||
711 | /* CM */ | |
712 | min_dpb_size += width_in_mb * height_in_mb * 64; | |
713 | ||
714 | /* IT surface buffer */ | |
715 | min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); | |
716 | break; | |
717 | ||
8e008dd7 | 718 | case 7: /* H264 Perf */ |
f10984a3 | 719 | switch (level) { |
8e008dd7 SJ |
720 | case 30: |
721 | num_dpb_buffer = 8100 / fs_in_mb; | |
722 | break; | |
723 | case 31: | |
724 | num_dpb_buffer = 18000 / fs_in_mb; | |
725 | break; | |
726 | case 32: | |
727 | num_dpb_buffer = 20480 / fs_in_mb; | |
728 | break; | |
729 | case 41: | |
730 | num_dpb_buffer = 32768 / fs_in_mb; | |
731 | break; | |
732 | case 42: | |
733 | num_dpb_buffer = 34816 / fs_in_mb; | |
734 | break; | |
735 | case 50: | |
736 | num_dpb_buffer = 110400 / fs_in_mb; | |
737 | break; | |
738 | case 51: | |
739 | num_dpb_buffer = 184320 / fs_in_mb; | |
740 | break; | |
741 | default: | |
742 | num_dpb_buffer = 184320 / fs_in_mb; | |
743 | break; | |
744 | } | |
745 | num_dpb_buffer++; | |
746 | if (num_dpb_buffer > 17) | |
747 | num_dpb_buffer = 17; | |
748 | ||
749 | /* reference picture buffer */ | |
750 | min_dpb_size = image_size * num_dpb_buffer; | |
751 | ||
f10984a3 | 752 | if (!adev->uvd.use_ctx_buf) { |
8e008dd7 SJ |
753 | /* macroblock context buffer */ |
754 | min_dpb_size += | |
755 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
756 | ||
757 | /* IT surface buffer */ | |
758 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
759 | } else { | |
760 | /* macroblock context buffer */ | |
761 | min_ctx_size = | |
762 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
763 | } | |
764 | break; | |
765 | ||
d0b83d41 LL |
766 | case 8: /* MJPEG */ |
767 | min_dpb_size = 0; | |
768 | break; | |
769 | ||
86fa0bdc CK |
770 | case 16: /* H265 */ |
771 | image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; | |
772 | image_size = ALIGN(image_size, 256); | |
773 | ||
774 | num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; | |
775 | min_dpb_size = image_size * num_dpb_buffer; | |
8c8bac59 BZ |
776 | min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) |
777 | * 16 * num_dpb_buffer + 52 * 1024; | |
86fa0bdc CK |
778 | break; |
779 | ||
d38ceaf9 AD |
780 | default: |
781 | DRM_ERROR("UVD codec not handled %d!\n", stream_type); | |
782 | return -EINVAL; | |
783 | } | |
784 | ||
785 | if (width > pitch) { | |
786 | DRM_ERROR("Invalid UVD decoding target pitch!\n"); | |
787 | return -EINVAL; | |
788 | } | |
789 | ||
790 | if (dpb_size < min_dpb_size) { | |
791 | DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", | |
792 | dpb_size, min_dpb_size); | |
793 | return -EINVAL; | |
794 | } | |
795 | ||
796 | buf_sizes[0x1] = dpb_size; | |
797 | buf_sizes[0x2] = image_size; | |
8c8bac59 | 798 | buf_sizes[0x4] = min_ctx_size; |
8ca606de GS |
799 | /* store image width to adjust nb memory pstate */ |
800 | adev->uvd.decode_image_width = width; | |
d38ceaf9 AD |
801 | return 0; |
802 | } | |
803 | ||
804 | /** | |
805 | * amdgpu_uvd_cs_msg - handle UVD message | |
806 | * | |
807 | * @ctx: UVD parser context | |
808 | * @bo: buffer object containing the message | |
809 | * @offset: offset into the buffer object | |
810 | * | |
811 | * Peek into the UVD message and extract the session id. | |
812 | * Make sure that we don't open up to many sessions. | |
813 | */ | |
814 | static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, | |
f10984a3 | 815 | struct amdgpu_bo *bo, unsigned int offset) |
d38ceaf9 AD |
816 | { |
817 | struct amdgpu_device *adev = ctx->parser->adev; | |
818 | int32_t *msg, msg_type, handle; | |
d38ceaf9 | 819 | void *ptr; |
4127a59e CK |
820 | long r; |
821 | int i; | |
d38ceaf9 AD |
822 | |
823 | if (offset & 0x3F) { | |
5c675bf2 | 824 | DRM_ERROR("UVD messages must be 64 byte aligned!\n"); |
d38ceaf9 AD |
825 | return -EINVAL; |
826 | } | |
827 | ||
d38ceaf9 AD |
828 | r = amdgpu_bo_kmap(bo, &ptr); |
829 | if (r) { | |
5c675bf2 | 830 | DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); |
d38ceaf9 AD |
831 | return r; |
832 | } | |
833 | ||
834 | msg = ptr + offset; | |
835 | ||
836 | msg_type = msg[1]; | |
837 | handle = msg[2]; | |
838 | ||
839 | if (handle == 0) { | |
db7b8154 | 840 | amdgpu_bo_kunmap(bo); |
5c675bf2 | 841 | DRM_ERROR("Invalid UVD handle!\n"); |
d38ceaf9 AD |
842 | return -EINVAL; |
843 | } | |
844 | ||
5146419e LL |
845 | switch (msg_type) { |
846 | case 0: | |
847 | /* it's a create msg, calc image size (width * height) */ | |
848 | amdgpu_bo_kunmap(bo); | |
849 | ||
850 | /* try to alloc a new handle */ | |
c0365541 | 851 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5c675bf2 CK |
852 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
853 | DRM_ERROR(")Handle 0x%x already in use!\n", | |
854 | handle); | |
5146419e LL |
855 | return -EINVAL; |
856 | } | |
857 | ||
5c675bf2 CK |
858 | if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { |
859 | adev->uvd.filp[i] = ctx->parser->filp; | |
5146419e LL |
860 | return 0; |
861 | } | |
862 | } | |
863 | ||
5c675bf2 | 864 | DRM_ERROR("No more free UVD handles!\n"); |
7129d3ae | 865 | return -ENOSPC; |
5146419e LL |
866 | |
867 | case 1: | |
d38ceaf9 | 868 | /* it's a decode msg, calc buffer sizes */ |
8e008dd7 | 869 | r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); |
d38ceaf9 AD |
870 | amdgpu_bo_kunmap(bo); |
871 | if (r) | |
872 | return r; | |
873 | ||
5146419e | 874 | /* validate the handle */ |
c0365541 | 875 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5c675bf2 CK |
876 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
877 | if (adev->uvd.filp[i] != ctx->parser->filp) { | |
878 | DRM_ERROR("UVD handle collision detected!\n"); | |
5146419e LL |
879 | return -EINVAL; |
880 | } | |
881 | return 0; | |
882 | } | |
883 | } | |
884 | ||
5c675bf2 | 885 | DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); |
5146419e LL |
886 | return -ENOENT; |
887 | ||
888 | case 2: | |
d38ceaf9 | 889 | /* it's a destroy msg, free the handle */ |
c0365541 | 890 | for (i = 0; i < adev->uvd.max_handles; ++i) |
5c675bf2 | 891 | atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); |
d38ceaf9 AD |
892 | amdgpu_bo_kunmap(bo); |
893 | return 0; | |
d38ceaf9 | 894 | |
5146419e | 895 | default: |
5c675bf2 | 896 | DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); |
d38ceaf9 | 897 | } |
66c46621 | 898 | |
db7b8154 | 899 | amdgpu_bo_kunmap(bo); |
d38ceaf9 AD |
900 | return -EINVAL; |
901 | } | |
902 | ||
903 | /** | |
904 | * amdgpu_uvd_cs_pass2 - second parsing round | |
905 | * | |
906 | * @ctx: UVD parser context | |
907 | * | |
908 | * Patch buffer addresses, make sure buffer sizes are correct. | |
909 | */ | |
910 | static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) | |
911 | { | |
912 | struct amdgpu_bo_va_mapping *mapping; | |
913 | struct amdgpu_bo *bo; | |
80983e4d | 914 | uint32_t cmd; |
d38ceaf9 | 915 | uint64_t start, end; |
80983e4d | 916 | uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); |
d38ceaf9 AD |
917 | int r; |
918 | ||
9cca0b8e CK |
919 | r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); |
920 | if (r) { | |
f10984a3 | 921 | DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); |
9cca0b8e | 922 | return r; |
042eb910 | 923 | } |
d38ceaf9 AD |
924 | |
925 | start = amdgpu_bo_gpu_offset(bo); | |
926 | ||
a9f87f64 | 927 | end = (mapping->last + 1 - mapping->start); |
d38ceaf9 AD |
928 | end = end * AMDGPU_GPU_PAGE_SIZE + start; |
929 | ||
a9f87f64 | 930 | addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; |
d38ceaf9 AD |
931 | start += addr; |
932 | ||
cdc7893f CK |
933 | amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start)); |
934 | amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start)); | |
d38ceaf9 | 935 | |
cdc7893f | 936 | cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; |
d38ceaf9 AD |
937 | if (cmd < 0x4) { |
938 | if ((end - start) < ctx->buf_sizes[cmd]) { | |
939 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
f10984a3 | 940 | (unsigned int)(end - start), |
d38ceaf9 AD |
941 | ctx->buf_sizes[cmd]); |
942 | return -EINVAL; | |
943 | } | |
944 | ||
8c8bac59 BZ |
945 | } else if (cmd == 0x206) { |
946 | if ((end - start) < ctx->buf_sizes[4]) { | |
947 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
f10984a3 | 948 | (unsigned int)(end - start), |
8c8bac59 BZ |
949 | ctx->buf_sizes[4]); |
950 | return -EINVAL; | |
951 | } | |
d38ceaf9 AD |
952 | } else if ((cmd != 0x100) && (cmd != 0x204)) { |
953 | DRM_ERROR("invalid UVD command %X!\n", cmd); | |
954 | return -EINVAL; | |
955 | } | |
956 | ||
957 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
958 | if ((start >> 28) != ((end - 1) >> 28)) { | |
f10984a3 | 959 | DRM_ERROR("reloc %llx-%llx crossing 256MB boundary!\n", |
d38ceaf9 AD |
960 | start, end); |
961 | return -EINVAL; | |
962 | } | |
963 | ||
964 | if ((cmd == 0 || cmd == 0x3) && | |
2bb795f5 | 965 | (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { |
f10984a3 | 966 | DRM_ERROR("msg/fb buffer %llx-%llx out of 256MB segment!\n", |
d38ceaf9 AD |
967 | start, end); |
968 | return -EINVAL; | |
969 | } | |
970 | } | |
971 | ||
972 | if (cmd == 0) { | |
973 | ctx->has_msg_cmd = true; | |
974 | r = amdgpu_uvd_cs_msg(ctx, bo, addr); | |
975 | if (r) | |
976 | return r; | |
977 | } else if (!ctx->has_msg_cmd) { | |
978 | DRM_ERROR("Message needed before other commands are send!\n"); | |
979 | return -EINVAL; | |
980 | } | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
985 | /** | |
986 | * amdgpu_uvd_cs_reg - parse register writes | |
987 | * | |
988 | * @ctx: UVD parser context | |
989 | * @cb: callback function | |
990 | * | |
991 | * Parse the register writes, call cb on each complete command. | |
992 | */ | |
993 | static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, | |
994 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
995 | { | |
d38ceaf9 AD |
996 | int i, r; |
997 | ||
998 | ctx->idx++; | |
999 | for (i = 0; i <= ctx->count; ++i) { | |
f10984a3 | 1000 | unsigned int reg = ctx->reg + i; |
d38ceaf9 | 1001 | |
cdc7893f | 1002 | if (ctx->idx >= ctx->ib->length_dw) { |
d38ceaf9 AD |
1003 | DRM_ERROR("Register command after end of CS!\n"); |
1004 | return -EINVAL; | |
1005 | } | |
1006 | ||
1007 | switch (reg) { | |
1008 | case mmUVD_GPCOM_VCPU_DATA0: | |
1009 | ctx->data0 = ctx->idx; | |
1010 | break; | |
1011 | case mmUVD_GPCOM_VCPU_DATA1: | |
1012 | ctx->data1 = ctx->idx; | |
1013 | break; | |
1014 | case mmUVD_GPCOM_VCPU_CMD: | |
1015 | r = cb(ctx); | |
1016 | if (r) | |
1017 | return r; | |
1018 | break; | |
1019 | case mmUVD_ENGINE_CNTL: | |
8dd31d74 | 1020 | case mmUVD_NO_OP: |
d38ceaf9 AD |
1021 | break; |
1022 | default: | |
1023 | DRM_ERROR("Invalid reg 0x%X!\n", reg); | |
1024 | return -EINVAL; | |
1025 | } | |
1026 | ctx->idx++; | |
1027 | } | |
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | /** | |
1032 | * amdgpu_uvd_cs_packets - parse UVD packets | |
1033 | * | |
1034 | * @ctx: UVD parser context | |
1035 | * @cb: callback function | |
1036 | * | |
1037 | * Parse the command stream packets. | |
1038 | */ | |
1039 | static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, | |
1040 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
1041 | { | |
d38ceaf9 AD |
1042 | int r; |
1043 | ||
cdc7893f CK |
1044 | for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) { |
1045 | uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx); | |
f10984a3 SS |
1046 | unsigned int type = CP_PACKET_GET_TYPE(cmd); |
1047 | ||
d38ceaf9 AD |
1048 | switch (type) { |
1049 | case PACKET_TYPE0: | |
1050 | ctx->reg = CP_PACKET0_GET_REG(cmd); | |
1051 | ctx->count = CP_PACKET_GET_COUNT(cmd); | |
1052 | r = amdgpu_uvd_cs_reg(ctx, cb); | |
1053 | if (r) | |
1054 | return r; | |
1055 | break; | |
1056 | case PACKET_TYPE2: | |
1057 | ++ctx->idx; | |
1058 | break; | |
1059 | default: | |
1060 | DRM_ERROR("Unknown packet type %d !\n", type); | |
1061 | return -EINVAL; | |
1062 | } | |
1063 | } | |
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | /** | |
1068 | * amdgpu_uvd_ring_parse_cs - UVD command submission parser | |
1069 | * | |
1070 | * @parser: Command submission parser context | |
cdc7893f CK |
1071 | * @job: the job to parse |
1072 | * @ib: the IB to patch | |
d38ceaf9 AD |
1073 | * |
1074 | * Parse the command stream, patch in addresses as necessary. | |
1075 | */ | |
cdc7893f CK |
1076 | int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, |
1077 | struct amdgpu_job *job, | |
1078 | struct amdgpu_ib *ib) | |
d38ceaf9 AD |
1079 | { |
1080 | struct amdgpu_uvd_cs_ctx ctx = {}; | |
f10984a3 | 1081 | unsigned int buf_sizes[] = { |
d38ceaf9 | 1082 | [0x00000000] = 2048, |
8c8bac59 BZ |
1083 | [0x00000001] = 0xFFFFFFFF, |
1084 | [0x00000002] = 0xFFFFFFFF, | |
d38ceaf9 | 1085 | [0x00000003] = 2048, |
8c8bac59 | 1086 | [0x00000004] = 0xFFFFFFFF, |
d38ceaf9 | 1087 | }; |
d38ceaf9 AD |
1088 | int r; |
1089 | ||
cdc7893f | 1090 | job->vm = NULL; |
45088efc CK |
1091 | ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); |
1092 | ||
d38ceaf9 AD |
1093 | if (ib->length_dw % 16) { |
1094 | DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", | |
1095 | ib->length_dw); | |
1096 | return -EINVAL; | |
1097 | } | |
1098 | ||
1099 | ctx.parser = parser; | |
1100 | ctx.buf_sizes = buf_sizes; | |
cdc7893f | 1101 | ctx.ib = ib; |
d38ceaf9 | 1102 | |
042eb910 AD |
1103 | /* first round only required on chips without UVD 64 bit address support */ |
1104 | if (!parser->adev->uvd.address_64_bit) { | |
1105 | /* first round, make sure the buffers are actually in the UVD segment */ | |
1106 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); | |
1107 | if (r) | |
1108 | return r; | |
1109 | } | |
d38ceaf9 AD |
1110 | |
1111 | /* second round, patch buffer addresses into the command stream */ | |
1112 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); | |
1113 | if (r) | |
1114 | return r; | |
1115 | ||
1116 | if (!ctx.has_msg_cmd) { | |
1117 | DRM_ERROR("UVD-IBs need a msg command!\n"); | |
1118 | return -EINVAL; | |
1119 | } | |
1120 | ||
d38ceaf9 AD |
1121 | return 0; |
1122 | } | |
1123 | ||
d7af97db | 1124 | static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, |
f54d1867 | 1125 | bool direct, struct dma_fence **fence) |
d38ceaf9 | 1126 | { |
4ab91cfb CK |
1127 | struct amdgpu_device *adev = ring->adev; |
1128 | struct dma_fence *f = NULL; | |
b059cba5 | 1129 | uint32_t offset, data[4]; |
d71518b5 CK |
1130 | struct amdgpu_job *job; |
1131 | struct amdgpu_ib *ib; | |
4ab91cfb | 1132 | uint64_t addr; |
c1aafd63 | 1133 | int i, r; |
d38ceaf9 | 1134 | |
f7d66fb2 CK |
1135 | r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity, |
1136 | AMDGPU_FENCE_OWNER_UNDEFINED, | |
1137 | 64, direct ? AMDGPU_IB_POOL_DIRECT : | |
9ecefb19 | 1138 | AMDGPU_IB_POOL_DELAYED, &job); |
7b5ec431 | 1139 | if (r) |
68331d7c | 1140 | return r; |
d38ceaf9 | 1141 | |
b059cba5 CK |
1142 | if (adev->asic_type >= CHIP_VEGA10) |
1143 | offset = adev->reg_offset[UVD_HWIP][ring->me][1]; | |
1144 | else | |
1145 | offset = UVD_BASE_SI; | |
09bfb891 | 1146 | |
b059cba5 CK |
1147 | data[0] = PACKET0(offset + UVD_GPCOM_VCPU_DATA0, 0); |
1148 | data[1] = PACKET0(offset + UVD_GPCOM_VCPU_DATA1, 0); | |
1149 | data[2] = PACKET0(offset + UVD_GPCOM_VCPU_CMD, 0); | |
1150 | data[3] = PACKET0(offset + UVD_NO_OP, 0); | |
9181dba6 | 1151 | |
d71518b5 | 1152 | ib = &job->ibs[0]; |
d38ceaf9 | 1153 | addr = amdgpu_bo_gpu_offset(bo); |
09bfb891 | 1154 | ib->ptr[0] = data[0]; |
7b5ec431 | 1155 | ib->ptr[1] = addr; |
09bfb891 | 1156 | ib->ptr[2] = data[1]; |
7b5ec431 | 1157 | ib->ptr[3] = addr >> 32; |
09bfb891 | 1158 | ib->ptr[4] = data[2]; |
7b5ec431 | 1159 | ib->ptr[5] = 0; |
c8b4f288 | 1160 | for (i = 6; i < 16; i += 2) { |
09bfb891 | 1161 | ib->ptr[i] = data[3]; |
c8b4f288 AD |
1162 | ib->ptr[i+1] = 0; |
1163 | } | |
7b5ec431 | 1164 | ib->length_dw = 16; |
d38ceaf9 | 1165 | |
d7af97db | 1166 | if (direct) { |
ee913fd9 | 1167 | r = amdgpu_job_submit_direct(job, ring, &f); |
d7af97db CK |
1168 | if (r) |
1169 | goto err_free; | |
d7af97db | 1170 | } else { |
46e0270c CK |
1171 | r = drm_sched_job_add_resv_dependencies(&job->base, |
1172 | bo->tbo.base.resv, | |
1173 | DMA_RESV_USAGE_KERNEL); | |
4ab91cfb CK |
1174 | if (r) |
1175 | goto err_free; | |
1176 | ||
f7d66fb2 | 1177 | f = amdgpu_job_submit(job); |
d7af97db | 1178 | } |
d38ceaf9 | 1179 | |
68331d7c | 1180 | amdgpu_bo_reserve(bo, true); |
4ab91cfb CK |
1181 | amdgpu_bo_fence(bo, f, false); |
1182 | amdgpu_bo_unreserve(bo); | |
d38ceaf9 | 1183 | |
7b5ec431 | 1184 | if (fence) |
f54d1867 | 1185 | *fence = dma_fence_get(f); |
f54d1867 | 1186 | dma_fence_put(f); |
7b5ec431 | 1187 | |
7b5ec431 | 1188 | return 0; |
d71518b5 CK |
1189 | |
1190 | err_free: | |
1191 | amdgpu_job_free(job); | |
d38ceaf9 AD |
1192 | return r; |
1193 | } | |
1194 | ||
1195 | /* multiple fence commands without any stream commands in between can | |
f10984a3 SS |
1196 | * crash the vcpu so just try to emmit a dummy create/destroy msg to |
1197 | * avoid this | |
1198 | */ | |
d38ceaf9 | 1199 | int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, |
f54d1867 | 1200 | struct dma_fence **fence) |
d38ceaf9 AD |
1201 | { |
1202 | struct amdgpu_device *adev = ring->adev; | |
68331d7c | 1203 | struct amdgpu_bo *bo = adev->uvd.ib_bo; |
d38ceaf9 | 1204 | uint32_t *msg; |
68331d7c | 1205 | int i; |
d38ceaf9 | 1206 | |
68331d7c | 1207 | msg = amdgpu_bo_kptr(bo); |
d38ceaf9 AD |
1208 | /* stitch together an UVD create msg */ |
1209 | msg[0] = cpu_to_le32(0x00000de4); | |
1210 | msg[1] = cpu_to_le32(0x00000000); | |
1211 | msg[2] = cpu_to_le32(handle); | |
1212 | msg[3] = cpu_to_le32(0x00000000); | |
1213 | msg[4] = cpu_to_le32(0x00000000); | |
1214 | msg[5] = cpu_to_le32(0x00000000); | |
1215 | msg[6] = cpu_to_le32(0x00000000); | |
1216 | msg[7] = cpu_to_le32(0x00000780); | |
1217 | msg[8] = cpu_to_le32(0x00000440); | |
1218 | msg[9] = cpu_to_le32(0x00000000); | |
1219 | msg[10] = cpu_to_le32(0x01b37000); | |
1220 | for (i = 11; i < 1024; ++i) | |
1221 | msg[i] = cpu_to_le32(0x0); | |
1222 | ||
d7af97db | 1223 | return amdgpu_uvd_send_msg(ring, bo, true, fence); |
68331d7c | 1224 | |
d38ceaf9 AD |
1225 | } |
1226 | ||
1227 | int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, | |
f54d1867 | 1228 | bool direct, struct dma_fence **fence) |
d38ceaf9 AD |
1229 | { |
1230 | struct amdgpu_device *adev = ring->adev; | |
4ab91cfb | 1231 | struct amdgpu_bo *bo = NULL; |
d38ceaf9 AD |
1232 | uint32_t *msg; |
1233 | int r, i; | |
1234 | ||
68331d7c | 1235 | if (direct) { |
1236 | bo = adev->uvd.ib_bo; | |
1237 | } else { | |
1238 | r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo); | |
1239 | if (r) | |
1240 | return r; | |
1241 | } | |
d38ceaf9 | 1242 | |
68331d7c | 1243 | msg = amdgpu_bo_kptr(bo); |
d38ceaf9 AD |
1244 | /* stitch together an UVD destroy msg */ |
1245 | msg[0] = cpu_to_le32(0x00000de4); | |
1246 | msg[1] = cpu_to_le32(0x00000002); | |
1247 | msg[2] = cpu_to_le32(handle); | |
1248 | msg[3] = cpu_to_le32(0x00000000); | |
1249 | for (i = 4; i < 1024; ++i) | |
1250 | msg[i] = cpu_to_le32(0x0); | |
1251 | ||
68331d7c | 1252 | r = amdgpu_uvd_send_msg(ring, bo, direct, fence); |
1253 | ||
1254 | if (!direct) | |
1255 | amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); | |
1256 | ||
1257 | return r; | |
d38ceaf9 AD |
1258 | } |
1259 | ||
1260 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work) | |
1261 | { | |
1262 | struct amdgpu_device *adev = | |
5c53d19b | 1263 | container_of(work, struct amdgpu_device, uvd.idle_work.work); |
f10984a3 | 1264 | unsigned int fences = 0, i, j; |
6f0fd919 AD |
1265 | |
1266 | for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { | |
f1e582eb AD |
1267 | if (adev->uvd.harvest_config & (1 << i)) |
1268 | continue; | |
6f0fd919 | 1269 | fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); |
f10984a3 | 1270 | for (j = 0; j < adev->uvd.num_enc_rings; ++j) |
4bd2c5dd | 1271 | fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); |
6f0fd919 | 1272 | } |
d38ceaf9 | 1273 | |
713c0021 | 1274 | if (fences == 0) { |
d38ceaf9 AD |
1275 | if (adev->pm.dpm_enabled) { |
1276 | amdgpu_dpm_enable_uvd(adev, false); | |
1277 | } else { | |
1278 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | |
e38ca2b3 | 1279 | /* shutdown the UVD block */ |
2990a1fc AD |
1280 | amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, |
1281 | AMD_PG_STATE_GATE); | |
1282 | amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, | |
1283 | AMD_CG_STATE_GATE); | |
d38ceaf9 AD |
1284 | } |
1285 | } else { | |
5c53d19b | 1286 | schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); |
d38ceaf9 AD |
1287 | } |
1288 | } | |
1289 | ||
c4120d55 | 1290 | void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) |
d38ceaf9 | 1291 | { |
c4120d55 | 1292 | struct amdgpu_device *adev = ring->adev; |
14a8032a | 1293 | bool set_clocks; |
d38ceaf9 | 1294 | |
d9af2259 XY |
1295 | if (amdgpu_sriov_vf(adev)) |
1296 | return; | |
1297 | ||
5c53d19b | 1298 | set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); |
d38ceaf9 AD |
1299 | if (set_clocks) { |
1300 | if (adev->pm.dpm_enabled) { | |
1301 | amdgpu_dpm_enable_uvd(adev, true); | |
1302 | } else { | |
1303 | amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); | |
2990a1fc AD |
1304 | amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, |
1305 | AMD_CG_STATE_UNGATE); | |
1306 | amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, | |
1307 | AMD_PG_STATE_UNGATE); | |
d38ceaf9 AD |
1308 | } |
1309 | } | |
1310 | } | |
c4120d55 CK |
1311 | |
1312 | void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) | |
1313 | { | |
14a8032a | 1314 | if (!amdgpu_sriov_vf(ring->adev)) |
5c53d19b | 1315 | schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); |
c4120d55 | 1316 | } |
8de190c9 CK |
1317 | |
1318 | /** | |
1319 | * amdgpu_uvd_ring_test_ib - test ib execution | |
1320 | * | |
1321 | * @ring: amdgpu_ring pointer | |
ce0e124a | 1322 | * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT |
8de190c9 CK |
1323 | * |
1324 | * Test if we can successfully execute an IB | |
1325 | */ | |
bbec97aa | 1326 | int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
8de190c9 | 1327 | { |
f54d1867 | 1328 | struct dma_fence *fence; |
bbec97aa | 1329 | long r; |
8de190c9 | 1330 | |
0a226780 | 1331 | r = amdgpu_uvd_get_create_msg(ring, 1, &fence); |
98079389 | 1332 | if (r) |
8de190c9 | 1333 | goto error; |
8de190c9 | 1334 | |
0a226780 | 1335 | r = dma_fence_wait_timeout(fence, false, timeout); |
1336 | dma_fence_put(fence); | |
1337 | if (r == 0) | |
1338 | r = -ETIMEDOUT; | |
1339 | if (r < 0) | |
1340 | goto error; | |
1341 | ||
8de190c9 | 1342 | r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); |
98079389 | 1343 | if (r) |
8de190c9 | 1344 | goto error; |
8de190c9 | 1345 | |
f54d1867 | 1346 | r = dma_fence_wait_timeout(fence, false, timeout); |
98079389 | 1347 | if (r == 0) |
bbec97aa | 1348 | r = -ETIMEDOUT; |
98079389 | 1349 | else if (r > 0) |
bbec97aa | 1350 | r = 0; |
bbec97aa | 1351 | |
f54d1867 | 1352 | dma_fence_put(fence); |
c2a4c5b7 JC |
1353 | |
1354 | error: | |
8de190c9 CK |
1355 | return r; |
1356 | } | |
44879b62 AN |
1357 | |
1358 | /** | |
1359 | * amdgpu_uvd_used_handles - returns used UVD handles | |
1360 | * | |
1361 | * @adev: amdgpu_device pointer | |
1362 | * | |
1363 | * Returns the number of UVD handles in use | |
1364 | */ | |
1365 | uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) | |
1366 | { | |
f10984a3 | 1367 | unsigned int i; |
44879b62 AN |
1368 | uint32_t used_handles = 0; |
1369 | ||
1370 | for (i = 0; i < adev->uvd.max_handles; ++i) { | |
1371 | /* | |
1372 | * Handles can be freed in any order, and not | |
1373 | * necessarily linear. So we need to count | |
1374 | * all non-zero handles. | |
1375 | */ | |
5c675bf2 | 1376 | if (atomic_read(&adev->uvd.handles[i])) |
44879b62 AN |
1377 | used_handles++; |
1378 | } | |
1379 | ||
1380 | return used_handles; | |
1381 | } |