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drm/amdgpu: stop loading firmware with pm.mutex locked
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_uvd.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31#include <linux/firmware.h>
32#include <linux/module.h>
33#include <drm/drmP.h>
34#include <drm/drm.h>
35
36#include "amdgpu.h"
37#include "amdgpu_pm.h"
38#include "amdgpu_uvd.h"
39#include "cikd.h"
40#include "uvd/uvd_4_2_d.h"
41
42/* 1 second timeout */
43#define UVD_IDLE_TIMEOUT_MS 1000
44
45/* Firmware Names */
46#ifdef CONFIG_DRM_AMDGPU_CIK
47#define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
48#define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
49#define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
50#define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
51#define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
52#endif
c65444fe
JZ		 53#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
54#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
d38ceaf9
AD		 55
56/**
57 * amdgpu_uvd_cs_ctx - Command submission parser context
58 *
59 * Used for emulating virtual memory support on UVD 4.2.
60 */
61struct amdgpu_uvd_cs_ctx {
62 struct amdgpu_cs_parser *parser;
63 unsigned reg, count;
64 unsigned data0, data1;
65 unsigned idx;
66 unsigned ib_idx;
67
68 /* does the IB has a msg command */
69 bool has_msg_cmd;
70
71 /* minimum buffer sizes */
72 unsigned *buf_sizes;
73};
74
75#ifdef CONFIG_DRM_AMDGPU_CIK
76MODULE_FIRMWARE(FIRMWARE_BONAIRE);
77MODULE_FIRMWARE(FIRMWARE_KABINI);
78MODULE_FIRMWARE(FIRMWARE_KAVERI);
79MODULE_FIRMWARE(FIRMWARE_HAWAII);
80MODULE_FIRMWARE(FIRMWARE_MULLINS);
81#endif
82MODULE_FIRMWARE(FIRMWARE_TONGA);
83MODULE_FIRMWARE(FIRMWARE_CARRIZO);
84
85static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
86static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
87
88int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
89{
90 unsigned long bo_size;
91 const char *fw_name;
92 const struct common_firmware_header *hdr;
93 unsigned version_major, version_minor, family_id;
94 int i, r;
95
96 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
97
98 switch (adev->asic_type) {
99#ifdef CONFIG_DRM_AMDGPU_CIK
100 case CHIP_BONAIRE:
101 fw_name = FIRMWARE_BONAIRE;
102 break;
103 case CHIP_KABINI:
104 fw_name = FIRMWARE_KABINI;
105 break;
106 case CHIP_KAVERI:
107 fw_name = FIRMWARE_KAVERI;
108 break;
109 case CHIP_HAWAII:
110 fw_name = FIRMWARE_HAWAII;
111 break;
112 case CHIP_MULLINS:
113 fw_name = FIRMWARE_MULLINS;
114 break;
115#endif
116 case CHIP_TONGA:
117 fw_name = FIRMWARE_TONGA;
118 break;
119 case CHIP_CARRIZO:
120 fw_name = FIRMWARE_CARRIZO;
121 break;
122 default:
123 return -EINVAL;
124 }
125
126 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
127 if (r) {
128 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
129 fw_name);
130 return r;
131 }
132
133 r = amdgpu_ucode_validate(adev->uvd.fw);
134 if (r) {
135 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
136 fw_name);
137 release_firmware(adev->uvd.fw);
138 adev->uvd.fw = NULL;
139 return r;
140 }
141
142 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
143 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
144 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
145 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
146 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
147 version_major, version_minor, family_id);
148
149 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
150 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
151 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
152 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->uvd.vcpu_bo);
153 if (r) {
154 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
155 return r;
156 }
157
158 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
159 if (r) {
160 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
161 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
162 return r;
163 }
164
165 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
166 &adev->uvd.gpu_addr);
167 if (r) {
168 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
169 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
170 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
171 return r;
172 }
173
174 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
175 if (r) {
176 dev_err(adev->dev, "(%d) UVD map failed\n", r);
177 return r;
178 }
179
180 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
181
182 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
183 atomic_set(&adev->uvd.handles[i], 0);
184 adev->uvd.filp[i] = NULL;
185 }
186
187 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
5fc3aeeb 188 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
d38ceaf9
AD		 189 adev->uvd.address_64_bit = true;
190
191 return 0;
192}
193
194int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
195{
196 int r;
197
198 if (adev->uvd.vcpu_bo == NULL)
199 return 0;
200
201 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
202 if (!r) {
203 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
204 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
205 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
206 }
207
208 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
209
210 amdgpu_ring_fini(&adev->uvd.ring);
211
212 release_firmware(adev->uvd.fw);
213
214 return 0;
215}
216
217int amdgpu_uvd_suspend(struct amdgpu_device *adev)
218{
219 unsigned size;
220 void *ptr;
221 const struct common_firmware_header *hdr;
222 int i;
223
224 if (adev->uvd.vcpu_bo == NULL)
225 return 0;
226
227 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
228 if (atomic_read(&adev->uvd.handles[i]))
229 break;
230
231 if (i == AMDGPU_MAX_UVD_HANDLES)
232 return 0;
233
234 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
235
236 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
237 size -= le32_to_cpu(hdr->ucode_size_bytes);
238
239 ptr = adev->uvd.cpu_addr;
240 ptr += le32_to_cpu(hdr->ucode_size_bytes);
241
242 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
243 memcpy(adev->uvd.saved_bo, ptr, size);
244
245 return 0;
246}
247
248int amdgpu_uvd_resume(struct amdgpu_device *adev)
249{
250 unsigned size;
251 void *ptr;
252 const struct common_firmware_header *hdr;
253 unsigned offset;
254
255 if (adev->uvd.vcpu_bo == NULL)
256 return -EINVAL;
257
258 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
259 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
260 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
261 (adev->uvd.fw->size) - offset);
262
263 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
264 size -= le32_to_cpu(hdr->ucode_size_bytes);
265 ptr = adev->uvd.cpu_addr;
266 ptr += le32_to_cpu(hdr->ucode_size_bytes);
267
268 if (adev->uvd.saved_bo != NULL) {
269 memcpy(ptr, adev->uvd.saved_bo, size);
270 kfree(adev->uvd.saved_bo);
271 adev->uvd.saved_bo = NULL;
272 } else
273 memset(ptr, 0, size);
274
275 return 0;
276}
277
278void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
279{
280 struct amdgpu_ring *ring = &adev->uvd.ring;
281 int i, r;
282
283 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
284 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
285 if (handle != 0 && adev->uvd.filp[i] == filp) {
286 struct amdgpu_fence *fence;
287
288 amdgpu_uvd_note_usage(adev);
289
290 r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
291 if (r) {
292 DRM_ERROR("Error destroying UVD (%d)!\n", r);
293 continue;
294 }
295
296 amdgpu_fence_wait(fence, false);
297 amdgpu_fence_unref(&fence);
298
299 adev->uvd.filp[i] = NULL;
300 atomic_set(&adev->uvd.handles[i], 0);
301 }
302 }
303}
304
305static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
306{
307 int i;
308 for (i = 0; i < rbo->placement.num_placement; ++i) {
309 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
310 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
311 }
312}
313
314/**
315 * amdgpu_uvd_cs_pass1 - first parsing round
316 *
317 * @ctx: UVD parser context
318 *
319 * Make sure UVD message and feedback buffers are in VRAM and
320 * nobody is violating an 256MB boundary.
321 */
322static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
323{
324 struct amdgpu_bo_va_mapping *mapping;
325 struct amdgpu_bo *bo;
326 uint32_t cmd, lo, hi;
327 uint64_t addr;
328 int r = 0;
329
330 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
331 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
332 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
333
334 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
335 if (mapping == NULL) {
336 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
337 return -EINVAL;
338 }
339
340 if (!ctx->parser->adev->uvd.address_64_bit) {
341 /* check if it's a message or feedback command */
342 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
343 if (cmd == 0x0 || cmd == 0x3) {
344 /* yes, force it into VRAM */
345 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
346 amdgpu_ttm_placement_from_domain(bo, domain);
347 }
348 amdgpu_uvd_force_into_uvd_segment(bo);
349
350 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
351 }
352
353 return r;
354}
355
356/**
357 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
358 *
359 * @msg: pointer to message structure
360 * @buf_sizes: returned buffer sizes
361 *
362 * Peek into the decode message and calculate the necessary buffer sizes.
363 */
364static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
365{
366 unsigned stream_type = msg[4];
367 unsigned width = msg[6];
368 unsigned height = msg[7];
369 unsigned dpb_size = msg[9];
370 unsigned pitch = msg[28];
371 unsigned level = msg[57];
372
373 unsigned width_in_mb = width / 16;
374 unsigned height_in_mb = ALIGN(height / 16, 2);
375 unsigned fs_in_mb = width_in_mb * height_in_mb;
376
377 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
378
379 image_size = width * height;
380 image_size += image_size / 2;
381 image_size = ALIGN(image_size, 1024);
382
383 switch (stream_type) {
384 case 0: /* H264 */
385 case 7: /* H264 Perf */
386 switch(level) {
387 case 30:
388 num_dpb_buffer = 8100 / fs_in_mb;
389 break;
390 case 31:
391 num_dpb_buffer = 18000 / fs_in_mb;
392 break;
393 case 32:
394 num_dpb_buffer = 20480 / fs_in_mb;
395 break;
396 case 41:
397 num_dpb_buffer = 32768 / fs_in_mb;
398 break;
399 case 42:
400 num_dpb_buffer = 34816 / fs_in_mb;
401 break;
402 case 50:
403 num_dpb_buffer = 110400 / fs_in_mb;
404 break;
405 case 51:
406 num_dpb_buffer = 184320 / fs_in_mb;
407 break;
408 default:
409 num_dpb_buffer = 184320 / fs_in_mb;
410 break;
411 }
412 num_dpb_buffer++;
413 if (num_dpb_buffer > 17)
414 num_dpb_buffer = 17;
415
416 /* reference picture buffer */
417 min_dpb_size = image_size * num_dpb_buffer;
418
419 /* macroblock context buffer */
420 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
421
422 /* IT surface buffer */
423 min_dpb_size += width_in_mb * height_in_mb * 32;
424 break;
425
426 case 1: /* VC1 */
427
428 /* reference picture buffer */
429 min_dpb_size = image_size * 3;
430
431 /* CONTEXT_BUFFER */
432 min_dpb_size += width_in_mb * height_in_mb * 128;
433
434 /* IT surface buffer */
435 min_dpb_size += width_in_mb * 64;
436
437 /* DB surface buffer */
438 min_dpb_size += width_in_mb * 128;
439
440 /* BP */
441 tmp = max(width_in_mb, height_in_mb);
442 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
443 break;
444
445 case 3: /* MPEG2 */
446
447 /* reference picture buffer */
448 min_dpb_size = image_size * 3;
449 break;
450
451 case 4: /* MPEG4 */
452
453 /* reference picture buffer */
454 min_dpb_size = image_size * 3;
455
456 /* CM */
457 min_dpb_size += width_in_mb * height_in_mb * 64;
458
459 /* IT surface buffer */
460 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
461 break;
462
463 default:
464 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
465 return -EINVAL;
466 }
467
468 if (width > pitch) {
469 DRM_ERROR("Invalid UVD decoding target pitch!\n");
470 return -EINVAL;
471 }
472
473 if (dpb_size < min_dpb_size) {
474 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
475 dpb_size, min_dpb_size);
476 return -EINVAL;
477 }
478
479 buf_sizes[0x1] = dpb_size;
480 buf_sizes[0x2] = image_size;
481 return 0;
482}
483
484/**
485 * amdgpu_uvd_cs_msg - handle UVD message
486 *
487 * @ctx: UVD parser context
488 * @bo: buffer object containing the message
489 * @offset: offset into the buffer object
490 *
491 * Peek into the UVD message and extract the session id.
492 * Make sure that we don't open up to many sessions.
493 */
494static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
495 struct amdgpu_bo *bo, unsigned offset)
496{
497 struct amdgpu_device *adev = ctx->parser->adev;
498 int32_t *msg, msg_type, handle;
499 struct fence *f;
500 void *ptr;
501
502 int i, r;
503
504 if (offset & 0x3F) {
505 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
506 return -EINVAL;
507 }
508
509 f = reservation_object_get_excl(bo->tbo.resv);
510 if (f) {
511 r = amdgpu_fence_wait((struct amdgpu_fence *)f, false);
512 if (r) {
513 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
514 return r;
515 }
516 }
517
518 r = amdgpu_bo_kmap(bo, &ptr);
519 if (r) {
520 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
521 return r;
522 }
523
524 msg = ptr + offset;
525
526 msg_type = msg[1];
527 handle = msg[2];
528
529 if (handle == 0) {
530 DRM_ERROR("Invalid UVD handle!\n");
531 return -EINVAL;
532 }
533
534 if (msg_type == 1) {
535 /* it's a decode msg, calc buffer sizes */
536 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
537 amdgpu_bo_kunmap(bo);
538 if (r)
539 return r;
540
541 } else if (msg_type == 2) {
542 /* it's a destroy msg, free the handle */
543 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
544 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
545 amdgpu_bo_kunmap(bo);
546 return 0;
547 } else {
548 /* it's a create msg */
549 amdgpu_bo_kunmap(bo);
550
551 if (msg_type != 0) {
552 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
553 return -EINVAL;
554 }
555
556 /* it's a create msg, no special handling needed */
557 }
558
559 /* create or decode, validate the handle */
560 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
561 if (atomic_read(&adev->uvd.handles[i]) == handle)
562 return 0;
563 }
564
565 /* handle not found try to alloc a new one */
566 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
567 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
568 adev->uvd.filp[i] = ctx->parser->filp;
569 return 0;
570 }
571 }
572
573 DRM_ERROR("No more free UVD handles!\n");
574 return -EINVAL;
575}
576
577/**
578 * amdgpu_uvd_cs_pass2 - second parsing round
579 *
580 * @ctx: UVD parser context
581 *
582 * Patch buffer addresses, make sure buffer sizes are correct.
583 */
584static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
585{
586 struct amdgpu_bo_va_mapping *mapping;
587 struct amdgpu_bo *bo;
588 struct amdgpu_ib *ib;
589 uint32_t cmd, lo, hi;
590 uint64_t start, end;
591 uint64_t addr;
592 int r;
593
594 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
595 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
596 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
597
598 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
599 if (mapping == NULL)
600 return -EINVAL;
601
602 start = amdgpu_bo_gpu_offset(bo);
603
604 end = (mapping->it.last + 1 - mapping->it.start);
605 end = end * AMDGPU_GPU_PAGE_SIZE + start;
606
607 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
608 start += addr;
609
610 ib = &ctx->parser->ibs[ctx->ib_idx];
611 ib->ptr[ctx->data0] = start & 0xFFFFFFFF;
612 ib->ptr[ctx->data1] = start >> 32;
613
614 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
615 if (cmd < 0x4) {
616 if ((end - start) < ctx->buf_sizes[cmd]) {
617 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
618 (unsigned)(end - start),
619 ctx->buf_sizes[cmd]);
620 return -EINVAL;
621 }
622
623 } else if ((cmd != 0x100) && (cmd != 0x204)) {
624 DRM_ERROR("invalid UVD command %X!\n", cmd);
625 return -EINVAL;
626 }
627
628 if (!ctx->parser->adev->uvd.address_64_bit) {
629 if ((start >> 28) != ((end - 1) >> 28)) {
630 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
631 start, end);
632 return -EINVAL;
633 }
634
635 if ((cmd == 0 || cmd == 0x3) &&
636 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
637 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
638 start, end);
639 return -EINVAL;
640 }
641 }
642
643 if (cmd == 0) {
644 ctx->has_msg_cmd = true;
645 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
646 if (r)
647 return r;
648 } else if (!ctx->has_msg_cmd) {
649 DRM_ERROR("Message needed before other commands are send!\n");
650 return -EINVAL;
651 }
652
653 return 0;
654}
655
656/**
657 * amdgpu_uvd_cs_reg - parse register writes
658 *
659 * @ctx: UVD parser context
660 * @cb: callback function
661 *
662 * Parse the register writes, call cb on each complete command.
663 */
664static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
665 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
666{
667 struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
668 int i, r;
669
670 ctx->idx++;
671 for (i = 0; i <= ctx->count; ++i) {
672 unsigned reg = ctx->reg + i;
673
674 if (ctx->idx >= ib->length_dw) {
675 DRM_ERROR("Register command after end of CS!\n");
676 return -EINVAL;
677 }
678
679 switch (reg) {
680 case mmUVD_GPCOM_VCPU_DATA0:
681 ctx->data0 = ctx->idx;
682 break;
683 case mmUVD_GPCOM_VCPU_DATA1:
684 ctx->data1 = ctx->idx;
685 break;
686 case mmUVD_GPCOM_VCPU_CMD:
687 r = cb(ctx);
688 if (r)
689 return r;
690 break;
691 case mmUVD_ENGINE_CNTL:
692 break;
693 default:
694 DRM_ERROR("Invalid reg 0x%X!\n", reg);
695 return -EINVAL;
696 }
697 ctx->idx++;
698 }
699 return 0;
700}
701
702/**
703 * amdgpu_uvd_cs_packets - parse UVD packets
704 *
705 * @ctx: UVD parser context
706 * @cb: callback function
707 *
708 * Parse the command stream packets.
709 */
710static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
711 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
712{
713 struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
714 int r;
715
716 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
717 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
718 unsigned type = CP_PACKET_GET_TYPE(cmd);
719 switch (type) {
720 case PACKET_TYPE0:
721 ctx->reg = CP_PACKET0_GET_REG(cmd);
722 ctx->count = CP_PACKET_GET_COUNT(cmd);
723 r = amdgpu_uvd_cs_reg(ctx, cb);
724 if (r)
725 return r;
726 break;
727 case PACKET_TYPE2:
728 ++ctx->idx;
729 break;
730 default:
731 DRM_ERROR("Unknown packet type %d !\n", type);
732 return -EINVAL;
733 }
734 }
735 return 0;
736}
737
738/**
739 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
740 *
741 * @parser: Command submission parser context
742 *
743 * Parse the command stream, patch in addresses as necessary.
744 */
745int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
746{
747 struct amdgpu_uvd_cs_ctx ctx = {};
748 unsigned buf_sizes[] = {
749 [0x00000000] = 2048,
750 [0x00000001] = 32 * 1024 * 1024,
751 [0x00000002] = 2048 * 1152 * 3,
752 [0x00000003] = 2048,
753 };
754 struct amdgpu_ib *ib = &parser->ibs[ib_idx];
755 int r;
756
757 if (ib->length_dw % 16) {
758 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
759 ib->length_dw);
760 return -EINVAL;
761 }
762
763 ctx.parser = parser;
764 ctx.buf_sizes = buf_sizes;
765 ctx.ib_idx = ib_idx;
766
767 /* first round, make sure the buffers are actually in the UVD segment */
768 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
769 if (r)
770 return r;
771
772 /* second round, patch buffer addresses into the command stream */
773 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
774 if (r)
775 return r;
776
777 if (!ctx.has_msg_cmd) {
778 DRM_ERROR("UVD-IBs need a msg command!\n");
779 return -EINVAL;
780 }
781
782 amdgpu_uvd_note_usage(ctx.parser->adev);
783
784 return 0;
785}
786
787static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
788 struct amdgpu_bo *bo,
789 struct amdgpu_fence **fence)
790{
791 struct ttm_validate_buffer tv;
792 struct ww_acquire_ctx ticket;
793 struct list_head head;
794 struct amdgpu_ib ib;
795 uint64_t addr;
796 int i, r;
797
798 memset(&tv, 0, sizeof(tv));
799 tv.bo = &bo->tbo;
800
801 INIT_LIST_HEAD(&head);
802 list_add(&tv.head, &head);
803
804 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
805 if (r)
806 return r;
807
808 if (!bo->adev->uvd.address_64_bit) {
809 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
810 amdgpu_uvd_force_into_uvd_segment(bo);
811 }
812
813 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
814 if (r)
815 goto err;
816
817 r = amdgpu_ib_get(ring, NULL, 64, &ib);
818 if (r)
819 goto err;
820
821 addr = amdgpu_bo_gpu_offset(bo);
822 ib.ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
823 ib.ptr[1] = addr;
824 ib.ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
825 ib.ptr[3] = addr >> 32;
826 ib.ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
827 ib.ptr[5] = 0;
828 for (i = 6; i < 16; ++i)
829 ib.ptr[i] = PACKET2(0);
830 ib.length_dw = 16;
831
832 r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
833 if (r)
834 goto err;
835 ttm_eu_fence_buffer_objects(&ticket, &head, &ib.fence->base);
836
837 if (fence)
838 *fence = amdgpu_fence_ref(ib.fence);
839
840 amdgpu_ib_free(ring->adev, &ib);
841 amdgpu_bo_unref(&bo);
842 return 0;
843
844err:
845 ttm_eu_backoff_reservation(&ticket, &head);
846 return r;
847}
848
849/* multiple fence commands without any stream commands in between can
850 crash the vcpu so just try to emmit a dummy create/destroy msg to
851 avoid this */
852int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
853 struct amdgpu_fence **fence)
854{
855 struct amdgpu_device *adev = ring->adev;
856 struct amdgpu_bo *bo;
857 uint32_t *msg;
858 int r, i;
859
860 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
861 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
862 if (r)
863 return r;
864
865 r = amdgpu_bo_reserve(bo, false);
866 if (r) {
867 amdgpu_bo_unref(&bo);
868 return r;
869 }
870
871 r = amdgpu_bo_kmap(bo, (void **)&msg);
872 if (r) {
873 amdgpu_bo_unreserve(bo);
874 amdgpu_bo_unref(&bo);
875 return r;
876 }
877
878 /* stitch together an UVD create msg */
879 msg[0] = cpu_to_le32(0x00000de4);
880 msg[1] = cpu_to_le32(0x00000000);
881 msg[2] = cpu_to_le32(handle);
882 msg[3] = cpu_to_le32(0x00000000);
883 msg[4] = cpu_to_le32(0x00000000);
884 msg[5] = cpu_to_le32(0x00000000);
885 msg[6] = cpu_to_le32(0x00000000);
886 msg[7] = cpu_to_le32(0x00000780);
887 msg[8] = cpu_to_le32(0x00000440);
888 msg[9] = cpu_to_le32(0x00000000);
889 msg[10] = cpu_to_le32(0x01b37000);
890 for (i = 11; i < 1024; ++i)
891 msg[i] = cpu_to_le32(0x0);
892
893 amdgpu_bo_kunmap(bo);
894 amdgpu_bo_unreserve(bo);
895
896 return amdgpu_uvd_send_msg(ring, bo, fence);
897}
898
899int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
900 struct amdgpu_fence **fence)
901{
902 struct amdgpu_device *adev = ring->adev;
903 struct amdgpu_bo *bo;
904 uint32_t *msg;
905 int r, i;
906
907 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
908 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
909 if (r)
910 return r;
911
912 r = amdgpu_bo_reserve(bo, false);
913 if (r) {
914 amdgpu_bo_unref(&bo);
915 return r;
916 }
917
918 r = amdgpu_bo_kmap(bo, (void **)&msg);
919 if (r) {
920 amdgpu_bo_unreserve(bo);
921 amdgpu_bo_unref(&bo);
922 return r;
923 }
924
925 /* stitch together an UVD destroy msg */
926 msg[0] = cpu_to_le32(0x00000de4);
927 msg[1] = cpu_to_le32(0x00000002);
928 msg[2] = cpu_to_le32(handle);
929 msg[3] = cpu_to_le32(0x00000000);
930 for (i = 4; i < 1024; ++i)
931 msg[i] = cpu_to_le32(0x0);
932
933 amdgpu_bo_kunmap(bo);
934 amdgpu_bo_unreserve(bo);
935
936 return amdgpu_uvd_send_msg(ring, bo, fence);
937}
938
939static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
940{
941 struct amdgpu_device *adev =
942 container_of(work, struct amdgpu_device, uvd.idle_work.work);
943 unsigned i, fences, handles = 0;
944
945 fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
946
947 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
948 if (atomic_read(&adev->uvd.handles[i]))
949 ++handles;
950
951 if (fences == 0 && handles == 0) {
952 if (adev->pm.dpm_enabled) {
953 amdgpu_dpm_enable_uvd(adev, false);
954 } else {
955 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
956 }
957 } else {
958 schedule_delayed_work(&adev->uvd.idle_work,
959 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
960 }
961}
962
963static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
964{
965 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
966 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
967 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
968
969 if (set_clocks) {
970 if (adev->pm.dpm_enabled) {
971 amdgpu_dpm_enable_uvd(adev, true);
972 } else {
973 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
974 }
975 }
976}
Linux 6.x block layer and io_uring tree(s)