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drm/amdgpu: add AMDGPU_BO_INVALID_OFFSET
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
a693e050 37#include <ttm/ttm_memory.h>
d38ceaf9
AD		 38#include <drm/drmP.h>
39#include <drm/amdgpu_drm.h>
40#include <linux/seq_file.h>
41#include <linux/slab.h>
42#include <linux/swiotlb.h>
43#include <linux/swap.h>
44#include <linux/pagemap.h>
45#include <linux/debugfs.h>
46#include "amdgpu.h"
47#include "bif/bif_4_1_d.h"
48
49#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
50
51static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
52static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
53
54static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
55{
56 struct amdgpu_mman *mman;
57 struct amdgpu_device *adev;
58
59 mman = container_of(bdev, struct amdgpu_mman, bdev);
60 adev = container_of(mman, struct amdgpu_device, mman);
61 return adev;
62}
63
64
65/*
66 * Global memory.
67 */
68static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
69{
70 return ttm_mem_global_init(ref->object);
71}
72
73static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
74{
75 ttm_mem_global_release(ref->object);
76}
77
a693e050 78int amdgpu_ttm_global_init(struct amdgpu_device *adev)
d38ceaf9
AD		 79{
80 struct drm_global_reference *global_ref;
703297c1
CK		 81 struct amdgpu_ring *ring;
82 struct amd_sched_rq *rq;
d38ceaf9
AD		 83 int r;
84
85 adev->mman.mem_global_referenced = false;
86 global_ref = &adev->mman.mem_global_ref;
87 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
88 global_ref->size = sizeof(struct ttm_mem_global);
89 global_ref->init = &amdgpu_ttm_mem_global_init;
90 global_ref->release = &amdgpu_ttm_mem_global_release;
91 r = drm_global_item_ref(global_ref);
e9d035ec 92 if (r) {
d38ceaf9
AD		 93 DRM_ERROR("Failed setting up TTM memory accounting "
94 "subsystem.\n");
e9d035ec 95 goto error_mem;
d38ceaf9
AD		 96 }
97
98 adev->mman.bo_global_ref.mem_glob =
99 adev->mman.mem_global_ref.object;
100 global_ref = &adev->mman.bo_global_ref.ref;
101 global_ref->global_type = DRM_GLOBAL_TTM_BO;
102 global_ref->size = sizeof(struct ttm_bo_global);
103 global_ref->init = &ttm_bo_global_init;
104 global_ref->release = &ttm_bo_global_release;
105 r = drm_global_item_ref(global_ref);
e9d035ec 106 if (r) {
d38ceaf9 107 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
e9d035ec 108 goto error_bo;
d38ceaf9
AD		 109 }
110
703297c1
CK		 111 ring = adev->mman.buffer_funcs_ring;
112 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
113 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
114 rq, amdgpu_sched_jobs);
e9d035ec 115 if (r) {
703297c1 116 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
e9d035ec 117 goto error_entity;
703297c1
CK		 118 }
119
d38ceaf9 120 adev->mman.mem_global_referenced = true;
703297c1 121
d38ceaf9 122 return 0;
e9d035ec
HR		 123
124error_entity:
125 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
126error_bo:
127 drm_global_item_unref(&adev->mman.mem_global_ref);
128error_mem:
129 return r;
d38ceaf9
AD		 130}
131
132static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
133{
134 if (adev->mman.mem_global_referenced) {
703297c1
CK		 135 amd_sched_entity_fini(adev->mman.entity.sched,
136 &adev->mman.entity);
d38ceaf9
AD		 137 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
138 drm_global_item_unref(&adev->mman.mem_global_ref);
139 adev->mman.mem_global_referenced = false;
140 }
141}
142
143static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
144{
145 return 0;
146}
147
148static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
149 struct ttm_mem_type_manager *man)
150{
151 struct amdgpu_device *adev;
152
153 adev = amdgpu_get_adev(bdev);
154
155 switch (type) {
156 case TTM_PL_SYSTEM:
157 /* System memory */
158 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
159 man->available_caching = TTM_PL_MASK_CACHING;
160 man->default_caching = TTM_PL_FLAG_CACHED;
161 break;
162 case TTM_PL_TT:
163 man->func = &ttm_bo_manager_func;
164 man->gpu_offset = adev->mc.gtt_start;
165 man->available_caching = TTM_PL_MASK_CACHING;
166 man->default_caching = TTM_PL_FLAG_CACHED;
167 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
168 break;
169 case TTM_PL_VRAM:
170 /* "On-card" video ram */
171 man->func = &ttm_bo_manager_func;
172 man->gpu_offset = adev->mc.vram_start;
173 man->flags = TTM_MEMTYPE_FLAG_FIXED |
174 TTM_MEMTYPE_FLAG_MAPPABLE;
175 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
176 man->default_caching = TTM_PL_FLAG_WC;
177 break;
178 case AMDGPU_PL_GDS:
179 case AMDGPU_PL_GWS:
180 case AMDGPU_PL_OA:
181 /* On-chip GDS memory*/
182 man->func = &ttm_bo_manager_func;
183 man->gpu_offset = 0;
184 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
185 man->available_caching = TTM_PL_FLAG_UNCACHED;
186 man->default_caching = TTM_PL_FLAG_UNCACHED;
187 break;
188 default:
189 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
190 return -EINVAL;
191 }
192 return 0;
193}
194
195static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
196 struct ttm_placement *placement)
197{
198 struct amdgpu_bo *rbo;
199 static struct ttm_place placements = {
200 .fpfn = 0,
201 .lpfn = 0,
202 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
203 };
204
205 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
206 placement->placement = &placements;
207 placement->busy_placement = &placements;
208 placement->num_placement = 1;
209 placement->num_busy_placement = 1;
210 return;
211 }
212 rbo = container_of(bo, struct amdgpu_bo, tbo);
213 switch (bo->mem.mem_type) {
214 case TTM_PL_VRAM:
215 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
216 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
217 else
218 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
219 break;
220 case TTM_PL_TT:
221 default:
222 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
223 }
224 *placement = rbo->placement;
225}
226
227static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
228{
229 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
230
054892ed
JG		 231 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
232 return -EPERM;
d38ceaf9
AD		 233 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
234}
235
236static void amdgpu_move_null(struct ttm_buffer_object *bo,
237 struct ttm_mem_reg *new_mem)
238{
239 struct ttm_mem_reg *old_mem = &bo->mem;
240
241 BUG_ON(old_mem->mm_node != NULL);
242 *old_mem = *new_mem;
243 new_mem->mm_node = NULL;
244}
245
246static int amdgpu_move_blit(struct ttm_buffer_object *bo,
247 bool evict, bool no_wait_gpu,
248 struct ttm_mem_reg *new_mem,
249 struct ttm_mem_reg *old_mem)
250{
251 struct amdgpu_device *adev;
252 struct amdgpu_ring *ring;
253 uint64_t old_start, new_start;
c7ae72c0 254 struct fence *fence;
d38ceaf9
AD		 255 int r;
256
257 adev = amdgpu_get_adev(bo->bdev);
258 ring = adev->mman.buffer_funcs_ring;
259 old_start = old_mem->start << PAGE_SHIFT;
260 new_start = new_mem->start << PAGE_SHIFT;
261
262 switch (old_mem->mem_type) {
d38ceaf9 263 case TTM_PL_TT:
c855e250
CK		 264 r = amdgpu_ttm_bind(bo->ttm, old_mem);
265 if (r)
266 return r;
267
268 case TTM_PL_VRAM:
27798e07 269 old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
d38ceaf9
AD		 270 break;
271 default:
272 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
273 return -EINVAL;
274 }
275 switch (new_mem->mem_type) {
d38ceaf9 276 case TTM_PL_TT:
c855e250
CK		 277 r = amdgpu_ttm_bind(bo->ttm, new_mem);
278 if (r)
279 return r;
280
281 case TTM_PL_VRAM:
27798e07 282 new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
d38ceaf9
AD		 283 break;
284 default:
285 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
286 return -EINVAL;
287 }
288 if (!ring->ready) {
289 DRM_ERROR("Trying to move memory with ring turned off.\n");
290 return -EINVAL;
291 }
292
293 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
294
295 r = amdgpu_copy_buffer(ring, old_start, new_start,
296 new_mem->num_pages * PAGE_SIZE, /* bytes */
e24db985 297 bo->resv, &fence, false);
ce64bc25
CK		 298 if (r)
299 return r;
300
301 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
c7ae72c0 302 fence_put(fence);
d38ceaf9
AD		 303 return r;
304}
305
306static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
307 bool evict, bool interruptible,
308 bool no_wait_gpu,
309 struct ttm_mem_reg *new_mem)
310{
311 struct amdgpu_device *adev;
312 struct ttm_mem_reg *old_mem = &bo->mem;
313 struct ttm_mem_reg tmp_mem;
314 struct ttm_place placements;
315 struct ttm_placement placement;
316 int r;
317
318 adev = amdgpu_get_adev(bo->bdev);
319 tmp_mem = *new_mem;
320 tmp_mem.mm_node = NULL;
321 placement.num_placement = 1;
322 placement.placement = &placements;
323 placement.num_busy_placement = 1;
324 placement.busy_placement = &placements;
325 placements.fpfn = 0;
326 placements.lpfn = 0;
327 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
328 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
329 interruptible, no_wait_gpu);
330 if (unlikely(r)) {
331 return r;
332 }
333
334 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
335 if (unlikely(r)) {
336 goto out_cleanup;
337 }
338
339 r = ttm_tt_bind(bo->ttm, &tmp_mem);
340 if (unlikely(r)) {
341 goto out_cleanup;
342 }
343 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
344 if (unlikely(r)) {
345 goto out_cleanup;
346 }
4e2f0caa 347 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
d38ceaf9
AD		 348out_cleanup:
349 ttm_bo_mem_put(bo, &tmp_mem);
350 return r;
351}
352
353static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
354 bool evict, bool interruptible,
355 bool no_wait_gpu,
356 struct ttm_mem_reg *new_mem)
357{
358 struct amdgpu_device *adev;
359 struct ttm_mem_reg *old_mem = &bo->mem;
360 struct ttm_mem_reg tmp_mem;
361 struct ttm_placement placement;
362 struct ttm_place placements;
363 int r;
364
365 adev = amdgpu_get_adev(bo->bdev);
366 tmp_mem = *new_mem;
367 tmp_mem.mm_node = NULL;
368 placement.num_placement = 1;
369 placement.placement = &placements;
370 placement.num_busy_placement = 1;
371 placement.busy_placement = &placements;
372 placements.fpfn = 0;
373 placements.lpfn = 0;
374 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
375 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
376 interruptible, no_wait_gpu);
377 if (unlikely(r)) {
378 return r;
379 }
4e2f0caa 380 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
d38ceaf9
AD		 381 if (unlikely(r)) {
382 goto out_cleanup;
383 }
384 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
385 if (unlikely(r)) {
386 goto out_cleanup;
387 }
388out_cleanup:
389 ttm_bo_mem_put(bo, &tmp_mem);
390 return r;
391}
392
393static int amdgpu_bo_move(struct ttm_buffer_object *bo,
394 bool evict, bool interruptible,
395 bool no_wait_gpu,
396 struct ttm_mem_reg *new_mem)
397{
398 struct amdgpu_device *adev;
104ece97 399 struct amdgpu_bo *abo;
d38ceaf9
AD		 400 struct ttm_mem_reg *old_mem = &bo->mem;
401 int r;
402
104ece97
MD		 403 /* Can't move a pinned BO */
404 abo = container_of(bo, struct amdgpu_bo, tbo);
405 if (WARN_ON_ONCE(abo->pin_count > 0))
406 return -EINVAL;
407
d38ceaf9 408 adev = amdgpu_get_adev(bo->bdev);
dbd5ed60
CK		 409
410 /* remember the eviction */
411 if (evict)
412 atomic64_inc(&adev->num_evictions);
413
d38ceaf9
AD		 414 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
415 amdgpu_move_null(bo, new_mem);
416 return 0;
417 }
418 if ((old_mem->mem_type == TTM_PL_TT &&
419 new_mem->mem_type == TTM_PL_SYSTEM) ||
420 (old_mem->mem_type == TTM_PL_SYSTEM &&
421 new_mem->mem_type == TTM_PL_TT)) {
422 /* bind is enough */
423 amdgpu_move_null(bo, new_mem);
424 return 0;
425 }
426 if (adev->mman.buffer_funcs == NULL ||
427 adev->mman.buffer_funcs_ring == NULL ||
428 !adev->mman.buffer_funcs_ring->ready) {
429 /* use memcpy */
430 goto memcpy;
431 }
432
433 if (old_mem->mem_type == TTM_PL_VRAM &&
434 new_mem->mem_type == TTM_PL_SYSTEM) {
435 r = amdgpu_move_vram_ram(bo, evict, interruptible,
436 no_wait_gpu, new_mem);
437 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
438 new_mem->mem_type == TTM_PL_VRAM) {
439 r = amdgpu_move_ram_vram(bo, evict, interruptible,
440 no_wait_gpu, new_mem);
441 } else {
442 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
443 }
444
445 if (r) {
446memcpy:
4499f2ac 447 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
d38ceaf9
AD		 448 if (r) {
449 return r;
450 }
451 }
452
453 /* update statistics */
454 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
455 return 0;
456}
457
458static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
459{
460 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
461 struct amdgpu_device *adev = amdgpu_get_adev(bdev);
462
463 mem->bus.addr = NULL;
464 mem->bus.offset = 0;
465 mem->bus.size = mem->num_pages << PAGE_SHIFT;
466 mem->bus.base = 0;
467 mem->bus.is_iomem = false;
468 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
469 return -EINVAL;
470 switch (mem->mem_type) {
471 case TTM_PL_SYSTEM:
472 /* system memory */
473 return 0;
474 case TTM_PL_TT:
475 break;
476 case TTM_PL_VRAM:
477 mem->bus.offset = mem->start << PAGE_SHIFT;
478 /* check if it's visible */
479 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
480 return -EINVAL;
481 mem->bus.base = adev->mc.aper_base;
482 mem->bus.is_iomem = true;
483#ifdef __alpha__
484 /*
485 * Alpha: use bus.addr to hold the ioremap() return,
486 * so we can modify bus.base below.
487 */
488 if (mem->placement & TTM_PL_FLAG_WC)
489 mem->bus.addr =
490 ioremap_wc(mem->bus.base + mem->bus.offset,
491 mem->bus.size);
492 else
493 mem->bus.addr =
494 ioremap_nocache(mem->bus.base + mem->bus.offset,
495 mem->bus.size);
496
497 /*
498 * Alpha: Use just the bus offset plus
499 * the hose/domain memory base for bus.base.
500 * It then can be used to build PTEs for VRAM
501 * access, as done in ttm_bo_vm_fault().
502 */
503 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
504 adev->ddev->hose->dense_mem_base;
505#endif
506 break;
507 default:
508 return -EINVAL;
509 }
510 return 0;
511}
512
513static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
514{
515}
516
517/*
518 * TTM backend functions.
519 */
637dd3b5
CK		 520struct amdgpu_ttm_gup_task_list {
521 struct list_head list;
522 struct task_struct *task;
523};
524
d38ceaf9 525struct amdgpu_ttm_tt {
637dd3b5
CK		 526 struct ttm_dma_tt ttm;
527 struct amdgpu_device *adev;
528 u64 offset;
529 uint64_t userptr;
530 struct mm_struct *usermm;
531 uint32_t userflags;
532 spinlock_t guptasklock;
533 struct list_head guptasks;
2f568dbd 534 atomic_t mmu_invalidations;
5c1354bd 535 struct list_head list;
d38ceaf9
AD		 536};
537
2f568dbd 538int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
d38ceaf9 539{
d38ceaf9 540 struct amdgpu_ttm_tt *gtt = (void *)ttm;
d38ceaf9 541 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
2f568dbd
CK		 542 unsigned pinned = 0;
543 int r;
d38ceaf9
AD		 544
545 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
2f568dbd 546 /* check that we only use anonymous memory
d38ceaf9
AD		 547 to prevent problems with writeback */
548 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
549 struct vm_area_struct *vma;
550
551 vma = find_vma(gtt->usermm, gtt->userptr);
552 if (!vma || vma->vm_file || vma->vm_end < end)
553 return -EPERM;
554 }
555
556 do {
557 unsigned num_pages = ttm->num_pages - pinned;
558 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
2f568dbd 559 struct page **p = pages + pinned;
637dd3b5
CK		 560 struct amdgpu_ttm_gup_task_list guptask;
561
562 guptask.task = current;
563 spin_lock(&gtt->guptasklock);
564 list_add(&guptask.list, &gtt->guptasks);
565 spin_unlock(&gtt->guptasklock);
d38ceaf9 566
266c73b7 567 r = get_user_pages(userptr, num_pages, write, 0, p, NULL);
637dd3b5
CK		 568
569 spin_lock(&gtt->guptasklock);
570 list_del(&guptask.list);
571 spin_unlock(&gtt->guptasklock);
d38ceaf9 572
d38ceaf9
AD		 573 if (r < 0)
574 goto release_pages;
575
576 pinned += r;
577
578 } while (pinned < ttm->num_pages);
579
2f568dbd
CK		 580 return 0;
581
582release_pages:
583 release_pages(pages, pinned, 0);
584 return r;
585}
586
587/* prepare the sg table with the user pages */
588static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
589{
590 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
591 struct amdgpu_ttm_tt *gtt = (void *)ttm;
592 unsigned nents;
593 int r;
594
595 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
596 enum dma_data_direction direction = write ?
597 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
598
d38ceaf9
AD		 599 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
600 ttm->num_pages << PAGE_SHIFT,
601 GFP_KERNEL);
602 if (r)
603 goto release_sg;
604
605 r = -ENOMEM;
606 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
607 if (nents != ttm->sg->nents)
608 goto release_sg;
609
610 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
611 gtt->ttm.dma_address, ttm->num_pages);
612
613 return 0;
614
615release_sg:
616 kfree(ttm->sg);
d38ceaf9
AD		 617 return r;
618}
619
620static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
621{
622 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
623 struct amdgpu_ttm_tt *gtt = (void *)ttm;
dd08fae1 624 struct sg_page_iter sg_iter;
d38ceaf9
AD		 625
626 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
627 enum dma_data_direction direction = write ?
628 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
629
630 /* double check that we don't free the table twice */
631 if (!ttm->sg->sgl)
632 return;
633
634 /* free the sg table and pages again */
635 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
636
dd08fae1 637 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
638 struct page *page = sg_page_iter_page(&sg_iter);
d38ceaf9
AD		 639 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
640 set_page_dirty(page);
641
642 mark_page_accessed(page);
09cbfeaf 643 put_page(page);
d38ceaf9
AD		 644 }
645
646 sg_free_table(ttm->sg);
647}
648
649static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
650 struct ttm_mem_reg *bo_mem)
651{
652 struct amdgpu_ttm_tt *gtt = (void*)ttm;
d38ceaf9
AD		 653 int r;
654
e2f784fa
CZ		 655 if (gtt->userptr) {
656 r = amdgpu_ttm_tt_pin_userptr(ttm);
657 if (r) {
658 DRM_ERROR("failed to pin userptr\n");
659 return r;
660 }
661 }
71c76a08 662 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
d38ceaf9
AD		 663 if (!ttm->num_pages) {
664 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
665 ttm->num_pages, bo_mem, ttm);
666 }
667
668 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
669 bo_mem->mem_type == AMDGPU_PL_GWS ||
670 bo_mem->mem_type == AMDGPU_PL_OA)
671 return -EINVAL;
672
c855e250
CK		 673 return 0;
674}
675
676bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
677{
678 struct amdgpu_ttm_tt *gtt = (void *)ttm;
679
680 return gtt && !list_empty(&gtt->list);
681}
682
683int amdgpu_ttm_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem)
684{
685 struct amdgpu_ttm_tt *gtt = (void *)ttm;
686 uint32_t flags;
687 int r;
688
689 if (!ttm || amdgpu_ttm_is_bound(ttm))
690 return 0;
691
692 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
d38ceaf9
AD		 693 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
694 ttm->pages, gtt->ttm.dma_address, flags);
695
696 if (r) {
71c76a08
CK		 697 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
698 ttm->num_pages, gtt->offset);
d38ceaf9
AD		 699 return r;
700 }
5c1354bd
CZ		 701 spin_lock(&gtt->adev->gtt_list_lock);
702 list_add_tail(&gtt->list, &gtt->adev->gtt_list);
703 spin_unlock(&gtt->adev->gtt_list_lock);
d38ceaf9
AD		 704 return 0;
705}
706
2c0d7318
CZ		 707int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
708{
709 struct amdgpu_ttm_tt *gtt, *tmp;
710 struct ttm_mem_reg bo_mem;
711 uint32_t flags;
712 int r;
713
714 bo_mem.mem_type = TTM_PL_TT;
715 spin_lock(&adev->gtt_list_lock);
716 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
717 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
718 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
719 gtt->ttm.ttm.pages, gtt->ttm.dma_address,
720 flags);
721 if (r) {
722 spin_unlock(&adev->gtt_list_lock);
71c76a08
CK		 723 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
724 gtt->ttm.ttm.num_pages, gtt->offset);
2c0d7318
CZ		 725 return r;
726 }
727 }
728 spin_unlock(&adev->gtt_list_lock);
729 return 0;
730}
731
d38ceaf9
AD		 732static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
733{
734 struct amdgpu_ttm_tt *gtt = (void *)ttm;
735
736 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
737 if (gtt->adev->gart.ready)
738 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
739
740 if (gtt->userptr)
741 amdgpu_ttm_tt_unpin_userptr(ttm);
742
5c1354bd
CZ		 743 spin_lock(&gtt->adev->gtt_list_lock);
744 list_del_init(&gtt->list);
745 spin_unlock(&gtt->adev->gtt_list_lock);
746
d38ceaf9
AD		 747 return 0;
748}
749
750static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
751{
752 struct amdgpu_ttm_tt *gtt = (void *)ttm;
753
754 ttm_dma_tt_fini(&gtt->ttm);
755 kfree(gtt);
756}
757
758static struct ttm_backend_func amdgpu_backend_func = {
759 .bind = &amdgpu_ttm_backend_bind,
760 .unbind = &amdgpu_ttm_backend_unbind,
761 .destroy = &amdgpu_ttm_backend_destroy,
762};
763
764static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
765 unsigned long size, uint32_t page_flags,
766 struct page *dummy_read_page)
767{
768 struct amdgpu_device *adev;
769 struct amdgpu_ttm_tt *gtt;
770
771 adev = amdgpu_get_adev(bdev);
772
773 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
774 if (gtt == NULL) {
775 return NULL;
776 }
777 gtt->ttm.ttm.func = &amdgpu_backend_func;
778 gtt->adev = adev;
779 if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
780 kfree(gtt);
781 return NULL;
782 }
5c1354bd 783 INIT_LIST_HEAD(&gtt->list);
d38ceaf9
AD		 784 return &gtt->ttm.ttm;
785}
786
787static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
788{
789 struct amdgpu_device *adev;
790 struct amdgpu_ttm_tt *gtt = (void *)ttm;
791 unsigned i;
792 int r;
793 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
794
795 if (ttm->state != tt_unpopulated)
796 return 0;
797
798 if (gtt && gtt->userptr) {
5f0b34cc 799 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
d38ceaf9
AD		 800 if (!ttm->sg)
801 return -ENOMEM;
802
803 ttm->page_flags |= TTM_PAGE_FLAG_SG;
804 ttm->state = tt_unbound;
805 return 0;
806 }
807
808 if (slave && ttm->sg) {
809 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
810 gtt->ttm.dma_address, ttm->num_pages);
811 ttm->state = tt_unbound;
812 return 0;
813 }
814
815 adev = amdgpu_get_adev(ttm->bdev);
816
817#ifdef CONFIG_SWIOTLB
818 if (swiotlb_nr_tbl()) {
819 return ttm_dma_populate(&gtt->ttm, adev->dev);
820 }
821#endif
822
823 r = ttm_pool_populate(ttm);
824 if (r) {
825 return r;
826 }
827
828 for (i = 0; i < ttm->num_pages; i++) {
829 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
830 0, PAGE_SIZE,
831 PCI_DMA_BIDIRECTIONAL);
832 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
09ccbb74 833 while (i--) {
d38ceaf9
AD		 834 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
835 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
836 gtt->ttm.dma_address[i] = 0;
837 }
838 ttm_pool_unpopulate(ttm);
839 return -EFAULT;
840 }
841 }
842 return 0;
843}
844
845static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
846{
847 struct amdgpu_device *adev;
848 struct amdgpu_ttm_tt *gtt = (void *)ttm;
849 unsigned i;
850 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
851
852 if (gtt && gtt->userptr) {
853 kfree(ttm->sg);
854 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
855 return;
856 }
857
858 if (slave)
859 return;
860
861 adev = amdgpu_get_adev(ttm->bdev);
862
863#ifdef CONFIG_SWIOTLB
864 if (swiotlb_nr_tbl()) {
865 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
866 return;
867 }
868#endif
869
870 for (i = 0; i < ttm->num_pages; i++) {
871 if (gtt->ttm.dma_address[i]) {
872 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
873 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
874 }
875 }
876
877 ttm_pool_unpopulate(ttm);
878}
879
880int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
881 uint32_t flags)
882{
883 struct amdgpu_ttm_tt *gtt = (void *)ttm;
884
885 if (gtt == NULL)
886 return -EINVAL;
887
888 gtt->userptr = addr;
889 gtt->usermm = current->mm;
890 gtt->userflags = flags;
637dd3b5
CK		 891 spin_lock_init(&gtt->guptasklock);
892 INIT_LIST_HEAD(&gtt->guptasks);
2f568dbd 893 atomic_set(&gtt->mmu_invalidations, 0);
637dd3b5 894
d38ceaf9
AD		 895 return 0;
896}
897
cc325d19 898struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
d38ceaf9
AD		 899{
900 struct amdgpu_ttm_tt *gtt = (void *)ttm;
901
902 if (gtt == NULL)
cc325d19 903 return NULL;
d38ceaf9 904
cc325d19 905 return gtt->usermm;
d38ceaf9
AD		 906}
907
cc1de6e8
CK		 908bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
909 unsigned long end)
910{
911 struct amdgpu_ttm_tt *gtt = (void *)ttm;
637dd3b5 912 struct amdgpu_ttm_gup_task_list *entry;
cc1de6e8
CK		 913 unsigned long size;
914
637dd3b5 915 if (gtt == NULL || !gtt->userptr)
cc1de6e8
CK		 916 return false;
917
918 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
919 if (gtt->userptr > end || gtt->userptr + size <= start)
920 return false;
921
637dd3b5
CK		 922 spin_lock(&gtt->guptasklock);
923 list_for_each_entry(entry, &gtt->guptasks, list) {
924 if (entry->task == current) {
925 spin_unlock(&gtt->guptasklock);
926 return false;
927 }
928 }
929 spin_unlock(&gtt->guptasklock);
930
2f568dbd
CK		 931 atomic_inc(&gtt->mmu_invalidations);
932
cc1de6e8
CK		 933 return true;
934}
935
2f568dbd
CK		 936bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
937 int *last_invalidated)
938{
939 struct amdgpu_ttm_tt *gtt = (void *)ttm;
940 int prev_invalidated = *last_invalidated;
941
942 *last_invalidated = atomic_read(&gtt->mmu_invalidations);
943 return prev_invalidated != *last_invalidated;
944}
945
d38ceaf9
AD		 946bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
947{
948 struct amdgpu_ttm_tt *gtt = (void *)ttm;
949
950 if (gtt == NULL)
951 return false;
952
953 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
954}
955
956uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
957 struct ttm_mem_reg *mem)
958{
959 uint32_t flags = 0;
960
961 if (mem && mem->mem_type != TTM_PL_SYSTEM)
962 flags |= AMDGPU_PTE_VALID;
963
6d99905a 964 if (mem && mem->mem_type == TTM_PL_TT) {
d38ceaf9
AD		 965 flags |= AMDGPU_PTE_SYSTEM;
966
6d99905a
CK		 967 if (ttm->caching_state == tt_cached)
968 flags |= AMDGPU_PTE_SNOOPED;
969 }
d38ceaf9 970
8f3c1629 971 if (adev->asic_type >= CHIP_TONGA)
d38ceaf9
AD		 972 flags |= AMDGPU_PTE_EXECUTABLE;
973
974 flags |= AMDGPU_PTE_READABLE;
975
976 if (!amdgpu_ttm_tt_is_readonly(ttm))
977 flags |= AMDGPU_PTE_WRITEABLE;
978
979 return flags;
980}
981
29b3259a
CK		 982static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
983{
984 struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
985 unsigned i, j;
986
987 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
988 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
989
990 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
991 if (&tbo->lru == lru->lru[j])
992 lru->lru[j] = tbo->lru.prev;
993
994 if (&tbo->swap == lru->swap_lru)
995 lru->swap_lru = tbo->swap.prev;
996 }
997}
998
999static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
1000{
1001 struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1002 unsigned log2_size = min(ilog2(tbo->num_pages),
1003 AMDGPU_TTM_LRU_SIZE - 1);
1004
1005 return &adev->mman.log2_size[log2_size];
1006}
1007
1008static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1009{
1010 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1011 struct list_head *res = lru->lru[tbo->mem.mem_type];
1012
1013 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1fdc0b76
CK		 1014 while ((++lru)->lru[tbo->mem.mem_type] == res)
1015 lru->lru[tbo->mem.mem_type] = &tbo->lru;
29b3259a
CK		 1016
1017 return res;
1018}
1019
1020static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1021{
1022 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1023 struct list_head *res = lru->swap_lru;
1024
1025 lru->swap_lru = &tbo->swap;
1fdc0b76
CK		 1026 while ((++lru)->swap_lru == res)
1027 lru->swap_lru = &tbo->swap;
29b3259a
CK		 1028
1029 return res;
1030}
1031
d38ceaf9
AD		 1032static struct ttm_bo_driver amdgpu_bo_driver = {
1033 .ttm_tt_create = &amdgpu_ttm_tt_create,
1034 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1035 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1036 .invalidate_caches = &amdgpu_invalidate_caches,
1037 .init_mem_type = &amdgpu_init_mem_type,
1038 .evict_flags = &amdgpu_evict_flags,
1039 .move = &amdgpu_bo_move,
1040 .verify_access = &amdgpu_verify_access,
1041 .move_notify = &amdgpu_bo_move_notify,
1042 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1043 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1044 .io_mem_free = &amdgpu_ttm_io_mem_free,
29b3259a
CK		 1045 .lru_removal = &amdgpu_ttm_lru_removal,
1046 .lru_tail = &amdgpu_ttm_lru_tail,
1047 .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
d38ceaf9
AD		 1048};
1049
1050int amdgpu_ttm_init(struct amdgpu_device *adev)
1051{
29b3259a 1052 unsigned i, j;
d38ceaf9
AD		 1053 int r;
1054
d38ceaf9
AD		 1055 /* No others user of address space so set it to 0 */
1056 r = ttm_bo_device_init(&adev->mman.bdev,
1057 adev->mman.bo_global_ref.ref.object,
1058 &amdgpu_bo_driver,
1059 adev->ddev->anon_inode->i_mapping,
1060 DRM_FILE_PAGE_OFFSET,
1061 adev->need_dma32);
1062 if (r) {
1063 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1064 return r;
1065 }
29b3259a
CK		 1066
1067 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1068 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1069
1070 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1071 lru->lru[j] = &adev->mman.bdev.man[j].lru;
1072 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1073 }
1074
1fdc0b76
CK		 1075 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1076 adev->mman.guard.lru[j] = NULL;
1077 adev->mman.guard.swap_lru = NULL;
1078
d38ceaf9
AD		 1079 adev->mman.initialized = true;
1080 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1081 adev->mc.real_vram_size >> PAGE_SHIFT);
1082 if (r) {
1083 DRM_ERROR("Failed initializing VRAM heap.\n");
1084 return r;
1085 }
1086 /* Change the size here instead of the init above so only lpfn is affected */
1087 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1088
1089 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
857d913d
AD		 1090 AMDGPU_GEM_DOMAIN_VRAM,
1091 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b 1092 NULL, NULL, &adev->stollen_vga_memory);
d38ceaf9
AD		 1093 if (r) {
1094 return r;
1095 }
1096 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1097 if (r)
1098 return r;
1099 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1100 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1101 if (r) {
1102 amdgpu_bo_unref(&adev->stollen_vga_memory);
1103 return r;
1104 }
1105 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1106 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1107 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1108 adev->mc.gtt_size >> PAGE_SHIFT);
1109 if (r) {
1110 DRM_ERROR("Failed initializing GTT heap.\n");
1111 return r;
1112 }
1113 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1114 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1115
1116 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1117 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1118 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1119 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1120 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1121 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1122 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1123 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1124 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1125 /* GDS Memory */
1126 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1127 adev->gds.mem.total_size >> PAGE_SHIFT);
1128 if (r) {
1129 DRM_ERROR("Failed initializing GDS heap.\n");
1130 return r;
1131 }
1132
1133 /* GWS */
1134 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1135 adev->gds.gws.total_size >> PAGE_SHIFT);
1136 if (r) {
1137 DRM_ERROR("Failed initializing gws heap.\n");
1138 return r;
1139 }
1140
1141 /* OA */
1142 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1143 adev->gds.oa.total_size >> PAGE_SHIFT);
1144 if (r) {
1145 DRM_ERROR("Failed initializing oa heap.\n");
1146 return r;
1147 }
1148
1149 r = amdgpu_ttm_debugfs_init(adev);
1150 if (r) {
1151 DRM_ERROR("Failed to init debugfs\n");
1152 return r;
1153 }
1154 return 0;
1155}
1156
1157void amdgpu_ttm_fini(struct amdgpu_device *adev)
1158{
1159 int r;
1160
1161 if (!adev->mman.initialized)
1162 return;
1163 amdgpu_ttm_debugfs_fini(adev);
1164 if (adev->stollen_vga_memory) {
1165 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1166 if (r == 0) {
1167 amdgpu_bo_unpin(adev->stollen_vga_memory);
1168 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1169 }
1170 amdgpu_bo_unref(&adev->stollen_vga_memory);
1171 }
1172 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1173 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1174 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1175 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1176 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1177 ttm_bo_device_release(&adev->mman.bdev);
1178 amdgpu_gart_fini(adev);
1179 amdgpu_ttm_global_fini(adev);
1180 adev->mman.initialized = false;
1181 DRM_INFO("amdgpu: ttm finalized\n");
1182}
1183
1184/* this should only be called at bootup or when userspace
1185 * isn't running */
1186void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1187{
1188 struct ttm_mem_type_manager *man;
1189
1190 if (!adev->mman.initialized)
1191 return;
1192
1193 man = &adev->mman.bdev.man[TTM_PL_VRAM];
1194 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1195 man->size = size >> PAGE_SHIFT;
1196}
1197
d38ceaf9
AD		 1198int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1199{
1200 struct drm_file *file_priv;
1201 struct amdgpu_device *adev;
d38ceaf9 1202
e176fe17 1203 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
d38ceaf9 1204 return -EINVAL;
d38ceaf9
AD		 1205
1206 file_priv = filp->private_data;
1207 adev = file_priv->minor->dev->dev_private;
e176fe17 1208 if (adev == NULL)
d38ceaf9 1209 return -EINVAL;
e176fe17
CK		 1210
1211 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
d38ceaf9
AD		 1212}
1213
1214int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1215 uint64_t src_offset,
1216 uint64_t dst_offset,
1217 uint32_t byte_count,
1218 struct reservation_object *resv,
e24db985 1219 struct fence **fence, bool direct_submit)
d38ceaf9
AD		 1220{
1221 struct amdgpu_device *adev = ring->adev;
d71518b5
CK		 1222 struct amdgpu_job *job;
1223
d38ceaf9
AD		 1224 uint32_t max_bytes;
1225 unsigned num_loops, num_dw;
1226 unsigned i;
1227 int r;
1228
d38ceaf9
AD		 1229 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1230 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1231 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1232
c7ae72c0
CZ		 1233 /* for IB padding */
1234 while (num_dw & 0x7)
1235 num_dw++;
1236
d71518b5
CK		 1237 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1238 if (r)
9066b0c3 1239 return r;
c7ae72c0
CZ		 1240
1241 if (resv) {
e86f9cee 1242 r = amdgpu_sync_resv(adev, &job->sync, resv,
c7ae72c0
CZ		 1243 AMDGPU_FENCE_OWNER_UNDEFINED);
1244 if (r) {
1245 DRM_ERROR("sync failed (%d).\n", r);
1246 goto error_free;
1247 }
d38ceaf9 1248 }
d38ceaf9
AD		 1249
1250 for (i = 0; i < num_loops; i++) {
1251 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1252
d71518b5
CK		 1253 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1254 dst_offset, cur_size_in_bytes);
d38ceaf9
AD		 1255
1256 src_offset += cur_size_in_bytes;
1257 dst_offset += cur_size_in_bytes;
1258 byte_count -= cur_size_in_bytes;
1259 }
1260
d71518b5
CK		 1261 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1262 WARN_ON(job->ibs[0].length_dw > num_dw);
e24db985
CZ		 1263 if (direct_submit) {
1264 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1265 NULL, NULL, fence);
1266 job->fence = fence_get(*fence);
1267 if (r)
1268 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1269 amdgpu_job_free(job);
1270 } else {
1271 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1272 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1273 if (r)
1274 goto error_free;
1275 }
d38ceaf9 1276
e24db985 1277 return r;
d71518b5 1278
c7ae72c0 1279error_free:
d71518b5 1280 amdgpu_job_free(job);
c7ae72c0 1281 return r;
d38ceaf9
AD		 1282}
1283
59b4a977
FC		 1284int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1285 uint32_t src_data,
1286 struct reservation_object *resv,
1287 struct fence **fence)
1288{
1289 struct amdgpu_device *adev = bo->adev;
1290 struct amdgpu_job *job;
1291 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1292
1293 uint32_t max_bytes, byte_count;
1294 uint64_t dst_offset;
1295 unsigned int num_loops, num_dw;
1296 unsigned int i;
1297 int r;
1298
1299 byte_count = bo->tbo.num_pages << PAGE_SHIFT;
1300 max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1301 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1302 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1303
1304 /* for IB padding */
1305 while (num_dw & 0x7)
1306 num_dw++;
1307
1308 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1309 if (r)
1310 return r;
1311
1312 if (resv) {
1313 r = amdgpu_sync_resv(adev, &job->sync, resv,
1314 AMDGPU_FENCE_OWNER_UNDEFINED);
1315 if (r) {
1316 DRM_ERROR("sync failed (%d).\n", r);
1317 goto error_free;
1318 }
1319 }
1320
1321 dst_offset = bo->tbo.mem.start << PAGE_SHIFT;
1322 for (i = 0; i < num_loops; i++) {
1323 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1324
1325 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1326 dst_offset, cur_size_in_bytes);
1327
1328 dst_offset += cur_size_in_bytes;
1329 byte_count -= cur_size_in_bytes;
1330 }
1331
1332 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1333 WARN_ON(job->ibs[0].length_dw > num_dw);
1334 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1335 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1336 if (r)
1337 goto error_free;
1338
1339 return 0;
1340
1341error_free:
1342 amdgpu_job_free(job);
1343 return r;
1344}
1345
d38ceaf9
AD		 1346#if defined(CONFIG_DEBUG_FS)
1347
1348static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1349{
1350 struct drm_info_node *node = (struct drm_info_node *)m->private;
1351 unsigned ttm_pl = *(int *)node->info_ent->data;
1352 struct drm_device *dev = node->minor->dev;
1353 struct amdgpu_device *adev = dev->dev_private;
1354 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1355 int ret;
1356 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1357
1358 spin_lock(&glob->lru_lock);
1359 ret = drm_mm_dump_table(m, mm);
1360 spin_unlock(&glob->lru_lock);
a2ef8a97 1361 if (ttm_pl == TTM_PL_VRAM)
e1b35f61 1362 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
a2ef8a97 1363 adev->mman.bdev.man[ttm_pl].size,
e1b35f61
AB		 1364 (u64)atomic64_read(&adev->vram_usage) >> 20,
1365 (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
d38ceaf9
AD		 1366 return ret;
1367}
1368
1369static int ttm_pl_vram = TTM_PL_VRAM;
1370static int ttm_pl_tt = TTM_PL_TT;
1371
06ab6832 1372static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
d38ceaf9
AD		 1373 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1374 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1375 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1376#ifdef CONFIG_SWIOTLB
1377 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1378#endif
1379};
1380
1381static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1382 size_t size, loff_t *pos)
1383{
1384 struct amdgpu_device *adev = f->f_inode->i_private;
1385 ssize_t result = 0;
1386 int r;
1387
1388 if (size & 0x3 || *pos & 0x3)
1389 return -EINVAL;
1390
1391 while (size) {
1392 unsigned long flags;
1393 uint32_t value;
1394
1395 if (*pos >= adev->mc.mc_vram_size)
1396 return result;
1397
1398 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1399 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1400 WREG32(mmMM_INDEX_HI, *pos >> 31);
1401 value = RREG32(mmMM_DATA);
1402 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1403
1404 r = put_user(value, (uint32_t *)buf);
1405 if (r)
1406 return r;
1407
1408 result += 4;
1409 buf += 4;
1410 *pos += 4;
1411 size -= 4;
1412 }
1413
1414 return result;
1415}
1416
1417static const struct file_operations amdgpu_ttm_vram_fops = {
1418 .owner = THIS_MODULE,
1419 .read = amdgpu_ttm_vram_read,
1420 .llseek = default_llseek
1421};
1422
a1d29476
CK		 1423#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1424
d38ceaf9
AD		 1425static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1426 size_t size, loff_t *pos)
1427{
1428 struct amdgpu_device *adev = f->f_inode->i_private;
1429 ssize_t result = 0;
1430 int r;
1431
1432 while (size) {
1433 loff_t p = *pos / PAGE_SIZE;
1434 unsigned off = *pos & ~PAGE_MASK;
1435 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1436 struct page *page;
1437 void *ptr;
1438
1439 if (p >= adev->gart.num_cpu_pages)
1440 return result;
1441
1442 page = adev->gart.pages[p];
1443 if (page) {
1444 ptr = kmap(page);
1445 ptr += off;
1446
1447 r = copy_to_user(buf, ptr, cur_size);
1448 kunmap(adev->gart.pages[p]);
1449 } else
1450 r = clear_user(buf, cur_size);
1451
1452 if (r)
1453 return -EFAULT;
1454
1455 result += cur_size;
1456 buf += cur_size;
1457 *pos += cur_size;
1458 size -= cur_size;
1459 }
1460
1461 return result;
1462}
1463
1464static const struct file_operations amdgpu_ttm_gtt_fops = {
1465 .owner = THIS_MODULE,
1466 .read = amdgpu_ttm_gtt_read,
1467 .llseek = default_llseek
1468};
1469
1470#endif
1471
a1d29476
CK		 1472#endif
1473
d38ceaf9
AD		 1474static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1475{
1476#if defined(CONFIG_DEBUG_FS)
1477 unsigned count;
1478
1479 struct drm_minor *minor = adev->ddev->primary;
1480 struct dentry *ent, *root = minor->debugfs_root;
1481
1482 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1483 adev, &amdgpu_ttm_vram_fops);
1484 if (IS_ERR(ent))
1485 return PTR_ERR(ent);
1486 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1487 adev->mman.vram = ent;
1488
a1d29476 1489#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9
AD		 1490 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1491 adev, &amdgpu_ttm_gtt_fops);
1492 if (IS_ERR(ent))
1493 return PTR_ERR(ent);
1494 i_size_write(ent->d_inode, adev->mc.gtt_size);
1495 adev->mman.gtt = ent;
1496
a1d29476 1497#endif
d38ceaf9
AD		 1498 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1499
1500#ifdef CONFIG_SWIOTLB
1501 if (!swiotlb_nr_tbl())
1502 --count;
1503#endif
1504
1505 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1506#else
1507
1508 return 0;
1509#endif
1510}
1511
1512static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1513{
1514#if defined(CONFIG_DEBUG_FS)
1515
1516 debugfs_remove(adev->mman.vram);
1517 adev->mman.vram = NULL;
1518
a1d29476 1519#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9
AD		 1520 debugfs_remove(adev->mman.gtt);
1521 adev->mman.gtt = NULL;
1522#endif
a1d29476
CK		 1523
1524#endif
d38ceaf9 1525}
a693e050
KW		 1526
1527u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1528{
1529 return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
1530}
Linux 6.x block layer and io_uring tree(s)