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drm/amd/scheduler: Mark amdgpu_sched_ops const
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
37#include <drm/drmP.h>
38#include <drm/amdgpu_drm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swiotlb.h>
42#include <linux/swap.h>
43#include <linux/pagemap.h>
44#include <linux/debugfs.h>
45#include "amdgpu.h"
46#include "bif/bif_4_1_d.h"
47
48#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
51static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
52
53static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
54{
55 struct amdgpu_mman *mman;
56 struct amdgpu_device *adev;
57
58 mman = container_of(bdev, struct amdgpu_mman, bdev);
59 adev = container_of(mman, struct amdgpu_device, mman);
60 return adev;
61}
62
63
64/*
65 * Global memory.
66 */
67static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
68{
69 return ttm_mem_global_init(ref->object);
70}
71
72static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
73{
74 ttm_mem_global_release(ref->object);
75}
76
77static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
78{
79 struct drm_global_reference *global_ref;
703297c1
CK		 80 struct amdgpu_ring *ring;
81 struct amd_sched_rq *rq;
d38ceaf9
AD		 82 int r;
83
84 adev->mman.mem_global_referenced = false;
85 global_ref = &adev->mman.mem_global_ref;
86 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
87 global_ref->size = sizeof(struct ttm_mem_global);
88 global_ref->init = &amdgpu_ttm_mem_global_init;
89 global_ref->release = &amdgpu_ttm_mem_global_release;
90 r = drm_global_item_ref(global_ref);
91 if (r != 0) {
92 DRM_ERROR("Failed setting up TTM memory accounting "
93 "subsystem.\n");
94 return r;
95 }
96
97 adev->mman.bo_global_ref.mem_glob =
98 adev->mman.mem_global_ref.object;
99 global_ref = &adev->mman.bo_global_ref.ref;
100 global_ref->global_type = DRM_GLOBAL_TTM_BO;
101 global_ref->size = sizeof(struct ttm_bo_global);
102 global_ref->init = &ttm_bo_global_init;
103 global_ref->release = &ttm_bo_global_release;
104 r = drm_global_item_ref(global_ref);
105 if (r != 0) {
106 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
107 drm_global_item_unref(&adev->mman.mem_global_ref);
108 return r;
109 }
110
703297c1
CK		 111 ring = adev->mman.buffer_funcs_ring;
112 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
113 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
114 rq, amdgpu_sched_jobs);
115 if (r != 0) {
116 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
117 drm_global_item_unref(&adev->mman.mem_global_ref);
118 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
119 return r;
120 }
121
d38ceaf9 122 adev->mman.mem_global_referenced = true;
703297c1 123
d38ceaf9
AD		 124 return 0;
125}
126
127static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
128{
129 if (adev->mman.mem_global_referenced) {
703297c1
CK		 130 amd_sched_entity_fini(adev->mman.entity.sched,
131 &adev->mman.entity);
d38ceaf9
AD		 132 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
133 drm_global_item_unref(&adev->mman.mem_global_ref);
134 adev->mman.mem_global_referenced = false;
135 }
136}
137
138static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
139{
140 return 0;
141}
142
143static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
144 struct ttm_mem_type_manager *man)
145{
146 struct amdgpu_device *adev;
147
148 adev = amdgpu_get_adev(bdev);
149
150 switch (type) {
151 case TTM_PL_SYSTEM:
152 /* System memory */
153 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
154 man->available_caching = TTM_PL_MASK_CACHING;
155 man->default_caching = TTM_PL_FLAG_CACHED;
156 break;
157 case TTM_PL_TT:
158 man->func = &ttm_bo_manager_func;
159 man->gpu_offset = adev->mc.gtt_start;
160 man->available_caching = TTM_PL_MASK_CACHING;
161 man->default_caching = TTM_PL_FLAG_CACHED;
162 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
163 break;
164 case TTM_PL_VRAM:
165 /* "On-card" video ram */
166 man->func = &ttm_bo_manager_func;
167 man->gpu_offset = adev->mc.vram_start;
168 man->flags = TTM_MEMTYPE_FLAG_FIXED |
169 TTM_MEMTYPE_FLAG_MAPPABLE;
170 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
171 man->default_caching = TTM_PL_FLAG_WC;
172 break;
173 case AMDGPU_PL_GDS:
174 case AMDGPU_PL_GWS:
175 case AMDGPU_PL_OA:
176 /* On-chip GDS memory*/
177 man->func = &ttm_bo_manager_func;
178 man->gpu_offset = 0;
179 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
180 man->available_caching = TTM_PL_FLAG_UNCACHED;
181 man->default_caching = TTM_PL_FLAG_UNCACHED;
182 break;
183 default:
184 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
185 return -EINVAL;
186 }
187 return 0;
188}
189
190static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
191 struct ttm_placement *placement)
192{
193 struct amdgpu_bo *rbo;
194 static struct ttm_place placements = {
195 .fpfn = 0,
196 .lpfn = 0,
197 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
198 };
199
200 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
201 placement->placement = &placements;
202 placement->busy_placement = &placements;
203 placement->num_placement = 1;
204 placement->num_busy_placement = 1;
205 return;
206 }
207 rbo = container_of(bo, struct amdgpu_bo, tbo);
208 switch (bo->mem.mem_type) {
209 case TTM_PL_VRAM:
210 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
211 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
212 else
213 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
214 break;
215 case TTM_PL_TT:
216 default:
217 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
218 }
219 *placement = rbo->placement;
220}
221
222static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
223{
224 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
225
226 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
227}
228
229static void amdgpu_move_null(struct ttm_buffer_object *bo,
230 struct ttm_mem_reg *new_mem)
231{
232 struct ttm_mem_reg *old_mem = &bo->mem;
233
234 BUG_ON(old_mem->mm_node != NULL);
235 *old_mem = *new_mem;
236 new_mem->mm_node = NULL;
237}
238
239static int amdgpu_move_blit(struct ttm_buffer_object *bo,
240 bool evict, bool no_wait_gpu,
241 struct ttm_mem_reg *new_mem,
242 struct ttm_mem_reg *old_mem)
243{
244 struct amdgpu_device *adev;
245 struct amdgpu_ring *ring;
246 uint64_t old_start, new_start;
c7ae72c0 247 struct fence *fence;
d38ceaf9
AD		 248 int r;
249
250 adev = amdgpu_get_adev(bo->bdev);
251 ring = adev->mman.buffer_funcs_ring;
252 old_start = old_mem->start << PAGE_SHIFT;
253 new_start = new_mem->start << PAGE_SHIFT;
254
255 switch (old_mem->mem_type) {
256 case TTM_PL_VRAM:
257 old_start += adev->mc.vram_start;
258 break;
259 case TTM_PL_TT:
260 old_start += adev->mc.gtt_start;
261 break;
262 default:
263 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
264 return -EINVAL;
265 }
266 switch (new_mem->mem_type) {
267 case TTM_PL_VRAM:
268 new_start += adev->mc.vram_start;
269 break;
270 case TTM_PL_TT:
271 new_start += adev->mc.gtt_start;
272 break;
273 default:
274 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
275 return -EINVAL;
276 }
277 if (!ring->ready) {
278 DRM_ERROR("Trying to move memory with ring turned off.\n");
279 return -EINVAL;
280 }
281
282 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
283
284 r = amdgpu_copy_buffer(ring, old_start, new_start,
285 new_mem->num_pages * PAGE_SIZE, /* bytes */
286 bo->resv, &fence);
287 /* FIXME: handle copy error */
c7ae72c0 288 r = ttm_bo_move_accel_cleanup(bo, fence,
d38ceaf9 289 evict, no_wait_gpu, new_mem);
c7ae72c0 290 fence_put(fence);
d38ceaf9
AD		 291 return r;
292}
293
294static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
295 bool evict, bool interruptible,
296 bool no_wait_gpu,
297 struct ttm_mem_reg *new_mem)
298{
299 struct amdgpu_device *adev;
300 struct ttm_mem_reg *old_mem = &bo->mem;
301 struct ttm_mem_reg tmp_mem;
302 struct ttm_place placements;
303 struct ttm_placement placement;
304 int r;
305
306 adev = amdgpu_get_adev(bo->bdev);
307 tmp_mem = *new_mem;
308 tmp_mem.mm_node = NULL;
309 placement.num_placement = 1;
310 placement.placement = &placements;
311 placement.num_busy_placement = 1;
312 placement.busy_placement = &placements;
313 placements.fpfn = 0;
314 placements.lpfn = 0;
315 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
316 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
317 interruptible, no_wait_gpu);
318 if (unlikely(r)) {
319 return r;
320 }
321
322 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
323 if (unlikely(r)) {
324 goto out_cleanup;
325 }
326
327 r = ttm_tt_bind(bo->ttm, &tmp_mem);
328 if (unlikely(r)) {
329 goto out_cleanup;
330 }
331 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
332 if (unlikely(r)) {
333 goto out_cleanup;
334 }
335 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
336out_cleanup:
337 ttm_bo_mem_put(bo, &tmp_mem);
338 return r;
339}
340
341static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
342 bool evict, bool interruptible,
343 bool no_wait_gpu,
344 struct ttm_mem_reg *new_mem)
345{
346 struct amdgpu_device *adev;
347 struct ttm_mem_reg *old_mem = &bo->mem;
348 struct ttm_mem_reg tmp_mem;
349 struct ttm_placement placement;
350 struct ttm_place placements;
351 int r;
352
353 adev = amdgpu_get_adev(bo->bdev);
354 tmp_mem = *new_mem;
355 tmp_mem.mm_node = NULL;
356 placement.num_placement = 1;
357 placement.placement = &placements;
358 placement.num_busy_placement = 1;
359 placement.busy_placement = &placements;
360 placements.fpfn = 0;
361 placements.lpfn = 0;
362 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
363 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
364 interruptible, no_wait_gpu);
365 if (unlikely(r)) {
366 return r;
367 }
368 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
369 if (unlikely(r)) {
370 goto out_cleanup;
371 }
372 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
373 if (unlikely(r)) {
374 goto out_cleanup;
375 }
376out_cleanup:
377 ttm_bo_mem_put(bo, &tmp_mem);
378 return r;
379}
380
381static int amdgpu_bo_move(struct ttm_buffer_object *bo,
382 bool evict, bool interruptible,
383 bool no_wait_gpu,
384 struct ttm_mem_reg *new_mem)
385{
386 struct amdgpu_device *adev;
104ece97 387 struct amdgpu_bo *abo;
d38ceaf9
AD		 388 struct ttm_mem_reg *old_mem = &bo->mem;
389 int r;
390
104ece97
MD		 391 /* Can't move a pinned BO */
392 abo = container_of(bo, struct amdgpu_bo, tbo);
393 if (WARN_ON_ONCE(abo->pin_count > 0))
394 return -EINVAL;
395
d38ceaf9
AD		 396 adev = amdgpu_get_adev(bo->bdev);
397 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
398 amdgpu_move_null(bo, new_mem);
399 return 0;
400 }
401 if ((old_mem->mem_type == TTM_PL_TT &&
402 new_mem->mem_type == TTM_PL_SYSTEM) ||
403 (old_mem->mem_type == TTM_PL_SYSTEM &&
404 new_mem->mem_type == TTM_PL_TT)) {
405 /* bind is enough */
406 amdgpu_move_null(bo, new_mem);
407 return 0;
408 }
409 if (adev->mman.buffer_funcs == NULL ||
410 adev->mman.buffer_funcs_ring == NULL ||
411 !adev->mman.buffer_funcs_ring->ready) {
412 /* use memcpy */
413 goto memcpy;
414 }
415
416 if (old_mem->mem_type == TTM_PL_VRAM &&
417 new_mem->mem_type == TTM_PL_SYSTEM) {
418 r = amdgpu_move_vram_ram(bo, evict, interruptible,
419 no_wait_gpu, new_mem);
420 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
421 new_mem->mem_type == TTM_PL_VRAM) {
422 r = amdgpu_move_ram_vram(bo, evict, interruptible,
423 no_wait_gpu, new_mem);
424 } else {
425 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
426 }
427
428 if (r) {
429memcpy:
430 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
431 if (r) {
432 return r;
433 }
434 }
435
436 /* update statistics */
437 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
438 return 0;
439}
440
441static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
442{
443 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
444 struct amdgpu_device *adev = amdgpu_get_adev(bdev);
445
446 mem->bus.addr = NULL;
447 mem->bus.offset = 0;
448 mem->bus.size = mem->num_pages << PAGE_SHIFT;
449 mem->bus.base = 0;
450 mem->bus.is_iomem = false;
451 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
452 return -EINVAL;
453 switch (mem->mem_type) {
454 case TTM_PL_SYSTEM:
455 /* system memory */
456 return 0;
457 case TTM_PL_TT:
458 break;
459 case TTM_PL_VRAM:
460 mem->bus.offset = mem->start << PAGE_SHIFT;
461 /* check if it's visible */
462 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
463 return -EINVAL;
464 mem->bus.base = adev->mc.aper_base;
465 mem->bus.is_iomem = true;
466#ifdef __alpha__
467 /*
468 * Alpha: use bus.addr to hold the ioremap() return,
469 * so we can modify bus.base below.
470 */
471 if (mem->placement & TTM_PL_FLAG_WC)
472 mem->bus.addr =
473 ioremap_wc(mem->bus.base + mem->bus.offset,
474 mem->bus.size);
475 else
476 mem->bus.addr =
477 ioremap_nocache(mem->bus.base + mem->bus.offset,
478 mem->bus.size);
479
480 /*
481 * Alpha: Use just the bus offset plus
482 * the hose/domain memory base for bus.base.
483 * It then can be used to build PTEs for VRAM
484 * access, as done in ttm_bo_vm_fault().
485 */
486 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
487 adev->ddev->hose->dense_mem_base;
488#endif
489 break;
490 default:
491 return -EINVAL;
492 }
493 return 0;
494}
495
496static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
497{
498}
499
500/*
501 * TTM backend functions.
502 */
637dd3b5
CK		 503struct amdgpu_ttm_gup_task_list {
504 struct list_head list;
505 struct task_struct *task;
506};
507
d38ceaf9 508struct amdgpu_ttm_tt {
637dd3b5
CK		 509 struct ttm_dma_tt ttm;
510 struct amdgpu_device *adev;
511 u64 offset;
512 uint64_t userptr;
513 struct mm_struct *usermm;
514 uint32_t userflags;
515 spinlock_t guptasklock;
516 struct list_head guptasks;
2f568dbd 517 atomic_t mmu_invalidations;
d38ceaf9
AD		 518};
519
2f568dbd 520int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
d38ceaf9 521{
d38ceaf9 522 struct amdgpu_ttm_tt *gtt = (void *)ttm;
d38ceaf9 523 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
2f568dbd
CK		 524 unsigned pinned = 0;
525 int r;
d38ceaf9
AD		 526
527 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
2f568dbd 528 /* check that we only use anonymous memory
d38ceaf9
AD		 529 to prevent problems with writeback */
530 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
531 struct vm_area_struct *vma;
532
533 vma = find_vma(gtt->usermm, gtt->userptr);
534 if (!vma || vma->vm_file || vma->vm_end < end)
535 return -EPERM;
536 }
537
538 do {
539 unsigned num_pages = ttm->num_pages - pinned;
540 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
2f568dbd 541 struct page **p = pages + pinned;
637dd3b5
CK		 542 struct amdgpu_ttm_gup_task_list guptask;
543
544 guptask.task = current;
545 spin_lock(&gtt->guptasklock);
546 list_add(&guptask.list, &gtt->guptasks);
547 spin_unlock(&gtt->guptasklock);
d38ceaf9 548
266c73b7 549 r = get_user_pages(userptr, num_pages, write, 0, p, NULL);
637dd3b5
CK		 550
551 spin_lock(&gtt->guptasklock);
552 list_del(&guptask.list);
553 spin_unlock(&gtt->guptasklock);
d38ceaf9 554
d38ceaf9
AD		 555 if (r < 0)
556 goto release_pages;
557
558 pinned += r;
559
560 } while (pinned < ttm->num_pages);
561
2f568dbd
CK		 562 return 0;
563
564release_pages:
565 release_pages(pages, pinned, 0);
566 return r;
567}
568
569/* prepare the sg table with the user pages */
570static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
571{
572 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
573 struct amdgpu_ttm_tt *gtt = (void *)ttm;
574 unsigned nents;
575 int r;
576
577 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
578 enum dma_data_direction direction = write ?
579 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
580
d38ceaf9
AD		 581 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
582 ttm->num_pages << PAGE_SHIFT,
583 GFP_KERNEL);
584 if (r)
585 goto release_sg;
586
587 r = -ENOMEM;
588 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
589 if (nents != ttm->sg->nents)
590 goto release_sg;
591
592 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
593 gtt->ttm.dma_address, ttm->num_pages);
594
595 return 0;
596
597release_sg:
598 kfree(ttm->sg);
d38ceaf9
AD		 599 return r;
600}
601
602static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
603{
604 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
605 struct amdgpu_ttm_tt *gtt = (void *)ttm;
dd08fae1 606 struct sg_page_iter sg_iter;
d38ceaf9
AD		 607
608 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
609 enum dma_data_direction direction = write ?
610 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
611
612 /* double check that we don't free the table twice */
613 if (!ttm->sg->sgl)
614 return;
615
616 /* free the sg table and pages again */
617 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
618
dd08fae1 619 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
620 struct page *page = sg_page_iter_page(&sg_iter);
d38ceaf9
AD		 621 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
622 set_page_dirty(page);
623
624 mark_page_accessed(page);
09cbfeaf 625 put_page(page);
d38ceaf9
AD		 626 }
627
628 sg_free_table(ttm->sg);
629}
630
631static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
632 struct ttm_mem_reg *bo_mem)
633{
634 struct amdgpu_ttm_tt *gtt = (void*)ttm;
635 uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
636 int r;
637
e2f784fa
CZ		 638 if (gtt->userptr) {
639 r = amdgpu_ttm_tt_pin_userptr(ttm);
640 if (r) {
641 DRM_ERROR("failed to pin userptr\n");
642 return r;
643 }
644 }
d38ceaf9
AD		 645 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
646 if (!ttm->num_pages) {
647 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
648 ttm->num_pages, bo_mem, ttm);
649 }
650
651 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
652 bo_mem->mem_type == AMDGPU_PL_GWS ||
653 bo_mem->mem_type == AMDGPU_PL_OA)
654 return -EINVAL;
655
656 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
657 ttm->pages, gtt->ttm.dma_address, flags);
658
659 if (r) {
660 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
661 ttm->num_pages, (unsigned)gtt->offset);
662 return r;
663 }
664 return 0;
665}
666
667static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
668{
669 struct amdgpu_ttm_tt *gtt = (void *)ttm;
670
671 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
672 if (gtt->adev->gart.ready)
673 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
674
675 if (gtt->userptr)
676 amdgpu_ttm_tt_unpin_userptr(ttm);
677
678 return 0;
679}
680
681static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
682{
683 struct amdgpu_ttm_tt *gtt = (void *)ttm;
684
685 ttm_dma_tt_fini(&gtt->ttm);
686 kfree(gtt);
687}
688
689static struct ttm_backend_func amdgpu_backend_func = {
690 .bind = &amdgpu_ttm_backend_bind,
691 .unbind = &amdgpu_ttm_backend_unbind,
692 .destroy = &amdgpu_ttm_backend_destroy,
693};
694
695static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
696 unsigned long size, uint32_t page_flags,
697 struct page *dummy_read_page)
698{
699 struct amdgpu_device *adev;
700 struct amdgpu_ttm_tt *gtt;
701
702 adev = amdgpu_get_adev(bdev);
703
704 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
705 if (gtt == NULL) {
706 return NULL;
707 }
708 gtt->ttm.ttm.func = &amdgpu_backend_func;
709 gtt->adev = adev;
710 if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
711 kfree(gtt);
712 return NULL;
713 }
714 return &gtt->ttm.ttm;
715}
716
717static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
718{
719 struct amdgpu_device *adev;
720 struct amdgpu_ttm_tt *gtt = (void *)ttm;
721 unsigned i;
722 int r;
723 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
724
725 if (ttm->state != tt_unpopulated)
726 return 0;
727
728 if (gtt && gtt->userptr) {
5f0b34cc 729 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
d38ceaf9
AD		 730 if (!ttm->sg)
731 return -ENOMEM;
732
733 ttm->page_flags |= TTM_PAGE_FLAG_SG;
734 ttm->state = tt_unbound;
735 return 0;
736 }
737
738 if (slave && ttm->sg) {
739 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
740 gtt->ttm.dma_address, ttm->num_pages);
741 ttm->state = tt_unbound;
742 return 0;
743 }
744
745 adev = amdgpu_get_adev(ttm->bdev);
746
747#ifdef CONFIG_SWIOTLB
748 if (swiotlb_nr_tbl()) {
749 return ttm_dma_populate(&gtt->ttm, adev->dev);
750 }
751#endif
752
753 r = ttm_pool_populate(ttm);
754 if (r) {
755 return r;
756 }
757
758 for (i = 0; i < ttm->num_pages; i++) {
759 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
760 0, PAGE_SIZE,
761 PCI_DMA_BIDIRECTIONAL);
762 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
09ccbb74 763 while (i--) {
d38ceaf9
AD		 764 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
765 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
766 gtt->ttm.dma_address[i] = 0;
767 }
768 ttm_pool_unpopulate(ttm);
769 return -EFAULT;
770 }
771 }
772 return 0;
773}
774
775static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
776{
777 struct amdgpu_device *adev;
778 struct amdgpu_ttm_tt *gtt = (void *)ttm;
779 unsigned i;
780 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
781
782 if (gtt && gtt->userptr) {
783 kfree(ttm->sg);
784 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
785 return;
786 }
787
788 if (slave)
789 return;
790
791 adev = amdgpu_get_adev(ttm->bdev);
792
793#ifdef CONFIG_SWIOTLB
794 if (swiotlb_nr_tbl()) {
795 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
796 return;
797 }
798#endif
799
800 for (i = 0; i < ttm->num_pages; i++) {
801 if (gtt->ttm.dma_address[i]) {
802 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
803 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
804 }
805 }
806
807 ttm_pool_unpopulate(ttm);
808}
809
810int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
811 uint32_t flags)
812{
813 struct amdgpu_ttm_tt *gtt = (void *)ttm;
814
815 if (gtt == NULL)
816 return -EINVAL;
817
818 gtt->userptr = addr;
819 gtt->usermm = current->mm;
820 gtt->userflags = flags;
637dd3b5
CK		 821 spin_lock_init(&gtt->guptasklock);
822 INIT_LIST_HEAD(&gtt->guptasks);
2f568dbd 823 atomic_set(&gtt->mmu_invalidations, 0);
637dd3b5 824
d38ceaf9
AD		 825 return 0;
826}
827
cc325d19 828struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
d38ceaf9
AD		 829{
830 struct amdgpu_ttm_tt *gtt = (void *)ttm;
831
832 if (gtt == NULL)
cc325d19 833 return NULL;
d38ceaf9 834
cc325d19 835 return gtt->usermm;
d38ceaf9
AD		 836}
837
cc1de6e8
CK		 838bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
839 unsigned long end)
840{
841 struct amdgpu_ttm_tt *gtt = (void *)ttm;
637dd3b5 842 struct amdgpu_ttm_gup_task_list *entry;
cc1de6e8
CK		 843 unsigned long size;
844
637dd3b5 845 if (gtt == NULL || !gtt->userptr)
cc1de6e8
CK		 846 return false;
847
848 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
849 if (gtt->userptr > end || gtt->userptr + size <= start)
850 return false;
851
637dd3b5
CK		 852 spin_lock(&gtt->guptasklock);
853 list_for_each_entry(entry, &gtt->guptasks, list) {
854 if (entry->task == current) {
855 spin_unlock(&gtt->guptasklock);
856 return false;
857 }
858 }
859 spin_unlock(&gtt->guptasklock);
860
2f568dbd
CK		 861 atomic_inc(&gtt->mmu_invalidations);
862
cc1de6e8
CK		 863 return true;
864}
865
2f568dbd
CK		 866bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
867 int *last_invalidated)
868{
869 struct amdgpu_ttm_tt *gtt = (void *)ttm;
870 int prev_invalidated = *last_invalidated;
871
872 *last_invalidated = atomic_read(&gtt->mmu_invalidations);
873 return prev_invalidated != *last_invalidated;
874}
875
d38ceaf9
AD		 876bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
877{
878 struct amdgpu_ttm_tt *gtt = (void *)ttm;
879
880 if (gtt == NULL)
881 return false;
882
883 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
884}
885
886uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
887 struct ttm_mem_reg *mem)
888{
889 uint32_t flags = 0;
890
891 if (mem && mem->mem_type != TTM_PL_SYSTEM)
892 flags |= AMDGPU_PTE_VALID;
893
6d99905a 894 if (mem && mem->mem_type == TTM_PL_TT) {
d38ceaf9
AD		 895 flags |= AMDGPU_PTE_SYSTEM;
896
6d99905a
CK		 897 if (ttm->caching_state == tt_cached)
898 flags |= AMDGPU_PTE_SNOOPED;
899 }
d38ceaf9 900
8f3c1629 901 if (adev->asic_type >= CHIP_TONGA)
d38ceaf9
AD		 902 flags |= AMDGPU_PTE_EXECUTABLE;
903
904 flags |= AMDGPU_PTE_READABLE;
905
906 if (!amdgpu_ttm_tt_is_readonly(ttm))
907 flags |= AMDGPU_PTE_WRITEABLE;
908
909 return flags;
910}
911
912static struct ttm_bo_driver amdgpu_bo_driver = {
913 .ttm_tt_create = &amdgpu_ttm_tt_create,
914 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
915 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
916 .invalidate_caches = &amdgpu_invalidate_caches,
917 .init_mem_type = &amdgpu_init_mem_type,
918 .evict_flags = &amdgpu_evict_flags,
919 .move = &amdgpu_bo_move,
920 .verify_access = &amdgpu_verify_access,
921 .move_notify = &amdgpu_bo_move_notify,
922 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
923 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
924 .io_mem_free = &amdgpu_ttm_io_mem_free,
925};
926
927int amdgpu_ttm_init(struct amdgpu_device *adev)
928{
929 int r;
930
931 r = amdgpu_ttm_global_init(adev);
932 if (r) {
933 return r;
934 }
935 /* No others user of address space so set it to 0 */
936 r = ttm_bo_device_init(&adev->mman.bdev,
937 adev->mman.bo_global_ref.ref.object,
938 &amdgpu_bo_driver,
939 adev->ddev->anon_inode->i_mapping,
940 DRM_FILE_PAGE_OFFSET,
941 adev->need_dma32);
942 if (r) {
943 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
944 return r;
945 }
946 adev->mman.initialized = true;
947 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
948 adev->mc.real_vram_size >> PAGE_SHIFT);
949 if (r) {
950 DRM_ERROR("Failed initializing VRAM heap.\n");
951 return r;
952 }
953 /* Change the size here instead of the init above so only lpfn is affected */
954 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
955
956 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
857d913d
AD		 957 AMDGPU_GEM_DOMAIN_VRAM,
958 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b 959 NULL, NULL, &adev->stollen_vga_memory);
d38ceaf9
AD		 960 if (r) {
961 return r;
962 }
963 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
964 if (r)
965 return r;
966 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
967 amdgpu_bo_unreserve(adev->stollen_vga_memory);
968 if (r) {
969 amdgpu_bo_unref(&adev->stollen_vga_memory);
970 return r;
971 }
972 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
973 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
974 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
975 adev->mc.gtt_size >> PAGE_SHIFT);
976 if (r) {
977 DRM_ERROR("Failed initializing GTT heap.\n");
978 return r;
979 }
980 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
981 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
982
983 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
984 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
985 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
986 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
987 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
988 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
989 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
990 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
991 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
992 /* GDS Memory */
993 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
994 adev->gds.mem.total_size >> PAGE_SHIFT);
995 if (r) {
996 DRM_ERROR("Failed initializing GDS heap.\n");
997 return r;
998 }
999
1000 /* GWS */
1001 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1002 adev->gds.gws.total_size >> PAGE_SHIFT);
1003 if (r) {
1004 DRM_ERROR("Failed initializing gws heap.\n");
1005 return r;
1006 }
1007
1008 /* OA */
1009 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1010 adev->gds.oa.total_size >> PAGE_SHIFT);
1011 if (r) {
1012 DRM_ERROR("Failed initializing oa heap.\n");
1013 return r;
1014 }
1015
1016 r = amdgpu_ttm_debugfs_init(adev);
1017 if (r) {
1018 DRM_ERROR("Failed to init debugfs\n");
1019 return r;
1020 }
1021 return 0;
1022}
1023
1024void amdgpu_ttm_fini(struct amdgpu_device *adev)
1025{
1026 int r;
1027
1028 if (!adev->mman.initialized)
1029 return;
1030 amdgpu_ttm_debugfs_fini(adev);
1031 if (adev->stollen_vga_memory) {
1032 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1033 if (r == 0) {
1034 amdgpu_bo_unpin(adev->stollen_vga_memory);
1035 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1036 }
1037 amdgpu_bo_unref(&adev->stollen_vga_memory);
1038 }
1039 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1040 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1041 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1042 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1043 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1044 ttm_bo_device_release(&adev->mman.bdev);
1045 amdgpu_gart_fini(adev);
1046 amdgpu_ttm_global_fini(adev);
1047 adev->mman.initialized = false;
1048 DRM_INFO("amdgpu: ttm finalized\n");
1049}
1050
1051/* this should only be called at bootup or when userspace
1052 * isn't running */
1053void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1054{
1055 struct ttm_mem_type_manager *man;
1056
1057 if (!adev->mman.initialized)
1058 return;
1059
1060 man = &adev->mman.bdev.man[TTM_PL_VRAM];
1061 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1062 man->size = size >> PAGE_SHIFT;
1063}
1064
d38ceaf9
AD		 1065int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1066{
1067 struct drm_file *file_priv;
1068 struct amdgpu_device *adev;
d38ceaf9 1069
e176fe17 1070 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
d38ceaf9 1071 return -EINVAL;
d38ceaf9
AD		 1072
1073 file_priv = filp->private_data;
1074 adev = file_priv->minor->dev->dev_private;
e176fe17 1075 if (adev == NULL)
d38ceaf9 1076 return -EINVAL;
e176fe17
CK		 1077
1078 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
d38ceaf9
AD		 1079}
1080
1081int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1082 uint64_t src_offset,
1083 uint64_t dst_offset,
1084 uint32_t byte_count,
1085 struct reservation_object *resv,
c7ae72c0 1086 struct fence **fence)
d38ceaf9
AD		 1087{
1088 struct amdgpu_device *adev = ring->adev;
d71518b5
CK		 1089 struct amdgpu_job *job;
1090
d38ceaf9
AD		 1091 uint32_t max_bytes;
1092 unsigned num_loops, num_dw;
1093 unsigned i;
1094 int r;
1095
d38ceaf9
AD		 1096 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1097 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1098 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1099
c7ae72c0
CZ		 1100 /* for IB padding */
1101 while (num_dw & 0x7)
1102 num_dw++;
1103
d71518b5
CK		 1104 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1105 if (r)
9066b0c3 1106 return r;
c7ae72c0
CZ		 1107
1108 if (resv) {
e86f9cee 1109 r = amdgpu_sync_resv(adev, &job->sync, resv,
c7ae72c0
CZ		 1110 AMDGPU_FENCE_OWNER_UNDEFINED);
1111 if (r) {
1112 DRM_ERROR("sync failed (%d).\n", r);
1113 goto error_free;
1114 }
d38ceaf9 1115 }
d38ceaf9
AD		 1116
1117 for (i = 0; i < num_loops; i++) {
1118 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1119
d71518b5
CK		 1120 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1121 dst_offset, cur_size_in_bytes);
d38ceaf9
AD		 1122
1123 src_offset += cur_size_in_bytes;
1124 dst_offset += cur_size_in_bytes;
1125 byte_count -= cur_size_in_bytes;
1126 }
1127
d71518b5
CK		 1128 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1129 WARN_ON(job->ibs[0].length_dw > num_dw);
703297c1
CK		 1130 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1131 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
c7ae72c0
CZ		 1132 if (r)
1133 goto error_free;
d38ceaf9
AD		 1134
1135 return 0;
d71518b5 1136
c7ae72c0 1137error_free:
d71518b5 1138 amdgpu_job_free(job);
c7ae72c0 1139 return r;
d38ceaf9
AD		 1140}
1141
1142#if defined(CONFIG_DEBUG_FS)
1143
1144static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1145{
1146 struct drm_info_node *node = (struct drm_info_node *)m->private;
1147 unsigned ttm_pl = *(int *)node->info_ent->data;
1148 struct drm_device *dev = node->minor->dev;
1149 struct amdgpu_device *adev = dev->dev_private;
1150 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1151 int ret;
1152 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1153
1154 spin_lock(&glob->lru_lock);
1155 ret = drm_mm_dump_table(m, mm);
1156 spin_unlock(&glob->lru_lock);
a2ef8a97 1157 if (ttm_pl == TTM_PL_VRAM)
e1b35f61 1158 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
a2ef8a97 1159 adev->mman.bdev.man[ttm_pl].size,
e1b35f61
AB		 1160 (u64)atomic64_read(&adev->vram_usage) >> 20,
1161 (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
d38ceaf9
AD		 1162 return ret;
1163}
1164
1165static int ttm_pl_vram = TTM_PL_VRAM;
1166static int ttm_pl_tt = TTM_PL_TT;
1167
1168static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1169 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1170 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1171 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1172#ifdef CONFIG_SWIOTLB
1173 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1174#endif
1175};
1176
1177static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1178 size_t size, loff_t *pos)
1179{
1180 struct amdgpu_device *adev = f->f_inode->i_private;
1181 ssize_t result = 0;
1182 int r;
1183
1184 if (size & 0x3 || *pos & 0x3)
1185 return -EINVAL;
1186
1187 while (size) {
1188 unsigned long flags;
1189 uint32_t value;
1190
1191 if (*pos >= adev->mc.mc_vram_size)
1192 return result;
1193
1194 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1195 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1196 WREG32(mmMM_INDEX_HI, *pos >> 31);
1197 value = RREG32(mmMM_DATA);
1198 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1199
1200 r = put_user(value, (uint32_t *)buf);
1201 if (r)
1202 return r;
1203
1204 result += 4;
1205 buf += 4;
1206 *pos += 4;
1207 size -= 4;
1208 }
1209
1210 return result;
1211}
1212
1213static const struct file_operations amdgpu_ttm_vram_fops = {
1214 .owner = THIS_MODULE,
1215 .read = amdgpu_ttm_vram_read,
1216 .llseek = default_llseek
1217};
1218
a1d29476
CK		 1219#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1220
d38ceaf9
AD		 1221static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1222 size_t size, loff_t *pos)
1223{
1224 struct amdgpu_device *adev = f->f_inode->i_private;
1225 ssize_t result = 0;
1226 int r;
1227
1228 while (size) {
1229 loff_t p = *pos / PAGE_SIZE;
1230 unsigned off = *pos & ~PAGE_MASK;
1231 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1232 struct page *page;
1233 void *ptr;
1234
1235 if (p >= adev->gart.num_cpu_pages)
1236 return result;
1237
1238 page = adev->gart.pages[p];
1239 if (page) {
1240 ptr = kmap(page);
1241 ptr += off;
1242
1243 r = copy_to_user(buf, ptr, cur_size);
1244 kunmap(adev->gart.pages[p]);
1245 } else
1246 r = clear_user(buf, cur_size);
1247
1248 if (r)
1249 return -EFAULT;
1250
1251 result += cur_size;
1252 buf += cur_size;
1253 *pos += cur_size;
1254 size -= cur_size;
1255 }
1256
1257 return result;
1258}
1259
1260static const struct file_operations amdgpu_ttm_gtt_fops = {
1261 .owner = THIS_MODULE,
1262 .read = amdgpu_ttm_gtt_read,
1263 .llseek = default_llseek
1264};
1265
1266#endif
1267
a1d29476
CK		 1268#endif
1269
d38ceaf9
AD		 1270static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1271{
1272#if defined(CONFIG_DEBUG_FS)
1273 unsigned count;
1274
1275 struct drm_minor *minor = adev->ddev->primary;
1276 struct dentry *ent, *root = minor->debugfs_root;
1277
1278 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1279 adev, &amdgpu_ttm_vram_fops);
1280 if (IS_ERR(ent))
1281 return PTR_ERR(ent);
1282 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1283 adev->mman.vram = ent;
1284
a1d29476 1285#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9
AD		 1286 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1287 adev, &amdgpu_ttm_gtt_fops);
1288 if (IS_ERR(ent))
1289 return PTR_ERR(ent);
1290 i_size_write(ent->d_inode, adev->mc.gtt_size);
1291 adev->mman.gtt = ent;
1292
a1d29476 1293#endif
d38ceaf9
AD		 1294 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1295
1296#ifdef CONFIG_SWIOTLB
1297 if (!swiotlb_nr_tbl())
1298 --count;
1299#endif
1300
1301 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1302#else
1303
1304 return 0;
1305#endif
1306}
1307
1308static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1309{
1310#if defined(CONFIG_DEBUG_FS)
1311
1312 debugfs_remove(adev->mman.vram);
1313 adev->mman.vram = NULL;
1314
a1d29476 1315#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9
AD		 1316 debugfs_remove(adev->mman.gtt);
1317 adev->mman.gtt = NULL;
1318#endif
a1d29476
CK		 1319
1320#endif
d38ceaf9 1321}
Linux 6.x block layer and io_uring tree(s)