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drm/amd/amdgpu: Various cleanups for DCEv6
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
a693e050 37#include <ttm/ttm_memory.h>
d38ceaf9
AD		 38#include <drm/drmP.h>
39#include <drm/amdgpu_drm.h>
40#include <linux/seq_file.h>
41#include <linux/slab.h>
42#include <linux/swiotlb.h>
43#include <linux/swap.h>
44#include <linux/pagemap.h>
45#include <linux/debugfs.h>
46#include "amdgpu.h"
47#include "bif/bif_4_1_d.h"
48
49#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
50
51static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
52static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
53
54static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
55{
56 struct amdgpu_mman *mman;
57 struct amdgpu_device *adev;
58
59 mman = container_of(bdev, struct amdgpu_mman, bdev);
60 adev = container_of(mman, struct amdgpu_device, mman);
61 return adev;
62}
63
64
65/*
66 * Global memory.
67 */
68static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
69{
70 return ttm_mem_global_init(ref->object);
71}
72
73static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
74{
75 ttm_mem_global_release(ref->object);
76}
77
a693e050 78int amdgpu_ttm_global_init(struct amdgpu_device *adev)
d38ceaf9
AD		 79{
80 struct drm_global_reference *global_ref;
703297c1
CK		 81 struct amdgpu_ring *ring;
82 struct amd_sched_rq *rq;
d38ceaf9
AD		 83 int r;
84
85 adev->mman.mem_global_referenced = false;
86 global_ref = &adev->mman.mem_global_ref;
87 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
88 global_ref->size = sizeof(struct ttm_mem_global);
89 global_ref->init = &amdgpu_ttm_mem_global_init;
90 global_ref->release = &amdgpu_ttm_mem_global_release;
91 r = drm_global_item_ref(global_ref);
e9d035ec 92 if (r) {
d38ceaf9
AD		 93 DRM_ERROR("Failed setting up TTM memory accounting "
94 "subsystem.\n");
e9d035ec 95 goto error_mem;
d38ceaf9
AD		 96 }
97
98 adev->mman.bo_global_ref.mem_glob =
99 adev->mman.mem_global_ref.object;
100 global_ref = &adev->mman.bo_global_ref.ref;
101 global_ref->global_type = DRM_GLOBAL_TTM_BO;
102 global_ref->size = sizeof(struct ttm_bo_global);
103 global_ref->init = &ttm_bo_global_init;
104 global_ref->release = &ttm_bo_global_release;
105 r = drm_global_item_ref(global_ref);
e9d035ec 106 if (r) {
d38ceaf9 107 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
e9d035ec 108 goto error_bo;
d38ceaf9
AD		 109 }
110
703297c1
CK		 111 ring = adev->mman.buffer_funcs_ring;
112 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
113 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
114 rq, amdgpu_sched_jobs);
e9d035ec 115 if (r) {
703297c1 116 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
e9d035ec 117 goto error_entity;
703297c1
CK		 118 }
119
d38ceaf9 120 adev->mman.mem_global_referenced = true;
703297c1 121
d38ceaf9 122 return 0;
e9d035ec
HR		 123
124error_entity:
125 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
126error_bo:
127 drm_global_item_unref(&adev->mman.mem_global_ref);
128error_mem:
129 return r;
d38ceaf9
AD		 130}
131
132static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
133{
134 if (adev->mman.mem_global_referenced) {
703297c1
CK		 135 amd_sched_entity_fini(adev->mman.entity.sched,
136 &adev->mman.entity);
d38ceaf9
AD		 137 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
138 drm_global_item_unref(&adev->mman.mem_global_ref);
139 adev->mman.mem_global_referenced = false;
140 }
141}
142
143static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
144{
145 return 0;
146}
147
148static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
149 struct ttm_mem_type_manager *man)
150{
151 struct amdgpu_device *adev;
152
153 adev = amdgpu_get_adev(bdev);
154
155 switch (type) {
156 case TTM_PL_SYSTEM:
157 /* System memory */
158 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
159 man->available_caching = TTM_PL_MASK_CACHING;
160 man->default_caching = TTM_PL_FLAG_CACHED;
161 break;
162 case TTM_PL_TT:
bb990bb0 163 man->func = &amdgpu_gtt_mgr_func;
d38ceaf9
AD		 164 man->gpu_offset = adev->mc.gtt_start;
165 man->available_caching = TTM_PL_MASK_CACHING;
166 man->default_caching = TTM_PL_FLAG_CACHED;
167 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
168 break;
169 case TTM_PL_VRAM:
170 /* "On-card" video ram */
171 man->func = &ttm_bo_manager_func;
172 man->gpu_offset = adev->mc.vram_start;
173 man->flags = TTM_MEMTYPE_FLAG_FIXED |
174 TTM_MEMTYPE_FLAG_MAPPABLE;
175 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
176 man->default_caching = TTM_PL_FLAG_WC;
177 break;
178 case AMDGPU_PL_GDS:
179 case AMDGPU_PL_GWS:
180 case AMDGPU_PL_OA:
181 /* On-chip GDS memory*/
182 man->func = &ttm_bo_manager_func;
183 man->gpu_offset = 0;
184 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
185 man->available_caching = TTM_PL_FLAG_UNCACHED;
186 man->default_caching = TTM_PL_FLAG_UNCACHED;
187 break;
188 default:
189 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
190 return -EINVAL;
191 }
192 return 0;
193}
194
195static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
196 struct ttm_placement *placement)
197{
765e7fbf 198 struct amdgpu_bo *abo;
d38ceaf9
AD		 199 static struct ttm_place placements = {
200 .fpfn = 0,
201 .lpfn = 0,
202 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
203 };
08291c5c 204 unsigned i;
d38ceaf9
AD		 205
206 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
207 placement->placement = &placements;
208 placement->busy_placement = &placements;
209 placement->num_placement = 1;
210 placement->num_busy_placement = 1;
211 return;
212 }
765e7fbf 213 abo = container_of(bo, struct amdgpu_bo, tbo);
d38ceaf9
AD		 214 switch (bo->mem.mem_type) {
215 case TTM_PL_VRAM:
765e7fbf
CK		 216 if (abo->adev->mman.buffer_funcs_ring->ready == false) {
217 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
08291c5c 218 } else {
765e7fbf
CK		 219 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
220 for (i = 0; i < abo->placement.num_placement; ++i) {
221 if (!(abo->placements[i].flags &
08291c5c
CK		 222 TTM_PL_FLAG_TT))
223 continue;
224
765e7fbf 225 if (abo->placements[i].lpfn)
08291c5c
CK		 226 continue;
227
228 /* set an upper limit to force directly
229 * allocating address space for the BO.
230 */
765e7fbf
CK		 231 abo->placements[i].lpfn =
232 abo->adev->mc.gtt_size >> PAGE_SHIFT;
08291c5c
CK		 233 }
234 }
d38ceaf9
AD		 235 break;
236 case TTM_PL_TT:
237 default:
765e7fbf 238 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
d38ceaf9 239 }
765e7fbf 240 *placement = abo->placement;
d38ceaf9
AD		 241}
242
243static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
244{
765e7fbf 245 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
d38ceaf9 246
054892ed
JG		 247 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
248 return -EPERM;
765e7fbf 249 return drm_vma_node_verify_access(&abo->gem_base.vma_node, filp);
d38ceaf9
AD		 250}
251
252static void amdgpu_move_null(struct ttm_buffer_object *bo,
253 struct ttm_mem_reg *new_mem)
254{
255 struct ttm_mem_reg *old_mem = &bo->mem;
256
257 BUG_ON(old_mem->mm_node != NULL);
258 *old_mem = *new_mem;
259 new_mem->mm_node = NULL;
260}
261
262static int amdgpu_move_blit(struct ttm_buffer_object *bo,
263 bool evict, bool no_wait_gpu,
264 struct ttm_mem_reg *new_mem,
265 struct ttm_mem_reg *old_mem)
266{
267 struct amdgpu_device *adev;
268 struct amdgpu_ring *ring;
269 uint64_t old_start, new_start;
c7ae72c0 270 struct fence *fence;
d38ceaf9
AD		 271 int r;
272
273 adev = amdgpu_get_adev(bo->bdev);
274 ring = adev->mman.buffer_funcs_ring;
d38ceaf9
AD		 275
276 switch (old_mem->mem_type) {
d38ceaf9 277 case TTM_PL_TT:
bb990bb0 278 r = amdgpu_ttm_bind(bo, old_mem);
c855e250
CK		 279 if (r)
280 return r;
281
282 case TTM_PL_VRAM:
ad78069c 283 old_start = (u64)old_mem->start << PAGE_SHIFT;
27798e07 284 old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
d38ceaf9
AD		 285 break;
286 default:
287 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
288 return -EINVAL;
289 }
290 switch (new_mem->mem_type) {
d38ceaf9 291 case TTM_PL_TT:
bb990bb0 292 r = amdgpu_ttm_bind(bo, new_mem);
c855e250
CK		 293 if (r)
294 return r;
295
296 case TTM_PL_VRAM:
ad78069c 297 new_start = (u64)new_mem->start << PAGE_SHIFT;
27798e07 298 new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
d38ceaf9
AD		 299 break;
300 default:
301 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
302 return -EINVAL;
303 }
304 if (!ring->ready) {
305 DRM_ERROR("Trying to move memory with ring turned off.\n");
306 return -EINVAL;
307 }
308
309 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
310
311 r = amdgpu_copy_buffer(ring, old_start, new_start,
312 new_mem->num_pages * PAGE_SIZE, /* bytes */
e24db985 313 bo->resv, &fence, false);
ce64bc25
CK		 314 if (r)
315 return r;
316
317 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
c7ae72c0 318 fence_put(fence);
d38ceaf9
AD		 319 return r;
320}
321
322static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
323 bool evict, bool interruptible,
324 bool no_wait_gpu,
325 struct ttm_mem_reg *new_mem)
326{
327 struct amdgpu_device *adev;
328 struct ttm_mem_reg *old_mem = &bo->mem;
329 struct ttm_mem_reg tmp_mem;
330 struct ttm_place placements;
331 struct ttm_placement placement;
332 int r;
333
334 adev = amdgpu_get_adev(bo->bdev);
335 tmp_mem = *new_mem;
336 tmp_mem.mm_node = NULL;
337 placement.num_placement = 1;
338 placement.placement = &placements;
339 placement.num_busy_placement = 1;
340 placement.busy_placement = &placements;
341 placements.fpfn = 0;
056472f1 342 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
d38ceaf9
AD		 343 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
344 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
345 interruptible, no_wait_gpu);
346 if (unlikely(r)) {
347 return r;
348 }
349
350 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
351 if (unlikely(r)) {
352 goto out_cleanup;
353 }
354
355 r = ttm_tt_bind(bo->ttm, &tmp_mem);
356 if (unlikely(r)) {
357 goto out_cleanup;
358 }
359 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
360 if (unlikely(r)) {
361 goto out_cleanup;
362 }
4e2f0caa 363 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
d38ceaf9
AD		 364out_cleanup:
365 ttm_bo_mem_put(bo, &tmp_mem);
366 return r;
367}
368
369static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
370 bool evict, bool interruptible,
371 bool no_wait_gpu,
372 struct ttm_mem_reg *new_mem)
373{
374 struct amdgpu_device *adev;
375 struct ttm_mem_reg *old_mem = &bo->mem;
376 struct ttm_mem_reg tmp_mem;
377 struct ttm_placement placement;
378 struct ttm_place placements;
379 int r;
380
381 adev = amdgpu_get_adev(bo->bdev);
382 tmp_mem = *new_mem;
383 tmp_mem.mm_node = NULL;
384 placement.num_placement = 1;
385 placement.placement = &placements;
386 placement.num_busy_placement = 1;
387 placement.busy_placement = &placements;
388 placements.fpfn = 0;
056472f1 389 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
d38ceaf9
AD		 390 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
391 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
392 interruptible, no_wait_gpu);
393 if (unlikely(r)) {
394 return r;
395 }
4e2f0caa 396 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
d38ceaf9
AD		 397 if (unlikely(r)) {
398 goto out_cleanup;
399 }
400 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
401 if (unlikely(r)) {
402 goto out_cleanup;
403 }
404out_cleanup:
405 ttm_bo_mem_put(bo, &tmp_mem);
406 return r;
407}
408
409static int amdgpu_bo_move(struct ttm_buffer_object *bo,
410 bool evict, bool interruptible,
411 bool no_wait_gpu,
412 struct ttm_mem_reg *new_mem)
413{
414 struct amdgpu_device *adev;
104ece97 415 struct amdgpu_bo *abo;
d38ceaf9
AD		 416 struct ttm_mem_reg *old_mem = &bo->mem;
417 int r;
418
104ece97
MD		 419 /* Can't move a pinned BO */
420 abo = container_of(bo, struct amdgpu_bo, tbo);
421 if (WARN_ON_ONCE(abo->pin_count > 0))
422 return -EINVAL;
423
d38ceaf9 424 adev = amdgpu_get_adev(bo->bdev);
dbd5ed60
CK		 425
426 /* remember the eviction */
427 if (evict)
428 atomic64_inc(&adev->num_evictions);
429
d38ceaf9
AD		 430 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
431 amdgpu_move_null(bo, new_mem);
432 return 0;
433 }
434 if ((old_mem->mem_type == TTM_PL_TT &&
435 new_mem->mem_type == TTM_PL_SYSTEM) ||
436 (old_mem->mem_type == TTM_PL_SYSTEM &&
437 new_mem->mem_type == TTM_PL_TT)) {
438 /* bind is enough */
439 amdgpu_move_null(bo, new_mem);
440 return 0;
441 }
442 if (adev->mman.buffer_funcs == NULL ||
443 adev->mman.buffer_funcs_ring == NULL ||
444 !adev->mman.buffer_funcs_ring->ready) {
445 /* use memcpy */
446 goto memcpy;
447 }
448
449 if (old_mem->mem_type == TTM_PL_VRAM &&
450 new_mem->mem_type == TTM_PL_SYSTEM) {
451 r = amdgpu_move_vram_ram(bo, evict, interruptible,
452 no_wait_gpu, new_mem);
453 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
454 new_mem->mem_type == TTM_PL_VRAM) {
455 r = amdgpu_move_ram_vram(bo, evict, interruptible,
456 no_wait_gpu, new_mem);
457 } else {
458 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
459 }
460
461 if (r) {
462memcpy:
4499f2ac 463 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
d38ceaf9
AD		 464 if (r) {
465 return r;
466 }
467 }
468
469 /* update statistics */
470 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
471 return 0;
472}
473
474static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
475{
476 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
477 struct amdgpu_device *adev = amdgpu_get_adev(bdev);
478
479 mem->bus.addr = NULL;
480 mem->bus.offset = 0;
481 mem->bus.size = mem->num_pages << PAGE_SHIFT;
482 mem->bus.base = 0;
483 mem->bus.is_iomem = false;
484 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
485 return -EINVAL;
486 switch (mem->mem_type) {
487 case TTM_PL_SYSTEM:
488 /* system memory */
489 return 0;
490 case TTM_PL_TT:
491 break;
492 case TTM_PL_VRAM:
493 mem->bus.offset = mem->start << PAGE_SHIFT;
494 /* check if it's visible */
495 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
496 return -EINVAL;
497 mem->bus.base = adev->mc.aper_base;
498 mem->bus.is_iomem = true;
499#ifdef __alpha__
500 /*
501 * Alpha: use bus.addr to hold the ioremap() return,
502 * so we can modify bus.base below.
503 */
504 if (mem->placement & TTM_PL_FLAG_WC)
505 mem->bus.addr =
506 ioremap_wc(mem->bus.base + mem->bus.offset,
507 mem->bus.size);
508 else
509 mem->bus.addr =
510 ioremap_nocache(mem->bus.base + mem->bus.offset,
511 mem->bus.size);
512
513 /*
514 * Alpha: Use just the bus offset plus
515 * the hose/domain memory base for bus.base.
516 * It then can be used to build PTEs for VRAM
517 * access, as done in ttm_bo_vm_fault().
518 */
519 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
520 adev->ddev->hose->dense_mem_base;
521#endif
522 break;
523 default:
524 return -EINVAL;
525 }
526 return 0;
527}
528
529static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
530{
531}
532
533/*
534 * TTM backend functions.
535 */
637dd3b5
CK		 536struct amdgpu_ttm_gup_task_list {
537 struct list_head list;
538 struct task_struct *task;
539};
540
d38ceaf9 541struct amdgpu_ttm_tt {
637dd3b5
CK		 542 struct ttm_dma_tt ttm;
543 struct amdgpu_device *adev;
544 u64 offset;
545 uint64_t userptr;
546 struct mm_struct *usermm;
547 uint32_t userflags;
548 spinlock_t guptasklock;
549 struct list_head guptasks;
2f568dbd 550 atomic_t mmu_invalidations;
5c1354bd 551 struct list_head list;
d38ceaf9
AD		 552};
553
2f568dbd 554int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
d38ceaf9 555{
d38ceaf9 556 struct amdgpu_ttm_tt *gtt = (void *)ttm;
d38ceaf9 557 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
2f568dbd
CK		 558 unsigned pinned = 0;
559 int r;
d38ceaf9
AD		 560
561 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
2f568dbd 562 /* check that we only use anonymous memory
d38ceaf9
AD		 563 to prevent problems with writeback */
564 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
565 struct vm_area_struct *vma;
566
567 vma = find_vma(gtt->usermm, gtt->userptr);
568 if (!vma || vma->vm_file || vma->vm_end < end)
569 return -EPERM;
570 }
571
572 do {
573 unsigned num_pages = ttm->num_pages - pinned;
574 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
2f568dbd 575 struct page **p = pages + pinned;
637dd3b5
CK		 576 struct amdgpu_ttm_gup_task_list guptask;
577
578 guptask.task = current;
579 spin_lock(&gtt->guptasklock);
580 list_add(&guptask.list, &gtt->guptasks);
581 spin_unlock(&gtt->guptasklock);
d38ceaf9 582
266c73b7 583 r = get_user_pages(userptr, num_pages, write, 0, p, NULL);
637dd3b5
CK		 584
585 spin_lock(&gtt->guptasklock);
586 list_del(&guptask.list);
587 spin_unlock(&gtt->guptasklock);
d38ceaf9 588
d38ceaf9
AD		 589 if (r < 0)
590 goto release_pages;
591
592 pinned += r;
593
594 } while (pinned < ttm->num_pages);
595
2f568dbd
CK		 596 return 0;
597
598release_pages:
599 release_pages(pages, pinned, 0);
600 return r;
601}
602
603/* prepare the sg table with the user pages */
604static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
605{
606 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
607 struct amdgpu_ttm_tt *gtt = (void *)ttm;
608 unsigned nents;
609 int r;
610
611 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
612 enum dma_data_direction direction = write ?
613 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
614
d38ceaf9
AD		 615 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
616 ttm->num_pages << PAGE_SHIFT,
617 GFP_KERNEL);
618 if (r)
619 goto release_sg;
620
621 r = -ENOMEM;
622 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
623 if (nents != ttm->sg->nents)
624 goto release_sg;
625
626 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
627 gtt->ttm.dma_address, ttm->num_pages);
628
629 return 0;
630
631release_sg:
632 kfree(ttm->sg);
d38ceaf9
AD		 633 return r;
634}
635
636static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
637{
638 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
639 struct amdgpu_ttm_tt *gtt = (void *)ttm;
dd08fae1 640 struct sg_page_iter sg_iter;
d38ceaf9
AD		 641
642 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
643 enum dma_data_direction direction = write ?
644 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
645
646 /* double check that we don't free the table twice */
647 if (!ttm->sg->sgl)
648 return;
649
650 /* free the sg table and pages again */
651 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
652
dd08fae1 653 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
654 struct page *page = sg_page_iter_page(&sg_iter);
d38ceaf9
AD		 655 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
656 set_page_dirty(page);
657
658 mark_page_accessed(page);
09cbfeaf 659 put_page(page);
d38ceaf9
AD		 660 }
661
662 sg_free_table(ttm->sg);
663}
664
665static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
666 struct ttm_mem_reg *bo_mem)
667{
668 struct amdgpu_ttm_tt *gtt = (void*)ttm;
d38ceaf9
AD		 669 int r;
670
e2f784fa
CZ		 671 if (gtt->userptr) {
672 r = amdgpu_ttm_tt_pin_userptr(ttm);
673 if (r) {
674 DRM_ERROR("failed to pin userptr\n");
675 return r;
676 }
677 }
d38ceaf9
AD		 678 if (!ttm->num_pages) {
679 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
680 ttm->num_pages, bo_mem, ttm);
681 }
682
683 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
684 bo_mem->mem_type == AMDGPU_PL_GWS ||
685 bo_mem->mem_type == AMDGPU_PL_OA)
686 return -EINVAL;
687
c855e250
CK		 688 return 0;
689}
690
691bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
692{
693 struct amdgpu_ttm_tt *gtt = (void *)ttm;
694
695 return gtt && !list_empty(&gtt->list);
696}
697
bb990bb0 698int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
c855e250 699{
bb990bb0
CK		 700 struct ttm_tt *ttm = bo->ttm;
701 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
c855e250
CK		 702 uint32_t flags;
703 int r;
704
705 if (!ttm || amdgpu_ttm_is_bound(ttm))
706 return 0;
707
bb990bb0
CK		 708 r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
709 NULL, bo_mem);
710 if (r) {
711 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
712 return r;
713 }
714
c855e250 715 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
bb990bb0 716 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
d38ceaf9
AD		 717 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
718 ttm->pages, gtt->ttm.dma_address, flags);
719
720 if (r) {
71c76a08
CK		 721 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
722 ttm->num_pages, gtt->offset);
d38ceaf9
AD		 723 return r;
724 }
5c1354bd
CZ		 725 spin_lock(&gtt->adev->gtt_list_lock);
726 list_add_tail(&gtt->list, &gtt->adev->gtt_list);
727 spin_unlock(&gtt->adev->gtt_list_lock);
d38ceaf9
AD		 728 return 0;
729}
730
2c0d7318
CZ		 731int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
732{
733 struct amdgpu_ttm_tt *gtt, *tmp;
734 struct ttm_mem_reg bo_mem;
735 uint32_t flags;
736 int r;
737
738 bo_mem.mem_type = TTM_PL_TT;
739 spin_lock(&adev->gtt_list_lock);
740 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
741 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
742 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
743 gtt->ttm.ttm.pages, gtt->ttm.dma_address,
744 flags);
745 if (r) {
746 spin_unlock(&adev->gtt_list_lock);
71c76a08
CK		 747 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
748 gtt->ttm.ttm.num_pages, gtt->offset);
2c0d7318
CZ		 749 return r;
750 }
751 }
752 spin_unlock(&adev->gtt_list_lock);
753 return 0;
754}
755
d38ceaf9
AD		 756static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
757{
758 struct amdgpu_ttm_tt *gtt = (void *)ttm;
759
78ab0a38
CK		 760 if (!amdgpu_ttm_is_bound(ttm))
761 return 0;
762
d38ceaf9
AD		 763 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
764 if (gtt->adev->gart.ready)
765 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
766
767 if (gtt->userptr)
768 amdgpu_ttm_tt_unpin_userptr(ttm);
769
5c1354bd
CZ		 770 spin_lock(&gtt->adev->gtt_list_lock);
771 list_del_init(&gtt->list);
772 spin_unlock(&gtt->adev->gtt_list_lock);
773
d38ceaf9
AD		 774 return 0;
775}
776
777static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
778{
779 struct amdgpu_ttm_tt *gtt = (void *)ttm;
780
781 ttm_dma_tt_fini(&gtt->ttm);
782 kfree(gtt);
783}
784
785static struct ttm_backend_func amdgpu_backend_func = {
786 .bind = &amdgpu_ttm_backend_bind,
787 .unbind = &amdgpu_ttm_backend_unbind,
788 .destroy = &amdgpu_ttm_backend_destroy,
789};
790
791static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
792 unsigned long size, uint32_t page_flags,
793 struct page *dummy_read_page)
794{
795 struct amdgpu_device *adev;
796 struct amdgpu_ttm_tt *gtt;
797
798 adev = amdgpu_get_adev(bdev);
799
800 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
801 if (gtt == NULL) {
802 return NULL;
803 }
804 gtt->ttm.ttm.func = &amdgpu_backend_func;
805 gtt->adev = adev;
806 if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
807 kfree(gtt);
808 return NULL;
809 }
5c1354bd 810 INIT_LIST_HEAD(&gtt->list);
d38ceaf9
AD		 811 return &gtt->ttm.ttm;
812}
813
814static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
815{
816 struct amdgpu_device *adev;
817 struct amdgpu_ttm_tt *gtt = (void *)ttm;
818 unsigned i;
819 int r;
820 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
821
822 if (ttm->state != tt_unpopulated)
823 return 0;
824
825 if (gtt && gtt->userptr) {
5f0b34cc 826 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
d38ceaf9
AD		 827 if (!ttm->sg)
828 return -ENOMEM;
829
830 ttm->page_flags |= TTM_PAGE_FLAG_SG;
831 ttm->state = tt_unbound;
832 return 0;
833 }
834
835 if (slave && ttm->sg) {
836 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
837 gtt->ttm.dma_address, ttm->num_pages);
838 ttm->state = tt_unbound;
839 return 0;
840 }
841
842 adev = amdgpu_get_adev(ttm->bdev);
843
844#ifdef CONFIG_SWIOTLB
845 if (swiotlb_nr_tbl()) {
846 return ttm_dma_populate(&gtt->ttm, adev->dev);
847 }
848#endif
849
850 r = ttm_pool_populate(ttm);
851 if (r) {
852 return r;
853 }
854
855 for (i = 0; i < ttm->num_pages; i++) {
856 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
857 0, PAGE_SIZE,
858 PCI_DMA_BIDIRECTIONAL);
859 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
09ccbb74 860 while (i--) {
d38ceaf9
AD		 861 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
862 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
863 gtt->ttm.dma_address[i] = 0;
864 }
865 ttm_pool_unpopulate(ttm);
866 return -EFAULT;
867 }
868 }
869 return 0;
870}
871
872static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
873{
874 struct amdgpu_device *adev;
875 struct amdgpu_ttm_tt *gtt = (void *)ttm;
876 unsigned i;
877 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
878
879 if (gtt && gtt->userptr) {
880 kfree(ttm->sg);
881 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
882 return;
883 }
884
885 if (slave)
886 return;
887
888 adev = amdgpu_get_adev(ttm->bdev);
889
890#ifdef CONFIG_SWIOTLB
891 if (swiotlb_nr_tbl()) {
892 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
893 return;
894 }
895#endif
896
897 for (i = 0; i < ttm->num_pages; i++) {
898 if (gtt->ttm.dma_address[i]) {
899 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
900 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
901 }
902 }
903
904 ttm_pool_unpopulate(ttm);
905}
906
907int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
908 uint32_t flags)
909{
910 struct amdgpu_ttm_tt *gtt = (void *)ttm;
911
912 if (gtt == NULL)
913 return -EINVAL;
914
915 gtt->userptr = addr;
916 gtt->usermm = current->mm;
917 gtt->userflags = flags;
637dd3b5
CK		 918 spin_lock_init(&gtt->guptasklock);
919 INIT_LIST_HEAD(&gtt->guptasks);
2f568dbd 920 atomic_set(&gtt->mmu_invalidations, 0);
637dd3b5 921
d38ceaf9
AD		 922 return 0;
923}
924
cc325d19 925struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
d38ceaf9
AD		 926{
927 struct amdgpu_ttm_tt *gtt = (void *)ttm;
928
929 if (gtt == NULL)
cc325d19 930 return NULL;
d38ceaf9 931
cc325d19 932 return gtt->usermm;
d38ceaf9
AD		 933}
934
cc1de6e8
CK		 935bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
936 unsigned long end)
937{
938 struct amdgpu_ttm_tt *gtt = (void *)ttm;
637dd3b5 939 struct amdgpu_ttm_gup_task_list *entry;
cc1de6e8
CK		 940 unsigned long size;
941
637dd3b5 942 if (gtt == NULL || !gtt->userptr)
cc1de6e8
CK		 943 return false;
944
945 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
946 if (gtt->userptr > end || gtt->userptr + size <= start)
947 return false;
948
637dd3b5
CK		 949 spin_lock(&gtt->guptasklock);
950 list_for_each_entry(entry, &gtt->guptasks, list) {
951 if (entry->task == current) {
952 spin_unlock(&gtt->guptasklock);
953 return false;
954 }
955 }
956 spin_unlock(&gtt->guptasklock);
957
2f568dbd
CK		 958 atomic_inc(&gtt->mmu_invalidations);
959
cc1de6e8
CK		 960 return true;
961}
962
2f568dbd
CK		 963bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
964 int *last_invalidated)
965{
966 struct amdgpu_ttm_tt *gtt = (void *)ttm;
967 int prev_invalidated = *last_invalidated;
968
969 *last_invalidated = atomic_read(&gtt->mmu_invalidations);
970 return prev_invalidated != *last_invalidated;
971}
972
d38ceaf9
AD		 973bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
974{
975 struct amdgpu_ttm_tt *gtt = (void *)ttm;
976
977 if (gtt == NULL)
978 return false;
979
980 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
981}
982
983uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
984 struct ttm_mem_reg *mem)
985{
986 uint32_t flags = 0;
987
988 if (mem && mem->mem_type != TTM_PL_SYSTEM)
989 flags |= AMDGPU_PTE_VALID;
990
6d99905a 991 if (mem && mem->mem_type == TTM_PL_TT) {
d38ceaf9
AD		 992 flags |= AMDGPU_PTE_SYSTEM;
993
6d99905a
CK		 994 if (ttm->caching_state == tt_cached)
995 flags |= AMDGPU_PTE_SNOOPED;
996 }
d38ceaf9 997
8f3c1629 998 if (adev->asic_type >= CHIP_TONGA)
d38ceaf9
AD		 999 flags |= AMDGPU_PTE_EXECUTABLE;
1000
1001 flags |= AMDGPU_PTE_READABLE;
1002
1003 if (!amdgpu_ttm_tt_is_readonly(ttm))
1004 flags |= AMDGPU_PTE_WRITEABLE;
1005
1006 return flags;
1007}
1008
29b3259a
CK		 1009static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
1010{
1011 struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1012 unsigned i, j;
1013
1014 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1015 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1016
1017 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1018 if (&tbo->lru == lru->lru[j])
1019 lru->lru[j] = tbo->lru.prev;
1020
1021 if (&tbo->swap == lru->swap_lru)
1022 lru->swap_lru = tbo->swap.prev;
1023 }
1024}
1025
1026static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
1027{
1028 struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1029 unsigned log2_size = min(ilog2(tbo->num_pages),
1030 AMDGPU_TTM_LRU_SIZE - 1);
1031
1032 return &adev->mman.log2_size[log2_size];
1033}
1034
1035static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1036{
1037 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1038 struct list_head *res = lru->lru[tbo->mem.mem_type];
1039
1040 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1fdc0b76
CK		 1041 while ((++lru)->lru[tbo->mem.mem_type] == res)
1042 lru->lru[tbo->mem.mem_type] = &tbo->lru;
29b3259a
CK		 1043
1044 return res;
1045}
1046
1047static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1048{
1049 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1050 struct list_head *res = lru->swap_lru;
1051
1052 lru->swap_lru = &tbo->swap;
1fdc0b76
CK		 1053 while ((++lru)->swap_lru == res)
1054 lru->swap_lru = &tbo->swap;
29b3259a
CK		 1055
1056 return res;
1057}
1058
d38ceaf9
AD		 1059static struct ttm_bo_driver amdgpu_bo_driver = {
1060 .ttm_tt_create = &amdgpu_ttm_tt_create,
1061 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1062 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1063 .invalidate_caches = &amdgpu_invalidate_caches,
1064 .init_mem_type = &amdgpu_init_mem_type,
1065 .evict_flags = &amdgpu_evict_flags,
1066 .move = &amdgpu_bo_move,
1067 .verify_access = &amdgpu_verify_access,
1068 .move_notify = &amdgpu_bo_move_notify,
1069 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1070 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1071 .io_mem_free = &amdgpu_ttm_io_mem_free,
29b3259a
CK		 1072 .lru_removal = &amdgpu_ttm_lru_removal,
1073 .lru_tail = &amdgpu_ttm_lru_tail,
1074 .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
d38ceaf9
AD		 1075};
1076
1077int amdgpu_ttm_init(struct amdgpu_device *adev)
1078{
29b3259a 1079 unsigned i, j;
d38ceaf9
AD		 1080 int r;
1081
d38ceaf9
AD		 1082 /* No others user of address space so set it to 0 */
1083 r = ttm_bo_device_init(&adev->mman.bdev,
1084 adev->mman.bo_global_ref.ref.object,
1085 &amdgpu_bo_driver,
1086 adev->ddev->anon_inode->i_mapping,
1087 DRM_FILE_PAGE_OFFSET,
1088 adev->need_dma32);
1089 if (r) {
1090 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1091 return r;
1092 }
29b3259a
CK		 1093
1094 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1095 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1096
1097 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1098 lru->lru[j] = &adev->mman.bdev.man[j].lru;
1099 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1100 }
1101
1fdc0b76
CK		 1102 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1103 adev->mman.guard.lru[j] = NULL;
1104 adev->mman.guard.swap_lru = NULL;
1105
d38ceaf9
AD		 1106 adev->mman.initialized = true;
1107 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1108 adev->mc.real_vram_size >> PAGE_SHIFT);
1109 if (r) {
1110 DRM_ERROR("Failed initializing VRAM heap.\n");
1111 return r;
1112 }
1113 /* Change the size here instead of the init above so only lpfn is affected */
1114 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1115
1116 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
857d913d
AD		 1117 AMDGPU_GEM_DOMAIN_VRAM,
1118 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b 1119 NULL, NULL, &adev->stollen_vga_memory);
d38ceaf9
AD		 1120 if (r) {
1121 return r;
1122 }
1123 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1124 if (r)
1125 return r;
1126 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1127 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1128 if (r) {
1129 amdgpu_bo_unref(&adev->stollen_vga_memory);
1130 return r;
1131 }
1132 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1133 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1134 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1135 adev->mc.gtt_size >> PAGE_SHIFT);
1136 if (r) {
1137 DRM_ERROR("Failed initializing GTT heap.\n");
1138 return r;
1139 }
1140 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1141 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1142
1143 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1144 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1145 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1146 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1147 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1148 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1149 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1150 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1151 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1152 /* GDS Memory */
1153 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1154 adev->gds.mem.total_size >> PAGE_SHIFT);
1155 if (r) {
1156 DRM_ERROR("Failed initializing GDS heap.\n");
1157 return r;
1158 }
1159
1160 /* GWS */
1161 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1162 adev->gds.gws.total_size >> PAGE_SHIFT);
1163 if (r) {
1164 DRM_ERROR("Failed initializing gws heap.\n");
1165 return r;
1166 }
1167
1168 /* OA */
1169 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1170 adev->gds.oa.total_size >> PAGE_SHIFT);
1171 if (r) {
1172 DRM_ERROR("Failed initializing oa heap.\n");
1173 return r;
1174 }
1175
1176 r = amdgpu_ttm_debugfs_init(adev);
1177 if (r) {
1178 DRM_ERROR("Failed to init debugfs\n");
1179 return r;
1180 }
1181 return 0;
1182}
1183
1184void amdgpu_ttm_fini(struct amdgpu_device *adev)
1185{
1186 int r;
1187
1188 if (!adev->mman.initialized)
1189 return;
1190 amdgpu_ttm_debugfs_fini(adev);
1191 if (adev->stollen_vga_memory) {
1192 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1193 if (r == 0) {
1194 amdgpu_bo_unpin(adev->stollen_vga_memory);
1195 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1196 }
1197 amdgpu_bo_unref(&adev->stollen_vga_memory);
1198 }
1199 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1200 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1201 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1202 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1203 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1204 ttm_bo_device_release(&adev->mman.bdev);
1205 amdgpu_gart_fini(adev);
1206 amdgpu_ttm_global_fini(adev);
1207 adev->mman.initialized = false;
1208 DRM_INFO("amdgpu: ttm finalized\n");
1209}
1210
1211/* this should only be called at bootup or when userspace
1212 * isn't running */
1213void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1214{
1215 struct ttm_mem_type_manager *man;
1216
1217 if (!adev->mman.initialized)
1218 return;
1219
1220 man = &adev->mman.bdev.man[TTM_PL_VRAM];
1221 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1222 man->size = size >> PAGE_SHIFT;
1223}
1224
d38ceaf9
AD		 1225int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1226{
1227 struct drm_file *file_priv;
1228 struct amdgpu_device *adev;
d38ceaf9 1229
e176fe17 1230 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
d38ceaf9 1231 return -EINVAL;
d38ceaf9
AD		 1232
1233 file_priv = filp->private_data;
1234 adev = file_priv->minor->dev->dev_private;
e176fe17 1235 if (adev == NULL)
d38ceaf9 1236 return -EINVAL;
e176fe17
CK		 1237
1238 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
d38ceaf9
AD		 1239}
1240
1241int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1242 uint64_t src_offset,
1243 uint64_t dst_offset,
1244 uint32_t byte_count,
1245 struct reservation_object *resv,
e24db985 1246 struct fence **fence, bool direct_submit)
d38ceaf9
AD		 1247{
1248 struct amdgpu_device *adev = ring->adev;
d71518b5
CK		 1249 struct amdgpu_job *job;
1250
d38ceaf9
AD		 1251 uint32_t max_bytes;
1252 unsigned num_loops, num_dw;
1253 unsigned i;
1254 int r;
1255
d38ceaf9
AD		 1256 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1257 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1258 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1259
c7ae72c0
CZ		 1260 /* for IB padding */
1261 while (num_dw & 0x7)
1262 num_dw++;
1263
d71518b5
CK		 1264 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1265 if (r)
9066b0c3 1266 return r;
c7ae72c0
CZ		 1267
1268 if (resv) {
e86f9cee 1269 r = amdgpu_sync_resv(adev, &job->sync, resv,
c7ae72c0
CZ		 1270 AMDGPU_FENCE_OWNER_UNDEFINED);
1271 if (r) {
1272 DRM_ERROR("sync failed (%d).\n", r);
1273 goto error_free;
1274 }
d38ceaf9 1275 }
d38ceaf9
AD		 1276
1277 for (i = 0; i < num_loops; i++) {
1278 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1279
d71518b5
CK		 1280 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1281 dst_offset, cur_size_in_bytes);
d38ceaf9
AD		 1282
1283 src_offset += cur_size_in_bytes;
1284 dst_offset += cur_size_in_bytes;
1285 byte_count -= cur_size_in_bytes;
1286 }
1287
d71518b5
CK		 1288 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1289 WARN_ON(job->ibs[0].length_dw > num_dw);
e24db985
CZ		 1290 if (direct_submit) {
1291 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1292 NULL, NULL, fence);
1293 job->fence = fence_get(*fence);
1294 if (r)
1295 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1296 amdgpu_job_free(job);
1297 } else {
1298 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1299 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1300 if (r)
1301 goto error_free;
1302 }
d38ceaf9 1303
e24db985 1304 return r;
d71518b5 1305
c7ae72c0 1306error_free:
d71518b5 1307 amdgpu_job_free(job);
c7ae72c0 1308 return r;
d38ceaf9
AD		 1309}
1310
59b4a977
FC		 1311int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1312 uint32_t src_data,
1313 struct reservation_object *resv,
1314 struct fence **fence)
1315{
1316 struct amdgpu_device *adev = bo->adev;
1317 struct amdgpu_job *job;
1318 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1319
1320 uint32_t max_bytes, byte_count;
1321 uint64_t dst_offset;
1322 unsigned int num_loops, num_dw;
1323 unsigned int i;
1324 int r;
1325
1326 byte_count = bo->tbo.num_pages << PAGE_SHIFT;
1327 max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1328 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1329 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1330
1331 /* for IB padding */
1332 while (num_dw & 0x7)
1333 num_dw++;
1334
1335 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1336 if (r)
1337 return r;
1338
1339 if (resv) {
1340 r = amdgpu_sync_resv(adev, &job->sync, resv,
1341 AMDGPU_FENCE_OWNER_UNDEFINED);
1342 if (r) {
1343 DRM_ERROR("sync failed (%d).\n", r);
1344 goto error_free;
1345 }
1346 }
1347
1348 dst_offset = bo->tbo.mem.start << PAGE_SHIFT;
1349 for (i = 0; i < num_loops; i++) {
1350 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1351
1352 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1353 dst_offset, cur_size_in_bytes);
1354
1355 dst_offset += cur_size_in_bytes;
1356 byte_count -= cur_size_in_bytes;
1357 }
1358
1359 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1360 WARN_ON(job->ibs[0].length_dw > num_dw);
1361 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1362 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1363 if (r)
1364 goto error_free;
1365
1366 return 0;
1367
1368error_free:
1369 amdgpu_job_free(job);
1370 return r;
1371}
1372
d38ceaf9
AD		 1373#if defined(CONFIG_DEBUG_FS)
1374
1375static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1376{
1377 struct drm_info_node *node = (struct drm_info_node *)m->private;
1378 unsigned ttm_pl = *(int *)node->info_ent->data;
1379 struct drm_device *dev = node->minor->dev;
1380 struct amdgpu_device *adev = dev->dev_private;
1381 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1382 int ret;
1383 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1384
1385 spin_lock(&glob->lru_lock);
1386 ret = drm_mm_dump_table(m, mm);
1387 spin_unlock(&glob->lru_lock);
a2ef8a97 1388 if (ttm_pl == TTM_PL_VRAM)
e1b35f61 1389 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
a2ef8a97 1390 adev->mman.bdev.man[ttm_pl].size,
e1b35f61
AB		 1391 (u64)atomic64_read(&adev->vram_usage) >> 20,
1392 (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
d38ceaf9
AD		 1393 return ret;
1394}
1395
1396static int ttm_pl_vram = TTM_PL_VRAM;
1397static int ttm_pl_tt = TTM_PL_TT;
1398
06ab6832 1399static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
d38ceaf9
AD		 1400 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1401 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1402 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1403#ifdef CONFIG_SWIOTLB
1404 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1405#endif
1406};
1407
1408static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1409 size_t size, loff_t *pos)
1410{
1411 struct amdgpu_device *adev = f->f_inode->i_private;
1412 ssize_t result = 0;
1413 int r;
1414
1415 if (size & 0x3 || *pos & 0x3)
1416 return -EINVAL;
1417
1418 while (size) {
1419 unsigned long flags;
1420 uint32_t value;
1421
1422 if (*pos >= adev->mc.mc_vram_size)
1423 return result;
1424
1425 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1426 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1427 WREG32(mmMM_INDEX_HI, *pos >> 31);
1428 value = RREG32(mmMM_DATA);
1429 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1430
1431 r = put_user(value, (uint32_t *)buf);
1432 if (r)
1433 return r;
1434
1435 result += 4;
1436 buf += 4;
1437 *pos += 4;
1438 size -= 4;
1439 }
1440
1441 return result;
1442}
1443
1444static const struct file_operations amdgpu_ttm_vram_fops = {
1445 .owner = THIS_MODULE,
1446 .read = amdgpu_ttm_vram_read,
1447 .llseek = default_llseek
1448};
1449
a1d29476
CK		 1450#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1451
d38ceaf9
AD		 1452static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1453 size_t size, loff_t *pos)
1454{
1455 struct amdgpu_device *adev = f->f_inode->i_private;
1456 ssize_t result = 0;
1457 int r;
1458
1459 while (size) {
1460 loff_t p = *pos / PAGE_SIZE;
1461 unsigned off = *pos & ~PAGE_MASK;
1462 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1463 struct page *page;
1464 void *ptr;
1465
1466 if (p >= adev->gart.num_cpu_pages)
1467 return result;
1468
1469 page = adev->gart.pages[p];
1470 if (page) {
1471 ptr = kmap(page);
1472 ptr += off;
1473
1474 r = copy_to_user(buf, ptr, cur_size);
1475 kunmap(adev->gart.pages[p]);
1476 } else
1477 r = clear_user(buf, cur_size);
1478
1479 if (r)
1480 return -EFAULT;
1481
1482 result += cur_size;
1483 buf += cur_size;
1484 *pos += cur_size;
1485 size -= cur_size;
1486 }
1487
1488 return result;
1489}
1490
1491static const struct file_operations amdgpu_ttm_gtt_fops = {
1492 .owner = THIS_MODULE,
1493 .read = amdgpu_ttm_gtt_read,
1494 .llseek = default_llseek
1495};
1496
1497#endif
1498
a1d29476
CK		 1499#endif
1500
d38ceaf9
AD		 1501static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1502{
1503#if defined(CONFIG_DEBUG_FS)
1504 unsigned count;
1505
1506 struct drm_minor *minor = adev->ddev->primary;
1507 struct dentry *ent, *root = minor->debugfs_root;
1508
1509 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1510 adev, &amdgpu_ttm_vram_fops);
1511 if (IS_ERR(ent))
1512 return PTR_ERR(ent);
1513 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1514 adev->mman.vram = ent;
1515
a1d29476 1516#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9
AD		 1517 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1518 adev, &amdgpu_ttm_gtt_fops);
1519 if (IS_ERR(ent))
1520 return PTR_ERR(ent);
1521 i_size_write(ent->d_inode, adev->mc.gtt_size);
1522 adev->mman.gtt = ent;
1523
a1d29476 1524#endif
d38ceaf9
AD		 1525 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1526
1527#ifdef CONFIG_SWIOTLB
1528 if (!swiotlb_nr_tbl())
1529 --count;
1530#endif
1531
1532 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1533#else
1534
1535 return 0;
1536#endif
1537}
1538
1539static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1540{
1541#if defined(CONFIG_DEBUG_FS)
1542
1543 debugfs_remove(adev->mman.vram);
1544 adev->mman.vram = NULL;
1545
a1d29476 1546#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9
AD		 1547 debugfs_remove(adev->mman.gtt);
1548 adev->mman.gtt = NULL;
1549#endif
a1d29476
CK		 1550
1551#endif
d38ceaf9 1552}
a693e050
KW		 1553
1554u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1555{
1556 return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
1557}
Linux 6.x block layer and io_uring tree(s)