Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include "amdgpu.h" | |
30 | #include <drm/amdgpu_drm.h> | |
52c6a62c | 31 | #include "amdgpu_sched.h" |
d38ceaf9 AD |
32 | #include "amdgpu_uvd.h" |
33 | #include "amdgpu_vce.h" | |
32d8c662 | 34 | #include "atom.h" |
d38ceaf9 AD |
35 | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/pm_runtime.h> | |
130e0371 | 39 | #include "amdgpu_amdkfd.h" |
d38ceaf9 | 40 | |
d38ceaf9 AD |
41 | /** |
42 | * amdgpu_driver_unload_kms - Main unload function for KMS. | |
43 | * | |
44 | * @dev: drm dev pointer | |
45 | * | |
46 | * This is the main unload function for KMS (all asics). | |
47 | * Returns 0 on success. | |
48 | */ | |
11b3c20b | 49 | void amdgpu_driver_unload_kms(struct drm_device *dev) |
d38ceaf9 AD |
50 | { |
51 | struct amdgpu_device *adev = dev->dev_private; | |
52 | ||
53 | if (adev == NULL) | |
11b3c20b | 54 | return; |
d38ceaf9 AD |
55 | |
56 | if (adev->rmmio == NULL) | |
57 | goto done_free; | |
58 | ||
3149d9da XY |
59 | if (amdgpu_sriov_vf(adev)) |
60 | amdgpu_virt_request_full_gpu(adev, false); | |
61 | ||
4a788547 LW |
62 | if (amdgpu_device_is_px(dev)) { |
63 | pm_runtime_get_sync(dev->dev); | |
6ce62d8b | 64 | pm_runtime_forbid(dev->dev); |
4a788547 | 65 | } |
d38ceaf9 AD |
66 | |
67 | amdgpu_acpi_fini(adev); | |
68 | ||
69 | amdgpu_device_fini(adev); | |
70 | ||
71 | done_free: | |
72 | kfree(adev); | |
73 | dev->dev_private = NULL; | |
d38ceaf9 AD |
74 | } |
75 | ||
76 | /** | |
77 | * amdgpu_driver_load_kms - Main load function for KMS. | |
78 | * | |
79 | * @dev: drm dev pointer | |
80 | * @flags: device flags | |
81 | * | |
82 | * This is the main load function for KMS (all asics). | |
83 | * Returns 0 on success, error on failure. | |
84 | */ | |
85 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) | |
86 | { | |
87 | struct amdgpu_device *adev; | |
1daee8b4 | 88 | int r, acpi_status; |
d38ceaf9 | 89 | |
6dd13096 FK |
90 | #ifdef CONFIG_DRM_AMDGPU_SI |
91 | if (!amdgpu_si_support) { | |
92 | switch (flags & AMD_ASIC_MASK) { | |
93 | case CHIP_TAHITI: | |
94 | case CHIP_PITCAIRN: | |
95 | case CHIP_VERDE: | |
96 | case CHIP_OLAND: | |
97 | case CHIP_HAINAN: | |
98 | dev_info(dev->dev, | |
99 | "SI support provided by radeon.\n"); | |
100 | dev_info(dev->dev, | |
2b059658 | 101 | "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" |
6dd13096 FK |
102 | ); |
103 | return -ENODEV; | |
104 | } | |
105 | } | |
106 | #endif | |
7df28986 FK |
107 | #ifdef CONFIG_DRM_AMDGPU_CIK |
108 | if (!amdgpu_cik_support) { | |
109 | switch (flags & AMD_ASIC_MASK) { | |
110 | case CHIP_KAVERI: | |
111 | case CHIP_BONAIRE: | |
112 | case CHIP_HAWAII: | |
113 | case CHIP_KABINI: | |
114 | case CHIP_MULLINS: | |
115 | dev_info(dev->dev, | |
2b059658 MD |
116 | "CIK support provided by radeon.\n"); |
117 | dev_info(dev->dev, | |
118 | "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" | |
119 | ); | |
7df28986 FK |
120 | return -ENODEV; |
121 | } | |
122 | } | |
123 | #endif | |
124 | ||
d38ceaf9 AD |
125 | adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); |
126 | if (adev == NULL) { | |
127 | return -ENOMEM; | |
128 | } | |
129 | dev->dev_private = (void *)adev; | |
130 | ||
131 | if ((amdgpu_runtime_pm != 0) && | |
132 | amdgpu_has_atpx() && | |
84b1528e AD |
133 | (amdgpu_is_atpx_hybrid() || |
134 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
84c8b22e LW |
135 | ((flags & AMD_IS_APU) == 0) && |
136 | !pci_is_thunderbolt_attached(dev->pdev)) | |
2f7d10b3 | 137 | flags |= AMD_IS_PX; |
d38ceaf9 AD |
138 | |
139 | /* amdgpu_device_init should report only fatal error | |
140 | * like memory allocation failure or iomapping failure, | |
141 | * or memory manager initialization failure, it must | |
142 | * properly initialize the GPU MC controller and permit | |
143 | * VRAM allocation | |
144 | */ | |
145 | r = amdgpu_device_init(adev, dev, dev->pdev, flags); | |
1daee8b4 | 146 | if (r) { |
d38ceaf9 AD |
147 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
148 | goto out; | |
149 | } | |
150 | ||
151 | /* Call ACPI methods: require modeset init | |
152 | * but failure is not fatal | |
153 | */ | |
154 | if (!r) { | |
155 | acpi_status = amdgpu_acpi_init(adev); | |
156 | if (acpi_status) | |
157 | dev_dbg(&dev->pdev->dev, | |
158 | "Error during ACPI methods call\n"); | |
159 | } | |
160 | ||
161 | if (amdgpu_device_is_px(dev)) { | |
162 | pm_runtime_use_autosuspend(dev->dev); | |
163 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
164 | pm_runtime_set_active(dev->dev); | |
165 | pm_runtime_allow(dev->dev); | |
166 | pm_runtime_mark_last_busy(dev->dev); | |
167 | pm_runtime_put_autosuspend(dev->dev); | |
168 | } | |
169 | ||
170 | out: | |
c9c9bbd7 LW |
171 | if (r) { |
172 | /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ | |
173 | if (adev->rmmio && amdgpu_device_is_px(dev)) | |
174 | pm_runtime_put_noidle(dev->dev); | |
d38ceaf9 | 175 | amdgpu_driver_unload_kms(dev); |
c9c9bbd7 | 176 | } |
d38ceaf9 AD |
177 | |
178 | return r; | |
179 | } | |
180 | ||
000cab9a HR |
181 | static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, |
182 | struct drm_amdgpu_query_fw *query_fw, | |
183 | struct amdgpu_device *adev) | |
184 | { | |
185 | switch (query_fw->fw_type) { | |
186 | case AMDGPU_INFO_FW_VCE: | |
187 | fw_info->ver = adev->vce.fw_version; | |
188 | fw_info->feature = adev->vce.fb_version; | |
189 | break; | |
190 | case AMDGPU_INFO_FW_UVD: | |
191 | fw_info->ver = adev->uvd.fw_version; | |
192 | fw_info->feature = 0; | |
193 | break; | |
3ac952b1 AD |
194 | case AMDGPU_INFO_FW_VCN: |
195 | fw_info->ver = adev->vcn.fw_version; | |
196 | fw_info->feature = 0; | |
197 | break; | |
000cab9a | 198 | case AMDGPU_INFO_FW_GMC: |
770d13b1 | 199 | fw_info->ver = adev->gmc.fw_version; |
000cab9a HR |
200 | fw_info->feature = 0; |
201 | break; | |
202 | case AMDGPU_INFO_FW_GFX_ME: | |
203 | fw_info->ver = adev->gfx.me_fw_version; | |
204 | fw_info->feature = adev->gfx.me_feature_version; | |
205 | break; | |
206 | case AMDGPU_INFO_FW_GFX_PFP: | |
207 | fw_info->ver = adev->gfx.pfp_fw_version; | |
208 | fw_info->feature = adev->gfx.pfp_feature_version; | |
209 | break; | |
210 | case AMDGPU_INFO_FW_GFX_CE: | |
211 | fw_info->ver = adev->gfx.ce_fw_version; | |
212 | fw_info->feature = adev->gfx.ce_feature_version; | |
213 | break; | |
214 | case AMDGPU_INFO_FW_GFX_RLC: | |
215 | fw_info->ver = adev->gfx.rlc_fw_version; | |
216 | fw_info->feature = adev->gfx.rlc_feature_version; | |
217 | break; | |
621a6318 HR |
218 | case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: |
219 | fw_info->ver = adev->gfx.rlc_srlc_fw_version; | |
220 | fw_info->feature = adev->gfx.rlc_srlc_feature_version; | |
221 | break; | |
222 | case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: | |
223 | fw_info->ver = adev->gfx.rlc_srlg_fw_version; | |
224 | fw_info->feature = adev->gfx.rlc_srlg_feature_version; | |
225 | break; | |
226 | case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: | |
227 | fw_info->ver = adev->gfx.rlc_srls_fw_version; | |
228 | fw_info->feature = adev->gfx.rlc_srls_feature_version; | |
229 | break; | |
000cab9a HR |
230 | case AMDGPU_INFO_FW_GFX_MEC: |
231 | if (query_fw->index == 0) { | |
232 | fw_info->ver = adev->gfx.mec_fw_version; | |
233 | fw_info->feature = adev->gfx.mec_feature_version; | |
234 | } else if (query_fw->index == 1) { | |
235 | fw_info->ver = adev->gfx.mec2_fw_version; | |
236 | fw_info->feature = adev->gfx.mec2_feature_version; | |
237 | } else | |
238 | return -EINVAL; | |
239 | break; | |
240 | case AMDGPU_INFO_FW_SMC: | |
241 | fw_info->ver = adev->pm.fw_version; | |
242 | fw_info->feature = 0; | |
243 | break; | |
244 | case AMDGPU_INFO_FW_SDMA: | |
245 | if (query_fw->index >= adev->sdma.num_instances) | |
246 | return -EINVAL; | |
247 | fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; | |
248 | fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; | |
249 | break; | |
6a7ed07e HR |
250 | case AMDGPU_INFO_FW_SOS: |
251 | fw_info->ver = adev->psp.sos_fw_version; | |
252 | fw_info->feature = adev->psp.sos_feature_version; | |
253 | break; | |
254 | case AMDGPU_INFO_FW_ASD: | |
255 | fw_info->ver = adev->psp.asd_fw_version; | |
256 | fw_info->feature = adev->psp.asd_feature_version; | |
257 | break; | |
000cab9a HR |
258 | default: |
259 | return -EINVAL; | |
260 | } | |
261 | return 0; | |
262 | } | |
263 | ||
d38ceaf9 AD |
264 | /* |
265 | * Userspace get information ioctl | |
266 | */ | |
267 | /** | |
268 | * amdgpu_info_ioctl - answer a device specific request. | |
269 | * | |
270 | * @adev: amdgpu device pointer | |
271 | * @data: request object | |
272 | * @filp: drm filp | |
273 | * | |
274 | * This function is used to pass device specific parameters to the userspace | |
275 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
276 | * etc. (all asics). | |
277 | * Returns 0 on success, -EINVAL on failure. | |
278 | */ | |
279 | static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
280 | { | |
281 | struct amdgpu_device *adev = dev->dev_private; | |
282 | struct drm_amdgpu_info *info = data; | |
283 | struct amdgpu_mode_info *minfo = &adev->mode_info; | |
ec2c467e | 284 | void __user *out = (void __user *)(uintptr_t)info->return_pointer; |
d38ceaf9 AD |
285 | uint32_t size = info->return_size; |
286 | struct drm_crtc *crtc; | |
287 | uint32_t ui32 = 0; | |
288 | uint64_t ui64 = 0; | |
10dd74ea | 289 | int i, j, found; |
5ebbac4b | 290 | int ui32_size = sizeof(ui32); |
d38ceaf9 AD |
291 | |
292 | if (!info->return_size || !info->return_pointer) | |
293 | return -EINVAL; | |
294 | ||
2c773de2 S |
295 | /* Ensure IB tests are run on ring */ |
296 | flush_delayed_work(&adev->late_init_work); | |
297 | ||
d38ceaf9 AD |
298 | switch (info->query) { |
299 | case AMDGPU_INFO_ACCEL_WORKING: | |
300 | ui32 = adev->accel_working; | |
301 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
302 | case AMDGPU_INFO_CRTC_FROM_ID: | |
303 | for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { | |
304 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
305 | if (crtc && crtc->base.id == info->mode_crtc.id) { | |
306 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
307 | ui32 = amdgpu_crtc->crtc_id; | |
308 | found = 1; | |
309 | break; | |
310 | } | |
311 | } | |
312 | if (!found) { | |
313 | DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); | |
314 | return -EINVAL; | |
315 | } | |
316 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
317 | case AMDGPU_INFO_HW_IP_INFO: { | |
318 | struct drm_amdgpu_info_hw_ip ip = {}; | |
5fc3aeeb | 319 | enum amd_ip_block_type type; |
d38ceaf9 | 320 | uint32_t ring_mask = 0; |
71062f43 KW |
321 | uint32_t ib_start_alignment = 0; |
322 | uint32_t ib_size_alignment = 0; | |
d38ceaf9 AD |
323 | |
324 | if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) | |
325 | return -EINVAL; | |
326 | ||
327 | switch (info->query_hw_ip.type) { | |
328 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 329 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
330 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
331 | ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); | |
8e2c7ad9 CZ |
332 | ib_start_alignment = 32; |
333 | ib_size_alignment = 32; | |
d38ceaf9 AD |
334 | break; |
335 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 336 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
337 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
338 | ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); | |
8e2c7ad9 CZ |
339 | ib_start_alignment = 32; |
340 | ib_size_alignment = 32; | |
d38ceaf9 AD |
341 | break; |
342 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 343 | type = AMD_IP_BLOCK_TYPE_SDMA; |
c113ea1c AD |
344 | for (i = 0; i < adev->sdma.num_instances; i++) |
345 | ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); | |
8e2c7ad9 CZ |
346 | ib_start_alignment = 256; |
347 | ib_size_alignment = 4; | |
d38ceaf9 AD |
348 | break; |
349 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 350 | type = AMD_IP_BLOCK_TYPE_UVD; |
10dd74ea JZ |
351 | for (i = 0; i < adev->uvd.num_uvd_inst; i++) |
352 | ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0) << i); | |
8e2c7ad9 CZ |
353 | ib_start_alignment = 64; |
354 | ib_size_alignment = 64; | |
d38ceaf9 AD |
355 | break; |
356 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 357 | type = AMD_IP_BLOCK_TYPE_VCE; |
75c65480 | 358 | for (i = 0; i < adev->vce.num_rings; i++) |
d38ceaf9 | 359 | ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); |
8e2c7ad9 | 360 | ib_start_alignment = 4; |
a22f803c | 361 | ib_size_alignment = 1; |
d38ceaf9 | 362 | break; |
63defd3f LL |
363 | case AMDGPU_HW_IP_UVD_ENC: |
364 | type = AMD_IP_BLOCK_TYPE_UVD; | |
10dd74ea JZ |
365 | for (i = 0; i < adev->uvd.num_uvd_inst; i++) |
366 | for (j = 0; j < adev->uvd.num_enc_rings; j++) | |
367 | ring_mask |= | |
368 | ((adev->uvd.inst[i].ring_enc[j].ready ? 1 : 0) << | |
369 | (j + i * adev->uvd.num_enc_rings)); | |
8e2c7ad9 CZ |
370 | ib_start_alignment = 64; |
371 | ib_size_alignment = 64; | |
63defd3f | 372 | break; |
bdc799e5 LL |
373 | case AMDGPU_HW_IP_VCN_DEC: |
374 | type = AMD_IP_BLOCK_TYPE_VCN; | |
375 | ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; | |
8e2c7ad9 | 376 | ib_start_alignment = 16; |
bdc799e5 LL |
377 | ib_size_alignment = 16; |
378 | break; | |
cefbc598 LL |
379 | case AMDGPU_HW_IP_VCN_ENC: |
380 | type = AMD_IP_BLOCK_TYPE_VCN; | |
381 | for (i = 0; i < adev->vcn.num_enc_rings; i++) | |
382 | ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); | |
8e2c7ad9 | 383 | ib_start_alignment = 64; |
cefbc598 LL |
384 | ib_size_alignment = 1; |
385 | break; | |
4bafe440 BZ |
386 | case AMDGPU_HW_IP_VCN_JPEG: |
387 | type = AMD_IP_BLOCK_TYPE_VCN; | |
388 | ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0; | |
8e2c7ad9 | 389 | ib_start_alignment = 16; |
4bafe440 BZ |
390 | ib_size_alignment = 16; |
391 | break; | |
d38ceaf9 AD |
392 | default: |
393 | return -EINVAL; | |
394 | } | |
395 | ||
396 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 AD |
397 | if (adev->ip_blocks[i].version->type == type && |
398 | adev->ip_blocks[i].status.valid) { | |
399 | ip.hw_ip_version_major = adev->ip_blocks[i].version->major; | |
400 | ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; | |
d38ceaf9 AD |
401 | ip.capabilities_flags = 0; |
402 | ip.available_rings = ring_mask; | |
71062f43 KW |
403 | ip.ib_start_alignment = ib_start_alignment; |
404 | ip.ib_size_alignment = ib_size_alignment; | |
d38ceaf9 AD |
405 | break; |
406 | } | |
407 | } | |
408 | return copy_to_user(out, &ip, | |
409 | min((size_t)size, sizeof(ip))) ? -EFAULT : 0; | |
410 | } | |
411 | case AMDGPU_INFO_HW_IP_COUNT: { | |
5fc3aeeb | 412 | enum amd_ip_block_type type; |
d38ceaf9 AD |
413 | uint32_t count = 0; |
414 | ||
415 | switch (info->query_hw_ip.type) { | |
416 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 417 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
418 | break; |
419 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 420 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
421 | break; |
422 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 423 | type = AMD_IP_BLOCK_TYPE_SDMA; |
d38ceaf9 AD |
424 | break; |
425 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 426 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 AD |
427 | break; |
428 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 429 | type = AMD_IP_BLOCK_TYPE_VCE; |
d38ceaf9 | 430 | break; |
63defd3f LL |
431 | case AMDGPU_HW_IP_UVD_ENC: |
432 | type = AMD_IP_BLOCK_TYPE_UVD; | |
433 | break; | |
bdc799e5 | 434 | case AMDGPU_HW_IP_VCN_DEC: |
cefbc598 | 435 | case AMDGPU_HW_IP_VCN_ENC: |
4bafe440 | 436 | case AMDGPU_HW_IP_VCN_JPEG: |
bdc799e5 LL |
437 | type = AMD_IP_BLOCK_TYPE_VCN; |
438 | break; | |
d38ceaf9 AD |
439 | default: |
440 | return -EINVAL; | |
441 | } | |
442 | ||
443 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 AD |
444 | if (adev->ip_blocks[i].version->type == type && |
445 | adev->ip_blocks[i].status.valid && | |
d38ceaf9 AD |
446 | count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) |
447 | count++; | |
448 | ||
449 | return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; | |
450 | } | |
451 | case AMDGPU_INFO_TIMESTAMP: | |
b95e31fd | 452 | ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); |
d38ceaf9 AD |
453 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
454 | case AMDGPU_INFO_FW_VERSION: { | |
455 | struct drm_amdgpu_info_firmware fw_info; | |
000cab9a | 456 | int ret; |
d38ceaf9 AD |
457 | |
458 | /* We only support one instance of each IP block right now. */ | |
459 | if (info->query_fw.ip_instance != 0) | |
460 | return -EINVAL; | |
461 | ||
000cab9a HR |
462 | ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); |
463 | if (ret) | |
464 | return ret; | |
465 | ||
d38ceaf9 AD |
466 | return copy_to_user(out, &fw_info, |
467 | min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; | |
468 | } | |
469 | case AMDGPU_INFO_NUM_BYTES_MOVED: | |
470 | ui64 = atomic64_read(&adev->num_bytes_moved); | |
471 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
83a59b63 MO |
472 | case AMDGPU_INFO_NUM_EVICTIONS: |
473 | ui64 = atomic64_read(&adev->num_evictions); | |
474 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
68e2c5ff MO |
475 | case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: |
476 | ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); | |
477 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
d38ceaf9 | 478 | case AMDGPU_INFO_VRAM_USAGE: |
3c848bb3 | 479 | ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); |
d38ceaf9 AD |
480 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
481 | case AMDGPU_INFO_VIS_VRAM_USAGE: | |
3c848bb3 | 482 | ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); |
d38ceaf9 AD |
483 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
484 | case AMDGPU_INFO_GTT_USAGE: | |
9255d77d | 485 | ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); |
d38ceaf9 AD |
486 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
487 | case AMDGPU_INFO_GDS_CONFIG: { | |
488 | struct drm_amdgpu_info_gds gds_info; | |
489 | ||
c92b90cc | 490 | memset(&gds_info, 0, sizeof(gds_info)); |
d38ceaf9 AD |
491 | gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; |
492 | gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; | |
493 | gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; | |
494 | gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; | |
495 | gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; | |
496 | gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; | |
497 | gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; | |
498 | return copy_to_user(out, &gds_info, | |
499 | min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; | |
500 | } | |
501 | case AMDGPU_INFO_VRAM_GTT: { | |
502 | struct drm_amdgpu_info_vram_gtt vram_gtt; | |
503 | ||
770d13b1 | 504 | vram_gtt.vram_size = adev->gmc.real_vram_size; |
7c0ecda1 | 505 | vram_gtt.vram_size -= adev->vram_pin_size; |
770d13b1 | 506 | vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size; |
ddc21af4 | 507 | vram_gtt.vram_cpu_accessible_size -= adev->visible_pin_size; |
09628c3f CK |
508 | vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; |
509 | vram_gtt.gtt_size *= PAGE_SIZE; | |
d38ceaf9 AD |
510 | vram_gtt.gtt_size -= adev->gart_pin_size; |
511 | return copy_to_user(out, &vram_gtt, | |
512 | min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; | |
513 | } | |
e0adf6c8 JZ |
514 | case AMDGPU_INFO_MEMORY: { |
515 | struct drm_amdgpu_memory_info mem; | |
516 | ||
517 | memset(&mem, 0, sizeof(mem)); | |
770d13b1 | 518 | mem.vram.total_heap_size = adev->gmc.real_vram_size; |
e0adf6c8 | 519 | mem.vram.usable_heap_size = |
770d13b1 | 520 | adev->gmc.real_vram_size - adev->vram_pin_size; |
3c848bb3 CK |
521 | mem.vram.heap_usage = |
522 | amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); | |
e0adf6c8 JZ |
523 | mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; |
524 | ||
525 | mem.cpu_accessible_vram.total_heap_size = | |
770d13b1 | 526 | adev->gmc.visible_vram_size; |
e0adf6c8 | 527 | mem.cpu_accessible_vram.usable_heap_size = |
ddc21af4 | 528 | adev->gmc.visible_vram_size - adev->visible_pin_size; |
e0adf6c8 | 529 | mem.cpu_accessible_vram.heap_usage = |
3c848bb3 | 530 | amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); |
e0adf6c8 JZ |
531 | mem.cpu_accessible_vram.max_allocation = |
532 | mem.cpu_accessible_vram.usable_heap_size * 3 / 4; | |
533 | ||
09628c3f CK |
534 | mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; |
535 | mem.gtt.total_heap_size *= PAGE_SIZE; | |
536 | mem.gtt.usable_heap_size = mem.gtt.total_heap_size | |
537 | - adev->gart_pin_size; | |
9255d77d CK |
538 | mem.gtt.heap_usage = |
539 | amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); | |
e0adf6c8 JZ |
540 | mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; |
541 | ||
542 | return copy_to_user(out, &mem, | |
543 | min((size_t)size, sizeof(mem))) | |
cfa32556 JZ |
544 | ? -EFAULT : 0; |
545 | } | |
d38ceaf9 | 546 | case AMDGPU_INFO_READ_MMR_REG: { |
0d2edd37 | 547 | unsigned n, alloc_size; |
d38ceaf9 AD |
548 | uint32_t *regs; |
549 | unsigned se_num = (info->read_mmr_reg.instance >> | |
550 | AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & | |
551 | AMDGPU_INFO_MMR_SE_INDEX_MASK; | |
552 | unsigned sh_num = (info->read_mmr_reg.instance >> | |
553 | AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & | |
554 | AMDGPU_INFO_MMR_SH_INDEX_MASK; | |
555 | ||
556 | /* set full masks if the userspace set all bits | |
557 | * in the bitfields */ | |
558 | if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) | |
559 | se_num = 0xffffffff; | |
560 | if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) | |
561 | sh_num = 0xffffffff; | |
562 | ||
0d2edd37 | 563 | regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); |
d38ceaf9 AD |
564 | if (!regs) |
565 | return -ENOMEM; | |
0d2edd37 | 566 | alloc_size = info->read_mmr_reg.count * sizeof(*regs); |
d38ceaf9 AD |
567 | |
568 | for (i = 0; i < info->read_mmr_reg.count; i++) | |
569 | if (amdgpu_asic_read_register(adev, se_num, sh_num, | |
570 | info->read_mmr_reg.dword_offset + i, | |
571 | ®s[i])) { | |
572 | DRM_DEBUG_KMS("unallowed offset %#x\n", | |
573 | info->read_mmr_reg.dword_offset + i); | |
574 | kfree(regs); | |
575 | return -EFAULT; | |
576 | } | |
577 | n = copy_to_user(out, regs, min(size, alloc_size)); | |
578 | kfree(regs); | |
579 | return n ? -EFAULT : 0; | |
580 | } | |
581 | case AMDGPU_INFO_DEV_INFO: { | |
c193fa91 | 582 | struct drm_amdgpu_info_device dev_info = {}; |
5b565e0e | 583 | uint64_t vm_size; |
d38ceaf9 AD |
584 | |
585 | dev_info.device_id = dev->pdev->device; | |
586 | dev_info.chip_rev = adev->rev_id; | |
587 | dev_info.external_rev = adev->external_rev_id; | |
588 | dev_info.pci_rev = dev->pdev->revision; | |
589 | dev_info.family = adev->family; | |
590 | dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; | |
591 | dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; | |
592 | /* return all clocks in KHz */ | |
593 | dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; | |
32bf7106 | 594 | if (adev->pm.dpm_enabled) { |
1304f0c7 EQ |
595 | dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; |
596 | dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; | |
32bf7106 | 597 | } else { |
2014bc3f XY |
598 | dev_info.max_engine_clock = adev->clock.default_sclk * 10; |
599 | dev_info.max_memory_clock = adev->clock.default_mclk * 10; | |
32bf7106 | 600 | } |
d38ceaf9 | 601 | dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; |
0b10029d AD |
602 | dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * |
603 | adev->gfx.config.max_shader_engines; | |
d38ceaf9 AD |
604 | dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; |
605 | dev_info._pad = 0; | |
606 | dev_info.ids_flags = 0; | |
2f7d10b3 | 607 | if (adev->flags & AMD_IS_APU) |
d38ceaf9 | 608 | dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; |
aafcafa0 ML |
609 | if (amdgpu_sriov_vf(adev)) |
610 | dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; | |
5b565e0e CK |
611 | |
612 | vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; | |
a3e9a15a | 613 | vm_size -= AMDGPU_VA_RESERVED_SIZE; |
6b034e25 CK |
614 | |
615 | /* Older VCE FW versions are buggy and can handle only 40bits */ | |
616 | if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45) | |
617 | vm_size = min(vm_size, 1ULL << 40); | |
618 | ||
d38ceaf9 | 619 | dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; |
bb7939b2 | 620 | dev_info.virtual_address_max = |
5b565e0e CK |
621 | min(vm_size, AMDGPU_VA_HOLE_START); |
622 | ||
5b565e0e CK |
623 | if (vm_size > AMDGPU_VA_HOLE_START) { |
624 | dev_info.high_va_offset = AMDGPU_VA_HOLE_END; | |
625 | dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size; | |
626 | } | |
c548b345 | 627 | dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); |
e618d306 | 628 | dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; |
d38ceaf9 | 629 | dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; |
7dae69a2 AD |
630 | dev_info.cu_active_number = adev->gfx.cu_info.number; |
631 | dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; | |
a101a899 | 632 | dev_info.ce_ram_size = adev->gfx.ce_ram_size; |
dbfe85ea FC |
633 | memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], |
634 | sizeof(adev->gfx.cu_info.ao_cu_bitmap)); | |
7dae69a2 AD |
635 | memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], |
636 | sizeof(adev->gfx.cu_info.bitmap)); | |
770d13b1 CK |
637 | dev_info.vram_type = adev->gmc.vram_type; |
638 | dev_info.vram_bit_width = adev->gmc.vram_width; | |
fa92754e | 639 | dev_info.vce_harvest_config = adev->vce.harvest_config; |
df6e2c4a JZ |
640 | dev_info.gc_double_offchip_lds_buf = |
641 | adev->gfx.config.double_offchip_lds_buf; | |
d38ceaf9 | 642 | |
bce23e00 | 643 | if (amdgpu_ngg) { |
af8baf15 GR |
644 | dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; |
645 | dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; | |
646 | dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; | |
647 | dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; | |
648 | dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; | |
649 | dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; | |
650 | dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; | |
651 | dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; | |
bce23e00 | 652 | } |
408bfe7c JZ |
653 | dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; |
654 | dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; | |
655 | dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; | |
656 | dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; | |
657 | dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; | |
658 | dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; | |
f47b77b4 | 659 | dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; |
bce23e00 | 660 | |
d38ceaf9 AD |
661 | return copy_to_user(out, &dev_info, |
662 | min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; | |
663 | } | |
07fecde5 AD |
664 | case AMDGPU_INFO_VCE_CLOCK_TABLE: { |
665 | unsigned i; | |
666 | struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; | |
667 | struct amd_vce_state *vce_state; | |
668 | ||
669 | for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { | |
670 | vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); | |
671 | if (vce_state) { | |
672 | vce_clk_table.entries[i].sclk = vce_state->sclk; | |
673 | vce_clk_table.entries[i].mclk = vce_state->mclk; | |
674 | vce_clk_table.entries[i].eclk = vce_state->evclk; | |
675 | vce_clk_table.num_valid_entries++; | |
676 | } | |
677 | } | |
678 | ||
679 | return copy_to_user(out, &vce_clk_table, | |
680 | min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; | |
681 | } | |
40ee5888 EQ |
682 | case AMDGPU_INFO_VBIOS: { |
683 | uint32_t bios_size = adev->bios_size; | |
684 | ||
685 | switch (info->vbios_info.type) { | |
686 | case AMDGPU_INFO_VBIOS_SIZE: | |
687 | return copy_to_user(out, &bios_size, | |
688 | min((size_t)size, sizeof(bios_size))) | |
689 | ? -EFAULT : 0; | |
690 | case AMDGPU_INFO_VBIOS_IMAGE: { | |
691 | uint8_t *bios; | |
692 | uint32_t bios_offset = info->vbios_info.offset; | |
693 | ||
694 | if (bios_offset >= bios_size) | |
695 | return -EINVAL; | |
696 | ||
697 | bios = adev->bios + bios_offset; | |
698 | return copy_to_user(out, bios, | |
699 | min((size_t)size, (size_t)(bios_size - bios_offset))) | |
700 | ? -EFAULT : 0; | |
701 | } | |
702 | default: | |
703 | DRM_DEBUG_KMS("Invalid request %d\n", | |
704 | info->vbios_info.type); | |
705 | return -EINVAL; | |
706 | } | |
707 | } | |
44879b62 AN |
708 | case AMDGPU_INFO_NUM_HANDLES: { |
709 | struct drm_amdgpu_info_num_handles handle; | |
710 | ||
711 | switch (info->query_hw_ip.type) { | |
712 | case AMDGPU_HW_IP_UVD: | |
713 | /* Starting Polaris, we support unlimited UVD handles */ | |
714 | if (adev->asic_type < CHIP_POLARIS10) { | |
715 | handle.uvd_max_handles = adev->uvd.max_handles; | |
716 | handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); | |
717 | ||
718 | return copy_to_user(out, &handle, | |
719 | min((size_t)size, sizeof(handle))) ? -EFAULT : 0; | |
720 | } else { | |
721 | return -ENODATA; | |
722 | } | |
723 | ||
724 | break; | |
725 | default: | |
726 | return -EINVAL; | |
727 | } | |
728 | } | |
5ebbac4b | 729 | case AMDGPU_INFO_SENSOR: { |
b13aa109 | 730 | if (!adev->pm.dpm_enabled) |
5ebbac4b AD |
731 | return -ENOENT; |
732 | ||
733 | switch (info->sensor_info.type) { | |
734 | case AMDGPU_INFO_SENSOR_GFX_SCLK: | |
735 | /* get sclk in Mhz */ | |
736 | if (amdgpu_dpm_read_sensor(adev, | |
737 | AMDGPU_PP_SENSOR_GFX_SCLK, | |
738 | (void *)&ui32, &ui32_size)) { | |
739 | return -EINVAL; | |
740 | } | |
741 | ui32 /= 100; | |
742 | break; | |
743 | case AMDGPU_INFO_SENSOR_GFX_MCLK: | |
744 | /* get mclk in Mhz */ | |
745 | if (amdgpu_dpm_read_sensor(adev, | |
746 | AMDGPU_PP_SENSOR_GFX_MCLK, | |
747 | (void *)&ui32, &ui32_size)) { | |
748 | return -EINVAL; | |
749 | } | |
750 | ui32 /= 100; | |
751 | break; | |
752 | case AMDGPU_INFO_SENSOR_GPU_TEMP: | |
753 | /* get temperature in millidegrees C */ | |
754 | if (amdgpu_dpm_read_sensor(adev, | |
755 | AMDGPU_PP_SENSOR_GPU_TEMP, | |
756 | (void *)&ui32, &ui32_size)) { | |
757 | return -EINVAL; | |
758 | } | |
759 | break; | |
760 | case AMDGPU_INFO_SENSOR_GPU_LOAD: | |
761 | /* get GPU load */ | |
762 | if (amdgpu_dpm_read_sensor(adev, | |
763 | AMDGPU_PP_SENSOR_GPU_LOAD, | |
764 | (void *)&ui32, &ui32_size)) { | |
765 | return -EINVAL; | |
766 | } | |
767 | break; | |
768 | case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: | |
769 | /* get average GPU power */ | |
770 | if (amdgpu_dpm_read_sensor(adev, | |
771 | AMDGPU_PP_SENSOR_GPU_POWER, | |
5b79d048 | 772 | (void *)&ui32, &ui32_size)) { |
5ebbac4b AD |
773 | return -EINVAL; |
774 | } | |
5b79d048 | 775 | ui32 >>= 8; |
5ebbac4b AD |
776 | break; |
777 | case AMDGPU_INFO_SENSOR_VDDNB: | |
778 | /* get VDDNB in millivolts */ | |
779 | if (amdgpu_dpm_read_sensor(adev, | |
780 | AMDGPU_PP_SENSOR_VDDNB, | |
781 | (void *)&ui32, &ui32_size)) { | |
782 | return -EINVAL; | |
783 | } | |
784 | break; | |
785 | case AMDGPU_INFO_SENSOR_VDDGFX: | |
786 | /* get VDDGFX in millivolts */ | |
787 | if (amdgpu_dpm_read_sensor(adev, | |
788 | AMDGPU_PP_SENSOR_VDDGFX, | |
789 | (void *)&ui32, &ui32_size)) { | |
790 | return -EINVAL; | |
791 | } | |
792 | break; | |
60bbade2 RZ |
793 | case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: |
794 | /* get stable pstate sclk in Mhz */ | |
795 | if (amdgpu_dpm_read_sensor(adev, | |
796 | AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, | |
797 | (void *)&ui32, &ui32_size)) { | |
798 | return -EINVAL; | |
799 | } | |
800 | ui32 /= 100; | |
801 | break; | |
802 | case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: | |
803 | /* get stable pstate mclk in Mhz */ | |
804 | if (amdgpu_dpm_read_sensor(adev, | |
805 | AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, | |
806 | (void *)&ui32, &ui32_size)) { | |
807 | return -EINVAL; | |
808 | } | |
809 | ui32 /= 100; | |
810 | break; | |
5ebbac4b AD |
811 | default: |
812 | DRM_DEBUG_KMS("Invalid request %d\n", | |
813 | info->sensor_info.type); | |
814 | return -EINVAL; | |
815 | } | |
816 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
817 | } | |
1f7251b7 CK |
818 | case AMDGPU_INFO_VRAM_LOST_COUNTER: |
819 | ui32 = atomic_read(&adev->vram_lost_counter); | |
820 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
d38ceaf9 AD |
821 | default: |
822 | DRM_DEBUG_KMS("Invalid request %d\n", info->query); | |
823 | return -EINVAL; | |
824 | } | |
825 | return 0; | |
826 | } | |
827 | ||
828 | ||
829 | /* | |
830 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
831 | */ | |
832 | /** | |
8b7530b1 | 833 | * amdgpu_driver_lastclose_kms - drm callback for last close |
d38ceaf9 AD |
834 | * |
835 | * @dev: drm dev pointer | |
836 | * | |
1694467b | 837 | * Switch vga_switcheroo state after last close (all asics). |
d38ceaf9 AD |
838 | */ |
839 | void amdgpu_driver_lastclose_kms(struct drm_device *dev) | |
840 | { | |
ab77e02c | 841 | drm_fb_helper_lastclose(dev); |
d38ceaf9 AD |
842 | vga_switcheroo_process_delayed_switch(); |
843 | } | |
844 | ||
845 | /** | |
846 | * amdgpu_driver_open_kms - drm callback for open | |
847 | * | |
848 | * @dev: drm dev pointer | |
849 | * @file_priv: drm file | |
850 | * | |
851 | * On device open, init vm on cayman+ (all asics). | |
852 | * Returns 0 on success, error on failure. | |
853 | */ | |
854 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |
855 | { | |
856 | struct amdgpu_device *adev = dev->dev_private; | |
857 | struct amdgpu_fpriv *fpriv; | |
5c2ff9a6 | 858 | int r, pasid; |
d38ceaf9 AD |
859 | |
860 | file_priv->driver_priv = NULL; | |
861 | ||
862 | r = pm_runtime_get_sync(dev->dev); | |
863 | if (r < 0) | |
864 | return r; | |
865 | ||
866 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
dc08267a AD |
867 | if (unlikely(!fpriv)) { |
868 | r = -ENOMEM; | |
869 | goto out_suspend; | |
870 | } | |
d38ceaf9 | 871 | |
5c2ff9a6 CK |
872 | pasid = amdgpu_pasid_alloc(16); |
873 | if (pasid < 0) { | |
874 | dev_warn(adev->dev, "No more PASIDs available!"); | |
875 | pasid = 0; | |
dc08267a | 876 | } |
5c2ff9a6 CK |
877 | r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); |
878 | if (r) | |
879 | goto error_pasid; | |
d38ceaf9 | 880 | |
b85891bd JZ |
881 | fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); |
882 | if (!fpriv->prt_va) { | |
883 | r = -ENOMEM; | |
5c2ff9a6 | 884 | goto error_vm; |
b85891bd JZ |
885 | } |
886 | ||
2493664f | 887 | if (amdgpu_sriov_vf(adev)) { |
0f4b3c68 | 888 | r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); |
5c2ff9a6 CK |
889 | if (r) |
890 | goto error_vm; | |
2493664f ML |
891 | } |
892 | ||
d38ceaf9 AD |
893 | mutex_init(&fpriv->bo_list_lock); |
894 | idr_init(&fpriv->bo_list_handles); | |
895 | ||
efd4ccb5 | 896 | amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); |
d38ceaf9 AD |
897 | |
898 | file_priv->driver_priv = fpriv; | |
5c2ff9a6 CK |
899 | goto out_suspend; |
900 | ||
901 | error_vm: | |
902 | amdgpu_vm_fini(adev, &fpriv->vm); | |
903 | ||
904 | error_pasid: | |
905 | if (pasid) | |
906 | amdgpu_pasid_free(pasid); | |
907 | ||
908 | kfree(fpriv); | |
d38ceaf9 | 909 | |
dc08267a | 910 | out_suspend: |
d38ceaf9 AD |
911 | pm_runtime_mark_last_busy(dev->dev); |
912 | pm_runtime_put_autosuspend(dev->dev); | |
d38ceaf9 AD |
913 | |
914 | return r; | |
915 | } | |
916 | ||
917 | /** | |
918 | * amdgpu_driver_postclose_kms - drm callback for post close | |
919 | * | |
920 | * @dev: drm dev pointer | |
921 | * @file_priv: drm file | |
922 | * | |
923 | * On device post close, tear down vm on cayman+ (all asics). | |
924 | */ | |
925 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
926 | struct drm_file *file_priv) | |
927 | { | |
928 | struct amdgpu_device *adev = dev->dev_private; | |
929 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
930 | struct amdgpu_bo_list *list; | |
5c2ff9a6 CK |
931 | struct amdgpu_bo *pd; |
932 | unsigned int pasid; | |
d38ceaf9 AD |
933 | int handle; |
934 | ||
935 | if (!fpriv) | |
936 | return; | |
937 | ||
04e30c9c | 938 | pm_runtime_get_sync(dev->dev); |
02537d63 | 939 | |
ef80d30b LL |
940 | if (adev->asic_type != CHIP_RAVEN) { |
941 | amdgpu_uvd_free_handles(adev, file_priv); | |
942 | amdgpu_vce_free_handles(adev, file_priv); | |
943 | } | |
cd437e37 | 944 | |
b85891bd JZ |
945 | amdgpu_vm_bo_rmv(adev, fpriv->prt_va); |
946 | ||
2493664f ML |
947 | if (amdgpu_sriov_vf(adev)) { |
948 | /* TODO: how to handle reserve failure */ | |
c81a1a74 | 949 | BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); |
0f4b3c68 CK |
950 | amdgpu_vm_bo_rmv(adev, fpriv->csa_va); |
951 | fpriv->csa_va = NULL; | |
2493664f ML |
952 | amdgpu_bo_unreserve(adev->virt.csa_obj); |
953 | } | |
954 | ||
5c2ff9a6 CK |
955 | pasid = fpriv->vm.pasid; |
956 | pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); | |
957 | ||
d38ceaf9 | 958 | amdgpu_vm_fini(adev, &fpriv->vm); |
8ee3a52e ED |
959 | amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); |
960 | ||
5c2ff9a6 CK |
961 | if (pasid) |
962 | amdgpu_pasid_free_delayed(pd->tbo.resv, pasid); | |
963 | amdgpu_bo_unref(&pd); | |
d38ceaf9 AD |
964 | |
965 | idr_for_each_entry(&fpriv->bo_list_handles, list, handle) | |
966 | amdgpu_bo_list_free(list); | |
967 | ||
968 | idr_destroy(&fpriv->bo_list_handles); | |
969 | mutex_destroy(&fpriv->bo_list_lock); | |
970 | ||
d38ceaf9 AD |
971 | kfree(fpriv); |
972 | file_priv->driver_priv = NULL; | |
d6bda7b4 AD |
973 | |
974 | pm_runtime_mark_last_busy(dev->dev); | |
975 | pm_runtime_put_autosuspend(dev->dev); | |
d38ceaf9 AD |
976 | } |
977 | ||
d38ceaf9 AD |
978 | /* |
979 | * VBlank related functions. | |
980 | */ | |
981 | /** | |
982 | * amdgpu_get_vblank_counter_kms - get frame count | |
983 | * | |
984 | * @dev: drm dev pointer | |
88e72717 | 985 | * @pipe: crtc to get the frame count from |
d38ceaf9 AD |
986 | * |
987 | * Gets the frame count on the requested crtc (all asics). | |
988 | * Returns frame count on success, -EINVAL on failure. | |
989 | */ | |
88e72717 | 990 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
991 | { |
992 | struct amdgpu_device *adev = dev->dev_private; | |
8e36f9d3 AD |
993 | int vpos, hpos, stat; |
994 | u32 count; | |
d38ceaf9 | 995 | |
88e72717 TR |
996 | if (pipe >= adev->mode_info.num_crtc) { |
997 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
d38ceaf9 AD |
998 | return -EINVAL; |
999 | } | |
1000 | ||
8e36f9d3 AD |
1001 | /* The hw increments its frame counter at start of vsync, not at start |
1002 | * of vblank, as is required by DRM core vblank counter handling. | |
1003 | * Cook the hw count here to make it appear to the caller as if it | |
1004 | * incremented at start of vblank. We measure distance to start of | |
1005 | * vblank in vpos. vpos therefore will be >= 0 between start of vblank | |
1006 | * and start of vsync, so vpos >= 0 means to bump the hw frame counter | |
1007 | * result by 1 to give the proper appearance to caller. | |
1008 | */ | |
1009 | if (adev->mode_info.crtcs[pipe]) { | |
1010 | /* Repeat readout if needed to provide stable result if | |
1011 | * we cross start of vsync during the queries. | |
1012 | */ | |
1013 | do { | |
1014 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
aa8e286a SL |
1015 | /* Ask amdgpu_display_get_crtc_scanoutpos to return |
1016 | * vpos as distance to start of vblank, instead of | |
1017 | * regular vertical scanout pos. | |
8e36f9d3 | 1018 | */ |
aa8e286a | 1019 | stat = amdgpu_display_get_crtc_scanoutpos( |
8e36f9d3 AD |
1020 | dev, pipe, GET_DISTANCE_TO_VBLANKSTART, |
1021 | &vpos, &hpos, NULL, NULL, | |
1022 | &adev->mode_info.crtcs[pipe]->base.hwmode); | |
1023 | } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); | |
1024 | ||
1025 | if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != | |
1026 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { | |
1027 | DRM_DEBUG_VBL("Query failed! stat %d\n", stat); | |
1028 | } else { | |
1029 | DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", | |
1030 | pipe, vpos); | |
1031 | ||
1032 | /* Bump counter if we are at >= leading edge of vblank, | |
1033 | * but before vsync where vpos would turn negative and | |
1034 | * the hw counter really increments. | |
1035 | */ | |
1036 | if (vpos >= 0) | |
1037 | count++; | |
1038 | } | |
1039 | } else { | |
1040 | /* Fallback to use value as is. */ | |
1041 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
1042 | DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); | |
1043 | } | |
1044 | ||
1045 | return count; | |
d38ceaf9 AD |
1046 | } |
1047 | ||
1048 | /** | |
1049 | * amdgpu_enable_vblank_kms - enable vblank interrupt | |
1050 | * | |
1051 | * @dev: drm dev pointer | |
88e72717 | 1052 | * @pipe: crtc to enable vblank interrupt for |
d38ceaf9 AD |
1053 | * |
1054 | * Enable the interrupt on the requested crtc (all asics). | |
1055 | * Returns 0 on success, -EINVAL on failure. | |
1056 | */ | |
88e72717 | 1057 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
1058 | { |
1059 | struct amdgpu_device *adev = dev->dev_private; | |
734dd01d | 1060 | int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
1061 | |
1062 | return amdgpu_irq_get(adev, &adev->crtc_irq, idx); | |
1063 | } | |
1064 | ||
1065 | /** | |
1066 | * amdgpu_disable_vblank_kms - disable vblank interrupt | |
1067 | * | |
1068 | * @dev: drm dev pointer | |
88e72717 | 1069 | * @pipe: crtc to disable vblank interrupt for |
d38ceaf9 AD |
1070 | * |
1071 | * Disable the interrupt on the requested crtc (all asics). | |
1072 | */ | |
88e72717 | 1073 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
1074 | { |
1075 | struct amdgpu_device *adev = dev->dev_private; | |
734dd01d | 1076 | int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
1077 | |
1078 | amdgpu_irq_put(adev, &adev->crtc_irq, idx); | |
1079 | } | |
1080 | ||
d38ceaf9 | 1081 | const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { |
f8c47144 DV |
1082 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
1083 | DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
cfbcacf4 | 1084 | DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
52c6a62c | 1085 | DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), |
f8c47144 | 1086 | DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
7ca24cf2 | 1087 | DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
d38ceaf9 | 1088 | /* KMS */ |
f8c47144 DV |
1089 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
1090 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1091 | DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1092 | DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1093 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
eef18a82 | 1094 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
f8c47144 DV |
1095 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
1096 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1097 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
4562236b | 1098 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) |
d38ceaf9 | 1099 | }; |
f498d9ed | 1100 | const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); |
50ab2533 HR |
1101 | |
1102 | /* | |
1103 | * Debugfs info | |
1104 | */ | |
1105 | #if defined(CONFIG_DEBUG_FS) | |
1106 | ||
1107 | static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) | |
1108 | { | |
1109 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1110 | struct drm_device *dev = node->minor->dev; | |
1111 | struct amdgpu_device *adev = dev->dev_private; | |
1112 | struct drm_amdgpu_info_firmware fw_info; | |
1113 | struct drm_amdgpu_query_fw query_fw; | |
32d8c662 | 1114 | struct atom_context *ctx = adev->mode_info.atom_context; |
50ab2533 HR |
1115 | int ret, i; |
1116 | ||
1117 | /* VCE */ | |
1118 | query_fw.fw_type = AMDGPU_INFO_FW_VCE; | |
1119 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1120 | if (ret) | |
1121 | return ret; | |
1122 | seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", | |
1123 | fw_info.feature, fw_info.ver); | |
1124 | ||
1125 | /* UVD */ | |
1126 | query_fw.fw_type = AMDGPU_INFO_FW_UVD; | |
1127 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1128 | if (ret) | |
1129 | return ret; | |
1130 | seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", | |
1131 | fw_info.feature, fw_info.ver); | |
1132 | ||
1133 | /* GMC */ | |
1134 | query_fw.fw_type = AMDGPU_INFO_FW_GMC; | |
1135 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1136 | if (ret) | |
1137 | return ret; | |
1138 | seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", | |
1139 | fw_info.feature, fw_info.ver); | |
1140 | ||
1141 | /* ME */ | |
1142 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; | |
1143 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1144 | if (ret) | |
1145 | return ret; | |
1146 | seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", | |
1147 | fw_info.feature, fw_info.ver); | |
1148 | ||
1149 | /* PFP */ | |
1150 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; | |
1151 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", | |
1155 | fw_info.feature, fw_info.ver); | |
1156 | ||
1157 | /* CE */ | |
1158 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; | |
1159 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1160 | if (ret) | |
1161 | return ret; | |
1162 | seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", | |
1163 | fw_info.feature, fw_info.ver); | |
1164 | ||
1165 | /* RLC */ | |
1166 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; | |
1167 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1168 | if (ret) | |
1169 | return ret; | |
1170 | seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", | |
1171 | fw_info.feature, fw_info.ver); | |
1172 | ||
621a6318 HR |
1173 | /* RLC SAVE RESTORE LIST CNTL */ |
1174 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; | |
1175 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1176 | if (ret) | |
1177 | return ret; | |
1178 | seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", | |
1179 | fw_info.feature, fw_info.ver); | |
1180 | ||
1181 | /* RLC SAVE RESTORE LIST GPM MEM */ | |
1182 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; | |
1183 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1184 | if (ret) | |
1185 | return ret; | |
1186 | seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", | |
1187 | fw_info.feature, fw_info.ver); | |
1188 | ||
1189 | /* RLC SAVE RESTORE LIST SRM MEM */ | |
1190 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; | |
1191 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1192 | if (ret) | |
1193 | return ret; | |
1194 | seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", | |
1195 | fw_info.feature, fw_info.ver); | |
1196 | ||
50ab2533 HR |
1197 | /* MEC */ |
1198 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; | |
1199 | query_fw.index = 0; | |
1200 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1201 | if (ret) | |
1202 | return ret; | |
1203 | seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", | |
1204 | fw_info.feature, fw_info.ver); | |
1205 | ||
1206 | /* MEC2 */ | |
1207 | if (adev->asic_type == CHIP_KAVERI || | |
1208 | (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { | |
1209 | query_fw.index = 1; | |
1210 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1211 | if (ret) | |
1212 | return ret; | |
1213 | seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", | |
1214 | fw_info.feature, fw_info.ver); | |
1215 | } | |
1216 | ||
6a7ed07e HR |
1217 | /* PSP SOS */ |
1218 | query_fw.fw_type = AMDGPU_INFO_FW_SOS; | |
1219 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1220 | if (ret) | |
1221 | return ret; | |
1222 | seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", | |
1223 | fw_info.feature, fw_info.ver); | |
1224 | ||
1225 | ||
1226 | /* PSP ASD */ | |
1227 | query_fw.fw_type = AMDGPU_INFO_FW_ASD; | |
1228 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1229 | if (ret) | |
1230 | return ret; | |
1231 | seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", | |
1232 | fw_info.feature, fw_info.ver); | |
1233 | ||
50ab2533 HR |
1234 | /* SMC */ |
1235 | query_fw.fw_type = AMDGPU_INFO_FW_SMC; | |
1236 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1237 | if (ret) | |
1238 | return ret; | |
1239 | seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", | |
1240 | fw_info.feature, fw_info.ver); | |
1241 | ||
1242 | /* SDMA */ | |
1243 | query_fw.fw_type = AMDGPU_INFO_FW_SDMA; | |
1244 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
1245 | query_fw.index = i; | |
1246 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1247 | if (ret) | |
1248 | return ret; | |
1249 | seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", | |
1250 | i, fw_info.feature, fw_info.ver); | |
1251 | } | |
1252 | ||
3ac952b1 AD |
1253 | /* VCN */ |
1254 | query_fw.fw_type = AMDGPU_INFO_FW_VCN; | |
1255 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1256 | if (ret) | |
1257 | return ret; | |
1258 | seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", | |
1259 | fw_info.feature, fw_info.ver); | |
1260 | ||
32d8c662 AD |
1261 | |
1262 | seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); | |
1263 | ||
50ab2533 HR |
1264 | return 0; |
1265 | } | |
1266 | ||
1267 | static const struct drm_info_list amdgpu_firmware_info_list[] = { | |
1268 | {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, | |
1269 | }; | |
1270 | #endif | |
1271 | ||
1272 | int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) | |
1273 | { | |
1274 | #if defined(CONFIG_DEBUG_FS) | |
1275 | return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, | |
1276 | ARRAY_SIZE(amdgpu_firmware_info_list)); | |
1277 | #else | |
1278 | return 0; | |
1279 | #endif | |
1280 | } |