Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include "amdgpu.h" | |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu_uvd.h" | |
32 | #include "amdgpu_vce.h" | |
33 | ||
34 | #include <linux/vga_switcheroo.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/pm_runtime.h> | |
130e0371 | 37 | #include "amdgpu_amdkfd.h" |
d38ceaf9 AD |
38 | |
39 | #if defined(CONFIG_VGA_SWITCHEROO) | |
40 | bool amdgpu_has_atpx(void); | |
41 | #else | |
42 | static inline bool amdgpu_has_atpx(void) { return false; } | |
43 | #endif | |
44 | ||
45 | /** | |
46 | * amdgpu_driver_unload_kms - Main unload function for KMS. | |
47 | * | |
48 | * @dev: drm dev pointer | |
49 | * | |
50 | * This is the main unload function for KMS (all asics). | |
51 | * Returns 0 on success. | |
52 | */ | |
53 | int amdgpu_driver_unload_kms(struct drm_device *dev) | |
54 | { | |
55 | struct amdgpu_device *adev = dev->dev_private; | |
56 | ||
57 | if (adev == NULL) | |
58 | return 0; | |
59 | ||
60 | if (adev->rmmio == NULL) | |
61 | goto done_free; | |
62 | ||
4a788547 LW |
63 | if (amdgpu_device_is_px(dev)) { |
64 | pm_runtime_get_sync(dev->dev); | |
6ce62d8b | 65 | pm_runtime_forbid(dev->dev); |
4a788547 | 66 | } |
d38ceaf9 | 67 | |
130e0371 OG |
68 | amdgpu_amdkfd_device_fini(adev); |
69 | ||
d38ceaf9 AD |
70 | amdgpu_acpi_fini(adev); |
71 | ||
72 | amdgpu_device_fini(adev); | |
73 | ||
74 | done_free: | |
75 | kfree(adev); | |
76 | dev->dev_private = NULL; | |
77 | return 0; | |
78 | } | |
79 | ||
80 | /** | |
81 | * amdgpu_driver_load_kms - Main load function for KMS. | |
82 | * | |
83 | * @dev: drm dev pointer | |
84 | * @flags: device flags | |
85 | * | |
86 | * This is the main load function for KMS (all asics). | |
87 | * Returns 0 on success, error on failure. | |
88 | */ | |
89 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) | |
90 | { | |
91 | struct amdgpu_device *adev; | |
92 | int r, acpi_status; | |
93 | ||
94 | adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); | |
95 | if (adev == NULL) { | |
96 | return -ENOMEM; | |
97 | } | |
98 | dev->dev_private = (void *)adev; | |
99 | ||
100 | if ((amdgpu_runtime_pm != 0) && | |
101 | amdgpu_has_atpx() && | |
2f7d10b3 JZ |
102 | ((flags & AMD_IS_APU) == 0)) |
103 | flags |= AMD_IS_PX; | |
d38ceaf9 AD |
104 | |
105 | /* amdgpu_device_init should report only fatal error | |
106 | * like memory allocation failure or iomapping failure, | |
107 | * or memory manager initialization failure, it must | |
108 | * properly initialize the GPU MC controller and permit | |
109 | * VRAM allocation | |
110 | */ | |
111 | r = amdgpu_device_init(adev, dev, dev->pdev, flags); | |
112 | if (r) { | |
113 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); | |
114 | goto out; | |
115 | } | |
116 | ||
117 | /* Call ACPI methods: require modeset init | |
118 | * but failure is not fatal | |
119 | */ | |
120 | if (!r) { | |
121 | acpi_status = amdgpu_acpi_init(adev); | |
122 | if (acpi_status) | |
123 | dev_dbg(&dev->pdev->dev, | |
124 | "Error during ACPI methods call\n"); | |
125 | } | |
126 | ||
130e0371 OG |
127 | amdgpu_amdkfd_load_interface(adev); |
128 | amdgpu_amdkfd_device_probe(adev); | |
129 | amdgpu_amdkfd_device_init(adev); | |
130 | ||
d38ceaf9 AD |
131 | if (amdgpu_device_is_px(dev)) { |
132 | pm_runtime_use_autosuspend(dev->dev); | |
133 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
134 | pm_runtime_set_active(dev->dev); | |
135 | pm_runtime_allow(dev->dev); | |
136 | pm_runtime_mark_last_busy(dev->dev); | |
137 | pm_runtime_put_autosuspend(dev->dev); | |
138 | } | |
139 | ||
140 | out: | |
c9c9bbd7 LW |
141 | if (r) { |
142 | /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ | |
143 | if (adev->rmmio && amdgpu_device_is_px(dev)) | |
144 | pm_runtime_put_noidle(dev->dev); | |
d38ceaf9 | 145 | amdgpu_driver_unload_kms(dev); |
c9c9bbd7 | 146 | } |
d38ceaf9 AD |
147 | |
148 | return r; | |
149 | } | |
150 | ||
000cab9a HR |
151 | static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, |
152 | struct drm_amdgpu_query_fw *query_fw, | |
153 | struct amdgpu_device *adev) | |
154 | { | |
155 | switch (query_fw->fw_type) { | |
156 | case AMDGPU_INFO_FW_VCE: | |
157 | fw_info->ver = adev->vce.fw_version; | |
158 | fw_info->feature = adev->vce.fb_version; | |
159 | break; | |
160 | case AMDGPU_INFO_FW_UVD: | |
161 | fw_info->ver = adev->uvd.fw_version; | |
162 | fw_info->feature = 0; | |
163 | break; | |
164 | case AMDGPU_INFO_FW_GMC: | |
165 | fw_info->ver = adev->mc.fw_version; | |
166 | fw_info->feature = 0; | |
167 | break; | |
168 | case AMDGPU_INFO_FW_GFX_ME: | |
169 | fw_info->ver = adev->gfx.me_fw_version; | |
170 | fw_info->feature = adev->gfx.me_feature_version; | |
171 | break; | |
172 | case AMDGPU_INFO_FW_GFX_PFP: | |
173 | fw_info->ver = adev->gfx.pfp_fw_version; | |
174 | fw_info->feature = adev->gfx.pfp_feature_version; | |
175 | break; | |
176 | case AMDGPU_INFO_FW_GFX_CE: | |
177 | fw_info->ver = adev->gfx.ce_fw_version; | |
178 | fw_info->feature = adev->gfx.ce_feature_version; | |
179 | break; | |
180 | case AMDGPU_INFO_FW_GFX_RLC: | |
181 | fw_info->ver = adev->gfx.rlc_fw_version; | |
182 | fw_info->feature = adev->gfx.rlc_feature_version; | |
183 | break; | |
184 | case AMDGPU_INFO_FW_GFX_MEC: | |
185 | if (query_fw->index == 0) { | |
186 | fw_info->ver = adev->gfx.mec_fw_version; | |
187 | fw_info->feature = adev->gfx.mec_feature_version; | |
188 | } else if (query_fw->index == 1) { | |
189 | fw_info->ver = adev->gfx.mec2_fw_version; | |
190 | fw_info->feature = adev->gfx.mec2_feature_version; | |
191 | } else | |
192 | return -EINVAL; | |
193 | break; | |
194 | case AMDGPU_INFO_FW_SMC: | |
195 | fw_info->ver = adev->pm.fw_version; | |
196 | fw_info->feature = 0; | |
197 | break; | |
198 | case AMDGPU_INFO_FW_SDMA: | |
199 | if (query_fw->index >= adev->sdma.num_instances) | |
200 | return -EINVAL; | |
201 | fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; | |
202 | fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; | |
203 | break; | |
204 | default: | |
205 | return -EINVAL; | |
206 | } | |
207 | return 0; | |
208 | } | |
209 | ||
d38ceaf9 AD |
210 | /* |
211 | * Userspace get information ioctl | |
212 | */ | |
213 | /** | |
214 | * amdgpu_info_ioctl - answer a device specific request. | |
215 | * | |
216 | * @adev: amdgpu device pointer | |
217 | * @data: request object | |
218 | * @filp: drm filp | |
219 | * | |
220 | * This function is used to pass device specific parameters to the userspace | |
221 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
222 | * etc. (all asics). | |
223 | * Returns 0 on success, -EINVAL on failure. | |
224 | */ | |
225 | static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
226 | { | |
227 | struct amdgpu_device *adev = dev->dev_private; | |
228 | struct drm_amdgpu_info *info = data; | |
229 | struct amdgpu_mode_info *minfo = &adev->mode_info; | |
230 | void __user *out = (void __user *)(long)info->return_pointer; | |
231 | uint32_t size = info->return_size; | |
232 | struct drm_crtc *crtc; | |
233 | uint32_t ui32 = 0; | |
234 | uint64_t ui64 = 0; | |
235 | int i, found; | |
236 | ||
237 | if (!info->return_size || !info->return_pointer) | |
238 | return -EINVAL; | |
239 | ||
240 | switch (info->query) { | |
241 | case AMDGPU_INFO_ACCEL_WORKING: | |
242 | ui32 = adev->accel_working; | |
243 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
244 | case AMDGPU_INFO_CRTC_FROM_ID: | |
245 | for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { | |
246 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
247 | if (crtc && crtc->base.id == info->mode_crtc.id) { | |
248 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
249 | ui32 = amdgpu_crtc->crtc_id; | |
250 | found = 1; | |
251 | break; | |
252 | } | |
253 | } | |
254 | if (!found) { | |
255 | DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); | |
256 | return -EINVAL; | |
257 | } | |
258 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
259 | case AMDGPU_INFO_HW_IP_INFO: { | |
260 | struct drm_amdgpu_info_hw_ip ip = {}; | |
5fc3aeeb | 261 | enum amd_ip_block_type type; |
d38ceaf9 | 262 | uint32_t ring_mask = 0; |
71062f43 KW |
263 | uint32_t ib_start_alignment = 0; |
264 | uint32_t ib_size_alignment = 0; | |
d38ceaf9 AD |
265 | |
266 | if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) | |
267 | return -EINVAL; | |
268 | ||
269 | switch (info->query_hw_ip.type) { | |
270 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 271 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
272 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
273 | ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); | |
71062f43 KW |
274 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
275 | ib_size_alignment = 8; | |
d38ceaf9 AD |
276 | break; |
277 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 278 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
279 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
280 | ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); | |
71062f43 KW |
281 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
282 | ib_size_alignment = 8; | |
d38ceaf9 AD |
283 | break; |
284 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 285 | type = AMD_IP_BLOCK_TYPE_SDMA; |
c113ea1c AD |
286 | for (i = 0; i < adev->sdma.num_instances; i++) |
287 | ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); | |
71062f43 KW |
288 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
289 | ib_size_alignment = 1; | |
d38ceaf9 AD |
290 | break; |
291 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 292 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 | 293 | ring_mask = adev->uvd.ring.ready ? 1 : 0; |
71062f43 | 294 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
c4795ca6 | 295 | ib_size_alignment = 16; |
d38ceaf9 AD |
296 | break; |
297 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 298 | type = AMD_IP_BLOCK_TYPE_VCE; |
75c65480 | 299 | for (i = 0; i < adev->vce.num_rings; i++) |
d38ceaf9 | 300 | ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); |
71062f43 | 301 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
a22f803c | 302 | ib_size_alignment = 1; |
d38ceaf9 AD |
303 | break; |
304 | default: | |
305 | return -EINVAL; | |
306 | } | |
307 | ||
308 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
309 | if (adev->ip_blocks[i].type == type && | |
8faf0e08 | 310 | adev->ip_block_status[i].valid) { |
d38ceaf9 AD |
311 | ip.hw_ip_version_major = adev->ip_blocks[i].major; |
312 | ip.hw_ip_version_minor = adev->ip_blocks[i].minor; | |
313 | ip.capabilities_flags = 0; | |
314 | ip.available_rings = ring_mask; | |
71062f43 KW |
315 | ip.ib_start_alignment = ib_start_alignment; |
316 | ip.ib_size_alignment = ib_size_alignment; | |
d38ceaf9 AD |
317 | break; |
318 | } | |
319 | } | |
320 | return copy_to_user(out, &ip, | |
321 | min((size_t)size, sizeof(ip))) ? -EFAULT : 0; | |
322 | } | |
323 | case AMDGPU_INFO_HW_IP_COUNT: { | |
5fc3aeeb | 324 | enum amd_ip_block_type type; |
d38ceaf9 AD |
325 | uint32_t count = 0; |
326 | ||
327 | switch (info->query_hw_ip.type) { | |
328 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 329 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
330 | break; |
331 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 332 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
333 | break; |
334 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 335 | type = AMD_IP_BLOCK_TYPE_SDMA; |
d38ceaf9 AD |
336 | break; |
337 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 338 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 AD |
339 | break; |
340 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 341 | type = AMD_IP_BLOCK_TYPE_VCE; |
d38ceaf9 AD |
342 | break; |
343 | default: | |
344 | return -EINVAL; | |
345 | } | |
346 | ||
347 | for (i = 0; i < adev->num_ip_blocks; i++) | |
348 | if (adev->ip_blocks[i].type == type && | |
8faf0e08 | 349 | adev->ip_block_status[i].valid && |
d38ceaf9 AD |
350 | count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) |
351 | count++; | |
352 | ||
353 | return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; | |
354 | } | |
355 | case AMDGPU_INFO_TIMESTAMP: | |
b95e31fd | 356 | ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); |
d38ceaf9 AD |
357 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
358 | case AMDGPU_INFO_FW_VERSION: { | |
359 | struct drm_amdgpu_info_firmware fw_info; | |
000cab9a | 360 | int ret; |
d38ceaf9 AD |
361 | |
362 | /* We only support one instance of each IP block right now. */ | |
363 | if (info->query_fw.ip_instance != 0) | |
364 | return -EINVAL; | |
365 | ||
000cab9a HR |
366 | ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); |
367 | if (ret) | |
368 | return ret; | |
369 | ||
d38ceaf9 AD |
370 | return copy_to_user(out, &fw_info, |
371 | min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; | |
372 | } | |
373 | case AMDGPU_INFO_NUM_BYTES_MOVED: | |
374 | ui64 = atomic64_read(&adev->num_bytes_moved); | |
375 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
83a59b63 MO |
376 | case AMDGPU_INFO_NUM_EVICTIONS: |
377 | ui64 = atomic64_read(&adev->num_evictions); | |
378 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
d38ceaf9 AD |
379 | case AMDGPU_INFO_VRAM_USAGE: |
380 | ui64 = atomic64_read(&adev->vram_usage); | |
381 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
382 | case AMDGPU_INFO_VIS_VRAM_USAGE: | |
383 | ui64 = atomic64_read(&adev->vram_vis_usage); | |
384 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
385 | case AMDGPU_INFO_GTT_USAGE: | |
386 | ui64 = atomic64_read(&adev->gtt_usage); | |
387 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
388 | case AMDGPU_INFO_GDS_CONFIG: { | |
389 | struct drm_amdgpu_info_gds gds_info; | |
390 | ||
c92b90cc | 391 | memset(&gds_info, 0, sizeof(gds_info)); |
d38ceaf9 AD |
392 | gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; |
393 | gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; | |
394 | gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; | |
395 | gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; | |
396 | gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; | |
397 | gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; | |
398 | gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; | |
399 | return copy_to_user(out, &gds_info, | |
400 | min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; | |
401 | } | |
402 | case AMDGPU_INFO_VRAM_GTT: { | |
403 | struct drm_amdgpu_info_vram_gtt vram_gtt; | |
404 | ||
405 | vram_gtt.vram_size = adev->mc.real_vram_size; | |
7c0ecda1 | 406 | vram_gtt.vram_size -= adev->vram_pin_size; |
d38ceaf9 | 407 | vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; |
e131b914 | 408 | vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); |
d38ceaf9 AD |
409 | vram_gtt.gtt_size = adev->mc.gtt_size; |
410 | vram_gtt.gtt_size -= adev->gart_pin_size; | |
411 | return copy_to_user(out, &vram_gtt, | |
412 | min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; | |
413 | } | |
e0adf6c8 JZ |
414 | case AMDGPU_INFO_MEMORY: { |
415 | struct drm_amdgpu_memory_info mem; | |
416 | ||
417 | memset(&mem, 0, sizeof(mem)); | |
418 | mem.vram.total_heap_size = adev->mc.real_vram_size; | |
419 | mem.vram.usable_heap_size = | |
420 | adev->mc.real_vram_size - adev->vram_pin_size; | |
421 | mem.vram.heap_usage = atomic64_read(&adev->vram_usage); | |
422 | mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; | |
423 | ||
424 | mem.cpu_accessible_vram.total_heap_size = | |
425 | adev->mc.visible_vram_size; | |
426 | mem.cpu_accessible_vram.usable_heap_size = | |
427 | adev->mc.visible_vram_size - | |
428 | (adev->vram_pin_size - adev->invisible_pin_size); | |
429 | mem.cpu_accessible_vram.heap_usage = | |
430 | atomic64_read(&adev->vram_vis_usage); | |
431 | mem.cpu_accessible_vram.max_allocation = | |
432 | mem.cpu_accessible_vram.usable_heap_size * 3 / 4; | |
433 | ||
434 | mem.gtt.total_heap_size = adev->mc.gtt_size; | |
435 | mem.gtt.usable_heap_size = | |
436 | adev->mc.gtt_size - adev->gart_pin_size; | |
437 | mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage); | |
438 | mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; | |
439 | ||
440 | return copy_to_user(out, &mem, | |
441 | min((size_t)size, sizeof(mem))) | |
cfa32556 JZ |
442 | ? -EFAULT : 0; |
443 | } | |
d38ceaf9 | 444 | case AMDGPU_INFO_READ_MMR_REG: { |
0d2edd37 | 445 | unsigned n, alloc_size; |
d38ceaf9 AD |
446 | uint32_t *regs; |
447 | unsigned se_num = (info->read_mmr_reg.instance >> | |
448 | AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & | |
449 | AMDGPU_INFO_MMR_SE_INDEX_MASK; | |
450 | unsigned sh_num = (info->read_mmr_reg.instance >> | |
451 | AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & | |
452 | AMDGPU_INFO_MMR_SH_INDEX_MASK; | |
453 | ||
454 | /* set full masks if the userspace set all bits | |
455 | * in the bitfields */ | |
456 | if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) | |
457 | se_num = 0xffffffff; | |
458 | if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) | |
459 | sh_num = 0xffffffff; | |
460 | ||
0d2edd37 | 461 | regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); |
d38ceaf9 AD |
462 | if (!regs) |
463 | return -ENOMEM; | |
0d2edd37 | 464 | alloc_size = info->read_mmr_reg.count * sizeof(*regs); |
d38ceaf9 AD |
465 | |
466 | for (i = 0; i < info->read_mmr_reg.count; i++) | |
467 | if (amdgpu_asic_read_register(adev, se_num, sh_num, | |
468 | info->read_mmr_reg.dword_offset + i, | |
469 | ®s[i])) { | |
470 | DRM_DEBUG_KMS("unallowed offset %#x\n", | |
471 | info->read_mmr_reg.dword_offset + i); | |
472 | kfree(regs); | |
473 | return -EFAULT; | |
474 | } | |
475 | n = copy_to_user(out, regs, min(size, alloc_size)); | |
476 | kfree(regs); | |
477 | return n ? -EFAULT : 0; | |
478 | } | |
479 | case AMDGPU_INFO_DEV_INFO: { | |
c193fa91 | 480 | struct drm_amdgpu_info_device dev_info = {}; |
d38ceaf9 AD |
481 | |
482 | dev_info.device_id = dev->pdev->device; | |
483 | dev_info.chip_rev = adev->rev_id; | |
484 | dev_info.external_rev = adev->external_rev_id; | |
485 | dev_info.pci_rev = dev->pdev->revision; | |
486 | dev_info.family = adev->family; | |
487 | dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; | |
488 | dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; | |
489 | /* return all clocks in KHz */ | |
490 | dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; | |
32bf7106 | 491 | if (adev->pm.dpm_enabled) { |
d38ceaf9 AD |
492 | dev_info.max_engine_clock = |
493 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; | |
32bf7106 KW |
494 | dev_info.max_memory_clock = |
495 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; | |
496 | } else { | |
d38ceaf9 | 497 | dev_info.max_engine_clock = adev->pm.default_sclk * 10; |
32bf7106 KW |
498 | dev_info.max_memory_clock = adev->pm.default_mclk * 10; |
499 | } | |
d38ceaf9 | 500 | dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; |
0b10029d AD |
501 | dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * |
502 | adev->gfx.config.max_shader_engines; | |
d38ceaf9 AD |
503 | dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; |
504 | dev_info._pad = 0; | |
505 | dev_info.ids_flags = 0; | |
2f7d10b3 | 506 | if (adev->flags & AMD_IS_APU) |
d38ceaf9 AD |
507 | dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; |
508 | dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; | |
02b70c8c | 509 | dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; |
c548b345 | 510 | dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); |
d38ceaf9 AD |
511 | dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * |
512 | AMDGPU_GPU_PAGE_SIZE; | |
513 | dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; | |
514 | ||
7dae69a2 AD |
515 | dev_info.cu_active_number = adev->gfx.cu_info.number; |
516 | dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; | |
a101a899 | 517 | dev_info.ce_ram_size = adev->gfx.ce_ram_size; |
7dae69a2 AD |
518 | memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], |
519 | sizeof(adev->gfx.cu_info.bitmap)); | |
81c59f54 KW |
520 | dev_info.vram_type = adev->mc.vram_type; |
521 | dev_info.vram_bit_width = adev->mc.vram_width; | |
fa92754e | 522 | dev_info.vce_harvest_config = adev->vce.harvest_config; |
d38ceaf9 AD |
523 | |
524 | return copy_to_user(out, &dev_info, | |
525 | min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; | |
526 | } | |
07fecde5 AD |
527 | case AMDGPU_INFO_VCE_CLOCK_TABLE: { |
528 | unsigned i; | |
529 | struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; | |
530 | struct amd_vce_state *vce_state; | |
531 | ||
532 | for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { | |
533 | vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); | |
534 | if (vce_state) { | |
535 | vce_clk_table.entries[i].sclk = vce_state->sclk; | |
536 | vce_clk_table.entries[i].mclk = vce_state->mclk; | |
537 | vce_clk_table.entries[i].eclk = vce_state->evclk; | |
538 | vce_clk_table.num_valid_entries++; | |
539 | } | |
540 | } | |
541 | ||
542 | return copy_to_user(out, &vce_clk_table, | |
543 | min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; | |
544 | } | |
d38ceaf9 AD |
545 | default: |
546 | DRM_DEBUG_KMS("Invalid request %d\n", info->query); | |
547 | return -EINVAL; | |
548 | } | |
549 | return 0; | |
550 | } | |
551 | ||
552 | ||
553 | /* | |
554 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
555 | */ | |
556 | /** | |
8b7530b1 | 557 | * amdgpu_driver_lastclose_kms - drm callback for last close |
d38ceaf9 AD |
558 | * |
559 | * @dev: drm dev pointer | |
560 | * | |
1694467b | 561 | * Switch vga_switcheroo state after last close (all asics). |
d38ceaf9 AD |
562 | */ |
563 | void amdgpu_driver_lastclose_kms(struct drm_device *dev) | |
564 | { | |
8b7530b1 AD |
565 | struct amdgpu_device *adev = dev->dev_private; |
566 | ||
567 | amdgpu_fbdev_restore_mode(adev); | |
d38ceaf9 AD |
568 | vga_switcheroo_process_delayed_switch(); |
569 | } | |
570 | ||
571 | /** | |
572 | * amdgpu_driver_open_kms - drm callback for open | |
573 | * | |
574 | * @dev: drm dev pointer | |
575 | * @file_priv: drm file | |
576 | * | |
577 | * On device open, init vm on cayman+ (all asics). | |
578 | * Returns 0 on success, error on failure. | |
579 | */ | |
580 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |
581 | { | |
582 | struct amdgpu_device *adev = dev->dev_private; | |
583 | struct amdgpu_fpriv *fpriv; | |
584 | int r; | |
585 | ||
586 | file_priv->driver_priv = NULL; | |
587 | ||
588 | r = pm_runtime_get_sync(dev->dev); | |
589 | if (r < 0) | |
590 | return r; | |
591 | ||
592 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
dc08267a AD |
593 | if (unlikely(!fpriv)) { |
594 | r = -ENOMEM; | |
595 | goto out_suspend; | |
596 | } | |
d38ceaf9 AD |
597 | |
598 | r = amdgpu_vm_init(adev, &fpriv->vm); | |
dc08267a AD |
599 | if (r) { |
600 | kfree(fpriv); | |
601 | goto out_suspend; | |
602 | } | |
d38ceaf9 AD |
603 | |
604 | mutex_init(&fpriv->bo_list_lock); | |
605 | idr_init(&fpriv->bo_list_handles); | |
606 | ||
efd4ccb5 | 607 | amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); |
d38ceaf9 AD |
608 | |
609 | file_priv->driver_priv = fpriv; | |
610 | ||
dc08267a | 611 | out_suspend: |
d38ceaf9 AD |
612 | pm_runtime_mark_last_busy(dev->dev); |
613 | pm_runtime_put_autosuspend(dev->dev); | |
d38ceaf9 AD |
614 | |
615 | return r; | |
616 | } | |
617 | ||
618 | /** | |
619 | * amdgpu_driver_postclose_kms - drm callback for post close | |
620 | * | |
621 | * @dev: drm dev pointer | |
622 | * @file_priv: drm file | |
623 | * | |
624 | * On device post close, tear down vm on cayman+ (all asics). | |
625 | */ | |
626 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
627 | struct drm_file *file_priv) | |
628 | { | |
629 | struct amdgpu_device *adev = dev->dev_private; | |
630 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
631 | struct amdgpu_bo_list *list; | |
632 | int handle; | |
633 | ||
634 | if (!fpriv) | |
635 | return; | |
636 | ||
02537d63 CK |
637 | amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); |
638 | ||
cd437e37 LL |
639 | amdgpu_uvd_free_handles(adev, file_priv); |
640 | amdgpu_vce_free_handles(adev, file_priv); | |
641 | ||
d38ceaf9 AD |
642 | amdgpu_vm_fini(adev, &fpriv->vm); |
643 | ||
644 | idr_for_each_entry(&fpriv->bo_list_handles, list, handle) | |
645 | amdgpu_bo_list_free(list); | |
646 | ||
647 | idr_destroy(&fpriv->bo_list_handles); | |
648 | mutex_destroy(&fpriv->bo_list_lock); | |
649 | ||
d38ceaf9 AD |
650 | kfree(fpriv); |
651 | file_priv->driver_priv = NULL; | |
d6bda7b4 AD |
652 | |
653 | pm_runtime_mark_last_busy(dev->dev); | |
654 | pm_runtime_put_autosuspend(dev->dev); | |
d38ceaf9 AD |
655 | } |
656 | ||
657 | /** | |
658 | * amdgpu_driver_preclose_kms - drm callback for pre close | |
659 | * | |
660 | * @dev: drm dev pointer | |
661 | * @file_priv: drm file | |
662 | * | |
663 | * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx | |
664 | * (all asics). | |
665 | */ | |
666 | void amdgpu_driver_preclose_kms(struct drm_device *dev, | |
667 | struct drm_file *file_priv) | |
668 | { | |
d6bda7b4 | 669 | pm_runtime_get_sync(dev->dev); |
d38ceaf9 AD |
670 | } |
671 | ||
672 | /* | |
673 | * VBlank related functions. | |
674 | */ | |
675 | /** | |
676 | * amdgpu_get_vblank_counter_kms - get frame count | |
677 | * | |
678 | * @dev: drm dev pointer | |
88e72717 | 679 | * @pipe: crtc to get the frame count from |
d38ceaf9 AD |
680 | * |
681 | * Gets the frame count on the requested crtc (all asics). | |
682 | * Returns frame count on success, -EINVAL on failure. | |
683 | */ | |
88e72717 | 684 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
685 | { |
686 | struct amdgpu_device *adev = dev->dev_private; | |
8e36f9d3 AD |
687 | int vpos, hpos, stat; |
688 | u32 count; | |
d38ceaf9 | 689 | |
88e72717 TR |
690 | if (pipe >= adev->mode_info.num_crtc) { |
691 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
d38ceaf9 AD |
692 | return -EINVAL; |
693 | } | |
694 | ||
8e36f9d3 AD |
695 | /* The hw increments its frame counter at start of vsync, not at start |
696 | * of vblank, as is required by DRM core vblank counter handling. | |
697 | * Cook the hw count here to make it appear to the caller as if it | |
698 | * incremented at start of vblank. We measure distance to start of | |
699 | * vblank in vpos. vpos therefore will be >= 0 between start of vblank | |
700 | * and start of vsync, so vpos >= 0 means to bump the hw frame counter | |
701 | * result by 1 to give the proper appearance to caller. | |
702 | */ | |
703 | if (adev->mode_info.crtcs[pipe]) { | |
704 | /* Repeat readout if needed to provide stable result if | |
705 | * we cross start of vsync during the queries. | |
706 | */ | |
707 | do { | |
708 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
709 | /* Ask amdgpu_get_crtc_scanoutpos to return vpos as | |
710 | * distance to start of vblank, instead of regular | |
711 | * vertical scanout pos. | |
712 | */ | |
713 | stat = amdgpu_get_crtc_scanoutpos( | |
714 | dev, pipe, GET_DISTANCE_TO_VBLANKSTART, | |
715 | &vpos, &hpos, NULL, NULL, | |
716 | &adev->mode_info.crtcs[pipe]->base.hwmode); | |
717 | } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); | |
718 | ||
719 | if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != | |
720 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { | |
721 | DRM_DEBUG_VBL("Query failed! stat %d\n", stat); | |
722 | } else { | |
723 | DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", | |
724 | pipe, vpos); | |
725 | ||
726 | /* Bump counter if we are at >= leading edge of vblank, | |
727 | * but before vsync where vpos would turn negative and | |
728 | * the hw counter really increments. | |
729 | */ | |
730 | if (vpos >= 0) | |
731 | count++; | |
732 | } | |
733 | } else { | |
734 | /* Fallback to use value as is. */ | |
735 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
736 | DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); | |
737 | } | |
738 | ||
739 | return count; | |
d38ceaf9 AD |
740 | } |
741 | ||
742 | /** | |
743 | * amdgpu_enable_vblank_kms - enable vblank interrupt | |
744 | * | |
745 | * @dev: drm dev pointer | |
88e72717 | 746 | * @pipe: crtc to enable vblank interrupt for |
d38ceaf9 AD |
747 | * |
748 | * Enable the interrupt on the requested crtc (all asics). | |
749 | * Returns 0 on success, -EINVAL on failure. | |
750 | */ | |
88e72717 | 751 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
752 | { |
753 | struct amdgpu_device *adev = dev->dev_private; | |
88e72717 | 754 | int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
755 | |
756 | return amdgpu_irq_get(adev, &adev->crtc_irq, idx); | |
757 | } | |
758 | ||
759 | /** | |
760 | * amdgpu_disable_vblank_kms - disable vblank interrupt | |
761 | * | |
762 | * @dev: drm dev pointer | |
88e72717 | 763 | * @pipe: crtc to disable vblank interrupt for |
d38ceaf9 AD |
764 | * |
765 | * Disable the interrupt on the requested crtc (all asics). | |
766 | */ | |
88e72717 | 767 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
768 | { |
769 | struct amdgpu_device *adev = dev->dev_private; | |
88e72717 | 770 | int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
771 | |
772 | amdgpu_irq_put(adev, &adev->crtc_irq, idx); | |
773 | } | |
774 | ||
775 | /** | |
776 | * amdgpu_get_vblank_timestamp_kms - get vblank timestamp | |
777 | * | |
778 | * @dev: drm dev pointer | |
779 | * @crtc: crtc to get the timestamp for | |
780 | * @max_error: max error | |
781 | * @vblank_time: time value | |
782 | * @flags: flags passed to the driver | |
783 | * | |
784 | * Gets the timestamp on the requested crtc based on the | |
785 | * scanout position. (all asics). | |
786 | * Returns postive status flags on success, negative error on failure. | |
787 | */ | |
88e72717 | 788 | int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, |
d38ceaf9 AD |
789 | int *max_error, |
790 | struct timeval *vblank_time, | |
791 | unsigned flags) | |
792 | { | |
88e72717 | 793 | struct drm_crtc *crtc; |
d38ceaf9 AD |
794 | struct amdgpu_device *adev = dev->dev_private; |
795 | ||
88e72717 TR |
796 | if (pipe >= dev->num_crtcs) { |
797 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
d38ceaf9 AD |
798 | return -EINVAL; |
799 | } | |
800 | ||
801 | /* Get associated drm_crtc: */ | |
88e72717 | 802 | crtc = &adev->mode_info.crtcs[pipe]->base; |
9ddf940f HW |
803 | if (!crtc) { |
804 | /* This can occur on driver load if some component fails to | |
805 | * initialize completely and driver is unloaded */ | |
806 | DRM_ERROR("Uninitialized crtc %d\n", pipe); | |
807 | return -EINVAL; | |
808 | } | |
d38ceaf9 AD |
809 | |
810 | /* Helper routine in DRM core does all the work: */ | |
88e72717 | 811 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
d38ceaf9 | 812 | vblank_time, flags, |
88e72717 | 813 | &crtc->hwmode); |
d38ceaf9 AD |
814 | } |
815 | ||
816 | const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { | |
f8c47144 DV |
817 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
818 | DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
819 | DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
d38ceaf9 | 820 | /* KMS */ |
f8c47144 DV |
821 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
822 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
823 | DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
824 | DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
825 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
826 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
827 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
828 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
829 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
d38ceaf9 | 830 | }; |
f498d9ed | 831 | const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); |
50ab2533 HR |
832 | |
833 | /* | |
834 | * Debugfs info | |
835 | */ | |
836 | #if defined(CONFIG_DEBUG_FS) | |
837 | ||
838 | static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) | |
839 | { | |
840 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
841 | struct drm_device *dev = node->minor->dev; | |
842 | struct amdgpu_device *adev = dev->dev_private; | |
843 | struct drm_amdgpu_info_firmware fw_info; | |
844 | struct drm_amdgpu_query_fw query_fw; | |
845 | int ret, i; | |
846 | ||
847 | /* VCE */ | |
848 | query_fw.fw_type = AMDGPU_INFO_FW_VCE; | |
849 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
850 | if (ret) | |
851 | return ret; | |
852 | seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", | |
853 | fw_info.feature, fw_info.ver); | |
854 | ||
855 | /* UVD */ | |
856 | query_fw.fw_type = AMDGPU_INFO_FW_UVD; | |
857 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
858 | if (ret) | |
859 | return ret; | |
860 | seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", | |
861 | fw_info.feature, fw_info.ver); | |
862 | ||
863 | /* GMC */ | |
864 | query_fw.fw_type = AMDGPU_INFO_FW_GMC; | |
865 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
866 | if (ret) | |
867 | return ret; | |
868 | seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", | |
869 | fw_info.feature, fw_info.ver); | |
870 | ||
871 | /* ME */ | |
872 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; | |
873 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
874 | if (ret) | |
875 | return ret; | |
876 | seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", | |
877 | fw_info.feature, fw_info.ver); | |
878 | ||
879 | /* PFP */ | |
880 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; | |
881 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
882 | if (ret) | |
883 | return ret; | |
884 | seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", | |
885 | fw_info.feature, fw_info.ver); | |
886 | ||
887 | /* CE */ | |
888 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; | |
889 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
890 | if (ret) | |
891 | return ret; | |
892 | seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", | |
893 | fw_info.feature, fw_info.ver); | |
894 | ||
895 | /* RLC */ | |
896 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; | |
897 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
898 | if (ret) | |
899 | return ret; | |
900 | seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", | |
901 | fw_info.feature, fw_info.ver); | |
902 | ||
903 | /* MEC */ | |
904 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; | |
905 | query_fw.index = 0; | |
906 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
907 | if (ret) | |
908 | return ret; | |
909 | seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", | |
910 | fw_info.feature, fw_info.ver); | |
911 | ||
912 | /* MEC2 */ | |
913 | if (adev->asic_type == CHIP_KAVERI || | |
914 | (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { | |
915 | query_fw.index = 1; | |
916 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
917 | if (ret) | |
918 | return ret; | |
919 | seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", | |
920 | fw_info.feature, fw_info.ver); | |
921 | } | |
922 | ||
923 | /* SMC */ | |
924 | query_fw.fw_type = AMDGPU_INFO_FW_SMC; | |
925 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
926 | if (ret) | |
927 | return ret; | |
928 | seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", | |
929 | fw_info.feature, fw_info.ver); | |
930 | ||
931 | /* SDMA */ | |
932 | query_fw.fw_type = AMDGPU_INFO_FW_SDMA; | |
933 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
934 | query_fw.index = i; | |
935 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
936 | if (ret) | |
937 | return ret; | |
938 | seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", | |
939 | i, fw_info.feature, fw_info.ver); | |
940 | } | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | static const struct drm_info_list amdgpu_firmware_info_list[] = { | |
946 | {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, | |
947 | }; | |
948 | #endif | |
949 | ||
950 | int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) | |
951 | { | |
952 | #if defined(CONFIG_DEBUG_FS) | |
953 | return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, | |
954 | ARRAY_SIZE(amdgpu_firmware_info_list)); | |
955 | #else | |
956 | return 0; | |
957 | #endif | |
958 | } |