Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include "amdgpu.h" | |
30 | #include <drm/amdgpu_drm.h> | |
52c6a62c | 31 | #include "amdgpu_sched.h" |
d38ceaf9 AD |
32 | #include "amdgpu_uvd.h" |
33 | #include "amdgpu_vce.h" | |
34 | ||
35 | #include <linux/vga_switcheroo.h> | |
36 | #include <linux/slab.h> | |
37 | #include <linux/pm_runtime.h> | |
130e0371 | 38 | #include "amdgpu_amdkfd.h" |
d38ceaf9 | 39 | |
d38ceaf9 AD |
40 | /** |
41 | * amdgpu_driver_unload_kms - Main unload function for KMS. | |
42 | * | |
43 | * @dev: drm dev pointer | |
44 | * | |
45 | * This is the main unload function for KMS (all asics). | |
46 | * Returns 0 on success. | |
47 | */ | |
11b3c20b | 48 | void amdgpu_driver_unload_kms(struct drm_device *dev) |
d38ceaf9 AD |
49 | { |
50 | struct amdgpu_device *adev = dev->dev_private; | |
51 | ||
52 | if (adev == NULL) | |
11b3c20b | 53 | return; |
d38ceaf9 AD |
54 | |
55 | if (adev->rmmio == NULL) | |
56 | goto done_free; | |
57 | ||
3149d9da XY |
58 | if (amdgpu_sriov_vf(adev)) |
59 | amdgpu_virt_request_full_gpu(adev, false); | |
60 | ||
4a788547 LW |
61 | if (amdgpu_device_is_px(dev)) { |
62 | pm_runtime_get_sync(dev->dev); | |
6ce62d8b | 63 | pm_runtime_forbid(dev->dev); |
4a788547 | 64 | } |
d38ceaf9 AD |
65 | |
66 | amdgpu_acpi_fini(adev); | |
67 | ||
68 | amdgpu_device_fini(adev); | |
69 | ||
70 | done_free: | |
71 | kfree(adev); | |
72 | dev->dev_private = NULL; | |
d38ceaf9 AD |
73 | } |
74 | ||
75 | /** | |
76 | * amdgpu_driver_load_kms - Main load function for KMS. | |
77 | * | |
78 | * @dev: drm dev pointer | |
79 | * @flags: device flags | |
80 | * | |
81 | * This is the main load function for KMS (all asics). | |
82 | * Returns 0 on success, error on failure. | |
83 | */ | |
84 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) | |
85 | { | |
86 | struct amdgpu_device *adev; | |
8840a387 | 87 | int r, acpi_status, retry = 0; |
d38ceaf9 | 88 | |
6dd13096 FK |
89 | #ifdef CONFIG_DRM_AMDGPU_SI |
90 | if (!amdgpu_si_support) { | |
91 | switch (flags & AMD_ASIC_MASK) { | |
92 | case CHIP_TAHITI: | |
93 | case CHIP_PITCAIRN: | |
94 | case CHIP_VERDE: | |
95 | case CHIP_OLAND: | |
96 | case CHIP_HAINAN: | |
97 | dev_info(dev->dev, | |
98 | "SI support provided by radeon.\n"); | |
99 | dev_info(dev->dev, | |
2b059658 | 100 | "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" |
6dd13096 FK |
101 | ); |
102 | return -ENODEV; | |
103 | } | |
104 | } | |
105 | #endif | |
7df28986 FK |
106 | #ifdef CONFIG_DRM_AMDGPU_CIK |
107 | if (!amdgpu_cik_support) { | |
108 | switch (flags & AMD_ASIC_MASK) { | |
109 | case CHIP_KAVERI: | |
110 | case CHIP_BONAIRE: | |
111 | case CHIP_HAWAII: | |
112 | case CHIP_KABINI: | |
113 | case CHIP_MULLINS: | |
114 | dev_info(dev->dev, | |
2b059658 MD |
115 | "CIK support provided by radeon.\n"); |
116 | dev_info(dev->dev, | |
117 | "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" | |
118 | ); | |
7df28986 FK |
119 | return -ENODEV; |
120 | } | |
121 | } | |
122 | #endif | |
8840a387 | 123 | retry_init: |
7df28986 | 124 | |
d38ceaf9 AD |
125 | adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); |
126 | if (adev == NULL) { | |
127 | return -ENOMEM; | |
128 | } | |
129 | dev->dev_private = (void *)adev; | |
130 | ||
131 | if ((amdgpu_runtime_pm != 0) && | |
132 | amdgpu_has_atpx() && | |
84b1528e AD |
133 | (amdgpu_is_atpx_hybrid() || |
134 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
84c8b22e LW |
135 | ((flags & AMD_IS_APU) == 0) && |
136 | !pci_is_thunderbolt_attached(dev->pdev)) | |
2f7d10b3 | 137 | flags |= AMD_IS_PX; |
d38ceaf9 AD |
138 | |
139 | /* amdgpu_device_init should report only fatal error | |
140 | * like memory allocation failure or iomapping failure, | |
141 | * or memory manager initialization failure, it must | |
142 | * properly initialize the GPU MC controller and permit | |
143 | * VRAM allocation | |
144 | */ | |
145 | r = amdgpu_device_init(adev, dev, dev->pdev, flags); | |
8840a387 | 146 | if (r == -EAGAIN && ++retry <= 3) { |
147 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
148 | adev->virt.ops = NULL; | |
149 | amdgpu_device_fini(adev); | |
150 | kfree(adev); | |
151 | dev->dev_private = NULL; | |
152 | /* Don't request EX mode too frequently which is attacking */ | |
153 | msleep(5000); | |
154 | dev_err(&dev->pdev->dev, "retry init %d\n", retry); | |
155 | goto retry_init; | |
156 | } else if (r) { | |
d38ceaf9 AD |
157 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
158 | goto out; | |
159 | } | |
160 | ||
161 | /* Call ACPI methods: require modeset init | |
162 | * but failure is not fatal | |
163 | */ | |
164 | if (!r) { | |
165 | acpi_status = amdgpu_acpi_init(adev); | |
166 | if (acpi_status) | |
167 | dev_dbg(&dev->pdev->dev, | |
168 | "Error during ACPI methods call\n"); | |
169 | } | |
170 | ||
171 | if (amdgpu_device_is_px(dev)) { | |
172 | pm_runtime_use_autosuspend(dev->dev); | |
173 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
174 | pm_runtime_set_active(dev->dev); | |
175 | pm_runtime_allow(dev->dev); | |
176 | pm_runtime_mark_last_busy(dev->dev); | |
177 | pm_runtime_put_autosuspend(dev->dev); | |
178 | } | |
179 | ||
180 | out: | |
c9c9bbd7 LW |
181 | if (r) { |
182 | /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ | |
183 | if (adev->rmmio && amdgpu_device_is_px(dev)) | |
184 | pm_runtime_put_noidle(dev->dev); | |
d38ceaf9 | 185 | amdgpu_driver_unload_kms(dev); |
c9c9bbd7 | 186 | } |
d38ceaf9 AD |
187 | |
188 | return r; | |
189 | } | |
190 | ||
000cab9a HR |
191 | static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, |
192 | struct drm_amdgpu_query_fw *query_fw, | |
193 | struct amdgpu_device *adev) | |
194 | { | |
195 | switch (query_fw->fw_type) { | |
196 | case AMDGPU_INFO_FW_VCE: | |
197 | fw_info->ver = adev->vce.fw_version; | |
198 | fw_info->feature = adev->vce.fb_version; | |
199 | break; | |
200 | case AMDGPU_INFO_FW_UVD: | |
201 | fw_info->ver = adev->uvd.fw_version; | |
202 | fw_info->feature = 0; | |
203 | break; | |
204 | case AMDGPU_INFO_FW_GMC: | |
205 | fw_info->ver = adev->mc.fw_version; | |
206 | fw_info->feature = 0; | |
207 | break; | |
208 | case AMDGPU_INFO_FW_GFX_ME: | |
209 | fw_info->ver = adev->gfx.me_fw_version; | |
210 | fw_info->feature = adev->gfx.me_feature_version; | |
211 | break; | |
212 | case AMDGPU_INFO_FW_GFX_PFP: | |
213 | fw_info->ver = adev->gfx.pfp_fw_version; | |
214 | fw_info->feature = adev->gfx.pfp_feature_version; | |
215 | break; | |
216 | case AMDGPU_INFO_FW_GFX_CE: | |
217 | fw_info->ver = adev->gfx.ce_fw_version; | |
218 | fw_info->feature = adev->gfx.ce_feature_version; | |
219 | break; | |
220 | case AMDGPU_INFO_FW_GFX_RLC: | |
221 | fw_info->ver = adev->gfx.rlc_fw_version; | |
222 | fw_info->feature = adev->gfx.rlc_feature_version; | |
223 | break; | |
224 | case AMDGPU_INFO_FW_GFX_MEC: | |
225 | if (query_fw->index == 0) { | |
226 | fw_info->ver = adev->gfx.mec_fw_version; | |
227 | fw_info->feature = adev->gfx.mec_feature_version; | |
228 | } else if (query_fw->index == 1) { | |
229 | fw_info->ver = adev->gfx.mec2_fw_version; | |
230 | fw_info->feature = adev->gfx.mec2_feature_version; | |
231 | } else | |
232 | return -EINVAL; | |
233 | break; | |
234 | case AMDGPU_INFO_FW_SMC: | |
235 | fw_info->ver = adev->pm.fw_version; | |
236 | fw_info->feature = 0; | |
237 | break; | |
238 | case AMDGPU_INFO_FW_SDMA: | |
239 | if (query_fw->index >= adev->sdma.num_instances) | |
240 | return -EINVAL; | |
241 | fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; | |
242 | fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; | |
243 | break; | |
6a7ed07e HR |
244 | case AMDGPU_INFO_FW_SOS: |
245 | fw_info->ver = adev->psp.sos_fw_version; | |
246 | fw_info->feature = adev->psp.sos_feature_version; | |
247 | break; | |
248 | case AMDGPU_INFO_FW_ASD: | |
249 | fw_info->ver = adev->psp.asd_fw_version; | |
250 | fw_info->feature = adev->psp.asd_feature_version; | |
251 | break; | |
000cab9a HR |
252 | default: |
253 | return -EINVAL; | |
254 | } | |
255 | return 0; | |
256 | } | |
257 | ||
d38ceaf9 AD |
258 | /* |
259 | * Userspace get information ioctl | |
260 | */ | |
261 | /** | |
262 | * amdgpu_info_ioctl - answer a device specific request. | |
263 | * | |
264 | * @adev: amdgpu device pointer | |
265 | * @data: request object | |
266 | * @filp: drm filp | |
267 | * | |
268 | * This function is used to pass device specific parameters to the userspace | |
269 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
270 | * etc. (all asics). | |
271 | * Returns 0 on success, -EINVAL on failure. | |
272 | */ | |
273 | static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
274 | { | |
275 | struct amdgpu_device *adev = dev->dev_private; | |
276 | struct drm_amdgpu_info *info = data; | |
277 | struct amdgpu_mode_info *minfo = &adev->mode_info; | |
ec2c467e | 278 | void __user *out = (void __user *)(uintptr_t)info->return_pointer; |
d38ceaf9 AD |
279 | uint32_t size = info->return_size; |
280 | struct drm_crtc *crtc; | |
281 | uint32_t ui32 = 0; | |
282 | uint64_t ui64 = 0; | |
283 | int i, found; | |
5ebbac4b | 284 | int ui32_size = sizeof(ui32); |
d38ceaf9 AD |
285 | |
286 | if (!info->return_size || !info->return_pointer) | |
287 | return -EINVAL; | |
288 | ||
289 | switch (info->query) { | |
290 | case AMDGPU_INFO_ACCEL_WORKING: | |
291 | ui32 = adev->accel_working; | |
292 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
293 | case AMDGPU_INFO_CRTC_FROM_ID: | |
294 | for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { | |
295 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
296 | if (crtc && crtc->base.id == info->mode_crtc.id) { | |
297 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
298 | ui32 = amdgpu_crtc->crtc_id; | |
299 | found = 1; | |
300 | break; | |
301 | } | |
302 | } | |
303 | if (!found) { | |
304 | DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); | |
305 | return -EINVAL; | |
306 | } | |
307 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
308 | case AMDGPU_INFO_HW_IP_INFO: { | |
309 | struct drm_amdgpu_info_hw_ip ip = {}; | |
5fc3aeeb | 310 | enum amd_ip_block_type type; |
d38ceaf9 | 311 | uint32_t ring_mask = 0; |
71062f43 KW |
312 | uint32_t ib_start_alignment = 0; |
313 | uint32_t ib_size_alignment = 0; | |
d38ceaf9 AD |
314 | |
315 | if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) | |
316 | return -EINVAL; | |
317 | ||
318 | switch (info->query_hw_ip.type) { | |
319 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 320 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
321 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
322 | ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); | |
71062f43 KW |
323 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
324 | ib_size_alignment = 8; | |
d38ceaf9 AD |
325 | break; |
326 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 327 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
328 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
329 | ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); | |
71062f43 KW |
330 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
331 | ib_size_alignment = 8; | |
d38ceaf9 AD |
332 | break; |
333 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 334 | type = AMD_IP_BLOCK_TYPE_SDMA; |
c113ea1c AD |
335 | for (i = 0; i < adev->sdma.num_instances; i++) |
336 | ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); | |
71062f43 KW |
337 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
338 | ib_size_alignment = 1; | |
d38ceaf9 AD |
339 | break; |
340 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 341 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 | 342 | ring_mask = adev->uvd.ring.ready ? 1 : 0; |
71062f43 | 343 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
c4795ca6 | 344 | ib_size_alignment = 16; |
d38ceaf9 AD |
345 | break; |
346 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 347 | type = AMD_IP_BLOCK_TYPE_VCE; |
75c65480 | 348 | for (i = 0; i < adev->vce.num_rings; i++) |
d38ceaf9 | 349 | ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); |
71062f43 | 350 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
a22f803c | 351 | ib_size_alignment = 1; |
d38ceaf9 | 352 | break; |
63defd3f LL |
353 | case AMDGPU_HW_IP_UVD_ENC: |
354 | type = AMD_IP_BLOCK_TYPE_UVD; | |
355 | for (i = 0; i < adev->uvd.num_enc_rings; i++) | |
356 | ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i); | |
357 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; | |
358 | ib_size_alignment = 1; | |
359 | break; | |
bdc799e5 LL |
360 | case AMDGPU_HW_IP_VCN_DEC: |
361 | type = AMD_IP_BLOCK_TYPE_VCN; | |
362 | ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; | |
363 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; | |
364 | ib_size_alignment = 16; | |
365 | break; | |
cefbc598 LL |
366 | case AMDGPU_HW_IP_VCN_ENC: |
367 | type = AMD_IP_BLOCK_TYPE_VCN; | |
368 | for (i = 0; i < adev->vcn.num_enc_rings; i++) | |
369 | ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); | |
370 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; | |
371 | ib_size_alignment = 1; | |
372 | break; | |
d38ceaf9 AD |
373 | default: |
374 | return -EINVAL; | |
375 | } | |
376 | ||
377 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 AD |
378 | if (adev->ip_blocks[i].version->type == type && |
379 | adev->ip_blocks[i].status.valid) { | |
380 | ip.hw_ip_version_major = adev->ip_blocks[i].version->major; | |
381 | ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; | |
d38ceaf9 AD |
382 | ip.capabilities_flags = 0; |
383 | ip.available_rings = ring_mask; | |
71062f43 KW |
384 | ip.ib_start_alignment = ib_start_alignment; |
385 | ip.ib_size_alignment = ib_size_alignment; | |
d38ceaf9 AD |
386 | break; |
387 | } | |
388 | } | |
389 | return copy_to_user(out, &ip, | |
390 | min((size_t)size, sizeof(ip))) ? -EFAULT : 0; | |
391 | } | |
392 | case AMDGPU_INFO_HW_IP_COUNT: { | |
5fc3aeeb | 393 | enum amd_ip_block_type type; |
d38ceaf9 AD |
394 | uint32_t count = 0; |
395 | ||
396 | switch (info->query_hw_ip.type) { | |
397 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 398 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
399 | break; |
400 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 401 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
402 | break; |
403 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 404 | type = AMD_IP_BLOCK_TYPE_SDMA; |
d38ceaf9 AD |
405 | break; |
406 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 407 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 AD |
408 | break; |
409 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 410 | type = AMD_IP_BLOCK_TYPE_VCE; |
d38ceaf9 | 411 | break; |
63defd3f LL |
412 | case AMDGPU_HW_IP_UVD_ENC: |
413 | type = AMD_IP_BLOCK_TYPE_UVD; | |
414 | break; | |
bdc799e5 | 415 | case AMDGPU_HW_IP_VCN_DEC: |
cefbc598 | 416 | case AMDGPU_HW_IP_VCN_ENC: |
bdc799e5 LL |
417 | type = AMD_IP_BLOCK_TYPE_VCN; |
418 | break; | |
d38ceaf9 AD |
419 | default: |
420 | return -EINVAL; | |
421 | } | |
422 | ||
423 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 AD |
424 | if (adev->ip_blocks[i].version->type == type && |
425 | adev->ip_blocks[i].status.valid && | |
d38ceaf9 AD |
426 | count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) |
427 | count++; | |
428 | ||
429 | return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; | |
430 | } | |
431 | case AMDGPU_INFO_TIMESTAMP: | |
b95e31fd | 432 | ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); |
d38ceaf9 AD |
433 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
434 | case AMDGPU_INFO_FW_VERSION: { | |
435 | struct drm_amdgpu_info_firmware fw_info; | |
000cab9a | 436 | int ret; |
d38ceaf9 AD |
437 | |
438 | /* We only support one instance of each IP block right now. */ | |
439 | if (info->query_fw.ip_instance != 0) | |
440 | return -EINVAL; | |
441 | ||
000cab9a HR |
442 | ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); |
443 | if (ret) | |
444 | return ret; | |
445 | ||
d38ceaf9 AD |
446 | return copy_to_user(out, &fw_info, |
447 | min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; | |
448 | } | |
449 | case AMDGPU_INFO_NUM_BYTES_MOVED: | |
450 | ui64 = atomic64_read(&adev->num_bytes_moved); | |
451 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
83a59b63 MO |
452 | case AMDGPU_INFO_NUM_EVICTIONS: |
453 | ui64 = atomic64_read(&adev->num_evictions); | |
454 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
68e2c5ff MO |
455 | case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: |
456 | ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); | |
457 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
d38ceaf9 | 458 | case AMDGPU_INFO_VRAM_USAGE: |
3c848bb3 | 459 | ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); |
d38ceaf9 AD |
460 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
461 | case AMDGPU_INFO_VIS_VRAM_USAGE: | |
3c848bb3 | 462 | ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); |
d38ceaf9 AD |
463 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
464 | case AMDGPU_INFO_GTT_USAGE: | |
9255d77d | 465 | ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); |
d38ceaf9 AD |
466 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
467 | case AMDGPU_INFO_GDS_CONFIG: { | |
468 | struct drm_amdgpu_info_gds gds_info; | |
469 | ||
c92b90cc | 470 | memset(&gds_info, 0, sizeof(gds_info)); |
d38ceaf9 AD |
471 | gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; |
472 | gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; | |
473 | gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; | |
474 | gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; | |
475 | gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; | |
476 | gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; | |
477 | gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; | |
478 | return copy_to_user(out, &gds_info, | |
479 | min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; | |
480 | } | |
481 | case AMDGPU_INFO_VRAM_GTT: { | |
482 | struct drm_amdgpu_info_vram_gtt vram_gtt; | |
483 | ||
484 | vram_gtt.vram_size = adev->mc.real_vram_size; | |
7c0ecda1 | 485 | vram_gtt.vram_size -= adev->vram_pin_size; |
d38ceaf9 | 486 | vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; |
e131b914 | 487 | vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); |
09628c3f CK |
488 | vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; |
489 | vram_gtt.gtt_size *= PAGE_SIZE; | |
d38ceaf9 AD |
490 | vram_gtt.gtt_size -= adev->gart_pin_size; |
491 | return copy_to_user(out, &vram_gtt, | |
492 | min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; | |
493 | } | |
e0adf6c8 JZ |
494 | case AMDGPU_INFO_MEMORY: { |
495 | struct drm_amdgpu_memory_info mem; | |
496 | ||
497 | memset(&mem, 0, sizeof(mem)); | |
498 | mem.vram.total_heap_size = adev->mc.real_vram_size; | |
499 | mem.vram.usable_heap_size = | |
500 | adev->mc.real_vram_size - adev->vram_pin_size; | |
3c848bb3 CK |
501 | mem.vram.heap_usage = |
502 | amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); | |
e0adf6c8 JZ |
503 | mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; |
504 | ||
505 | mem.cpu_accessible_vram.total_heap_size = | |
506 | adev->mc.visible_vram_size; | |
507 | mem.cpu_accessible_vram.usable_heap_size = | |
508 | adev->mc.visible_vram_size - | |
509 | (adev->vram_pin_size - adev->invisible_pin_size); | |
510 | mem.cpu_accessible_vram.heap_usage = | |
3c848bb3 | 511 | amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); |
e0adf6c8 JZ |
512 | mem.cpu_accessible_vram.max_allocation = |
513 | mem.cpu_accessible_vram.usable_heap_size * 3 / 4; | |
514 | ||
09628c3f CK |
515 | mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; |
516 | mem.gtt.total_heap_size *= PAGE_SIZE; | |
517 | mem.gtt.usable_heap_size = mem.gtt.total_heap_size | |
518 | - adev->gart_pin_size; | |
9255d77d CK |
519 | mem.gtt.heap_usage = |
520 | amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); | |
e0adf6c8 JZ |
521 | mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; |
522 | ||
523 | return copy_to_user(out, &mem, | |
524 | min((size_t)size, sizeof(mem))) | |
cfa32556 JZ |
525 | ? -EFAULT : 0; |
526 | } | |
d38ceaf9 | 527 | case AMDGPU_INFO_READ_MMR_REG: { |
0d2edd37 | 528 | unsigned n, alloc_size; |
d38ceaf9 AD |
529 | uint32_t *regs; |
530 | unsigned se_num = (info->read_mmr_reg.instance >> | |
531 | AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & | |
532 | AMDGPU_INFO_MMR_SE_INDEX_MASK; | |
533 | unsigned sh_num = (info->read_mmr_reg.instance >> | |
534 | AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & | |
535 | AMDGPU_INFO_MMR_SH_INDEX_MASK; | |
536 | ||
537 | /* set full masks if the userspace set all bits | |
538 | * in the bitfields */ | |
539 | if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) | |
540 | se_num = 0xffffffff; | |
541 | if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) | |
542 | sh_num = 0xffffffff; | |
543 | ||
0d2edd37 | 544 | regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); |
d38ceaf9 AD |
545 | if (!regs) |
546 | return -ENOMEM; | |
0d2edd37 | 547 | alloc_size = info->read_mmr_reg.count * sizeof(*regs); |
d38ceaf9 AD |
548 | |
549 | for (i = 0; i < info->read_mmr_reg.count; i++) | |
550 | if (amdgpu_asic_read_register(adev, se_num, sh_num, | |
551 | info->read_mmr_reg.dword_offset + i, | |
552 | ®s[i])) { | |
553 | DRM_DEBUG_KMS("unallowed offset %#x\n", | |
554 | info->read_mmr_reg.dword_offset + i); | |
555 | kfree(regs); | |
556 | return -EFAULT; | |
557 | } | |
558 | n = copy_to_user(out, regs, min(size, alloc_size)); | |
559 | kfree(regs); | |
560 | return n ? -EFAULT : 0; | |
561 | } | |
562 | case AMDGPU_INFO_DEV_INFO: { | |
c193fa91 | 563 | struct drm_amdgpu_info_device dev_info = {}; |
d38ceaf9 AD |
564 | |
565 | dev_info.device_id = dev->pdev->device; | |
566 | dev_info.chip_rev = adev->rev_id; | |
567 | dev_info.external_rev = adev->external_rev_id; | |
568 | dev_info.pci_rev = dev->pdev->revision; | |
569 | dev_info.family = adev->family; | |
570 | dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; | |
571 | dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; | |
572 | /* return all clocks in KHz */ | |
573 | dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; | |
32bf7106 | 574 | if (adev->pm.dpm_enabled) { |
1304f0c7 EQ |
575 | dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; |
576 | dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; | |
32bf7106 | 577 | } else { |
2014bc3f XY |
578 | dev_info.max_engine_clock = adev->clock.default_sclk * 10; |
579 | dev_info.max_memory_clock = adev->clock.default_mclk * 10; | |
32bf7106 | 580 | } |
d38ceaf9 | 581 | dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; |
0b10029d AD |
582 | dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * |
583 | adev->gfx.config.max_shader_engines; | |
d38ceaf9 AD |
584 | dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; |
585 | dev_info._pad = 0; | |
586 | dev_info.ids_flags = 0; | |
2f7d10b3 | 587 | if (adev->flags & AMD_IS_APU) |
d38ceaf9 | 588 | dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; |
aafcafa0 ML |
589 | if (amdgpu_sriov_vf(adev)) |
590 | dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; | |
d38ceaf9 | 591 | dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; |
02b70c8c | 592 | dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; |
c548b345 | 593 | dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); |
e618d306 | 594 | dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; |
d38ceaf9 | 595 | dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; |
7dae69a2 AD |
596 | dev_info.cu_active_number = adev->gfx.cu_info.number; |
597 | dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; | |
a101a899 | 598 | dev_info.ce_ram_size = adev->gfx.ce_ram_size; |
dbfe85ea FC |
599 | memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], |
600 | sizeof(adev->gfx.cu_info.ao_cu_bitmap)); | |
7dae69a2 AD |
601 | memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], |
602 | sizeof(adev->gfx.cu_info.bitmap)); | |
81c59f54 KW |
603 | dev_info.vram_type = adev->mc.vram_type; |
604 | dev_info.vram_bit_width = adev->mc.vram_width; | |
fa92754e | 605 | dev_info.vce_harvest_config = adev->vce.harvest_config; |
df6e2c4a JZ |
606 | dev_info.gc_double_offchip_lds_buf = |
607 | adev->gfx.config.double_offchip_lds_buf; | |
d38ceaf9 | 608 | |
bce23e00 | 609 | if (amdgpu_ngg) { |
af8baf15 GR |
610 | dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; |
611 | dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; | |
612 | dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; | |
613 | dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; | |
614 | dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; | |
615 | dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; | |
616 | dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; | |
617 | dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; | |
bce23e00 | 618 | } |
408bfe7c JZ |
619 | dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; |
620 | dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; | |
621 | dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; | |
622 | dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; | |
623 | dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; | |
624 | dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; | |
f47b77b4 | 625 | dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; |
bce23e00 | 626 | |
d38ceaf9 AD |
627 | return copy_to_user(out, &dev_info, |
628 | min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; | |
629 | } | |
07fecde5 AD |
630 | case AMDGPU_INFO_VCE_CLOCK_TABLE: { |
631 | unsigned i; | |
632 | struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; | |
633 | struct amd_vce_state *vce_state; | |
634 | ||
635 | for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { | |
636 | vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); | |
637 | if (vce_state) { | |
638 | vce_clk_table.entries[i].sclk = vce_state->sclk; | |
639 | vce_clk_table.entries[i].mclk = vce_state->mclk; | |
640 | vce_clk_table.entries[i].eclk = vce_state->evclk; | |
641 | vce_clk_table.num_valid_entries++; | |
642 | } | |
643 | } | |
644 | ||
645 | return copy_to_user(out, &vce_clk_table, | |
646 | min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; | |
647 | } | |
40ee5888 EQ |
648 | case AMDGPU_INFO_VBIOS: { |
649 | uint32_t bios_size = adev->bios_size; | |
650 | ||
651 | switch (info->vbios_info.type) { | |
652 | case AMDGPU_INFO_VBIOS_SIZE: | |
653 | return copy_to_user(out, &bios_size, | |
654 | min((size_t)size, sizeof(bios_size))) | |
655 | ? -EFAULT : 0; | |
656 | case AMDGPU_INFO_VBIOS_IMAGE: { | |
657 | uint8_t *bios; | |
658 | uint32_t bios_offset = info->vbios_info.offset; | |
659 | ||
660 | if (bios_offset >= bios_size) | |
661 | return -EINVAL; | |
662 | ||
663 | bios = adev->bios + bios_offset; | |
664 | return copy_to_user(out, bios, | |
665 | min((size_t)size, (size_t)(bios_size - bios_offset))) | |
666 | ? -EFAULT : 0; | |
667 | } | |
668 | default: | |
669 | DRM_DEBUG_KMS("Invalid request %d\n", | |
670 | info->vbios_info.type); | |
671 | return -EINVAL; | |
672 | } | |
673 | } | |
44879b62 AN |
674 | case AMDGPU_INFO_NUM_HANDLES: { |
675 | struct drm_amdgpu_info_num_handles handle; | |
676 | ||
677 | switch (info->query_hw_ip.type) { | |
678 | case AMDGPU_HW_IP_UVD: | |
679 | /* Starting Polaris, we support unlimited UVD handles */ | |
680 | if (adev->asic_type < CHIP_POLARIS10) { | |
681 | handle.uvd_max_handles = adev->uvd.max_handles; | |
682 | handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); | |
683 | ||
684 | return copy_to_user(out, &handle, | |
685 | min((size_t)size, sizeof(handle))) ? -EFAULT : 0; | |
686 | } else { | |
687 | return -ENODATA; | |
688 | } | |
689 | ||
690 | break; | |
691 | default: | |
692 | return -EINVAL; | |
693 | } | |
694 | } | |
5ebbac4b AD |
695 | case AMDGPU_INFO_SENSOR: { |
696 | struct pp_gpu_power query = {0}; | |
697 | int query_size = sizeof(query); | |
698 | ||
699 | if (amdgpu_dpm == 0) | |
700 | return -ENOENT; | |
701 | ||
702 | switch (info->sensor_info.type) { | |
703 | case AMDGPU_INFO_SENSOR_GFX_SCLK: | |
704 | /* get sclk in Mhz */ | |
705 | if (amdgpu_dpm_read_sensor(adev, | |
706 | AMDGPU_PP_SENSOR_GFX_SCLK, | |
707 | (void *)&ui32, &ui32_size)) { | |
708 | return -EINVAL; | |
709 | } | |
710 | ui32 /= 100; | |
711 | break; | |
712 | case AMDGPU_INFO_SENSOR_GFX_MCLK: | |
713 | /* get mclk in Mhz */ | |
714 | if (amdgpu_dpm_read_sensor(adev, | |
715 | AMDGPU_PP_SENSOR_GFX_MCLK, | |
716 | (void *)&ui32, &ui32_size)) { | |
717 | return -EINVAL; | |
718 | } | |
719 | ui32 /= 100; | |
720 | break; | |
721 | case AMDGPU_INFO_SENSOR_GPU_TEMP: | |
722 | /* get temperature in millidegrees C */ | |
723 | if (amdgpu_dpm_read_sensor(adev, | |
724 | AMDGPU_PP_SENSOR_GPU_TEMP, | |
725 | (void *)&ui32, &ui32_size)) { | |
726 | return -EINVAL; | |
727 | } | |
728 | break; | |
729 | case AMDGPU_INFO_SENSOR_GPU_LOAD: | |
730 | /* get GPU load */ | |
731 | if (amdgpu_dpm_read_sensor(adev, | |
732 | AMDGPU_PP_SENSOR_GPU_LOAD, | |
733 | (void *)&ui32, &ui32_size)) { | |
734 | return -EINVAL; | |
735 | } | |
736 | break; | |
737 | case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: | |
738 | /* get average GPU power */ | |
739 | if (amdgpu_dpm_read_sensor(adev, | |
740 | AMDGPU_PP_SENSOR_GPU_POWER, | |
741 | (void *)&query, &query_size)) { | |
742 | return -EINVAL; | |
743 | } | |
744 | ui32 = query.average_gpu_power >> 8; | |
745 | break; | |
746 | case AMDGPU_INFO_SENSOR_VDDNB: | |
747 | /* get VDDNB in millivolts */ | |
748 | if (amdgpu_dpm_read_sensor(adev, | |
749 | AMDGPU_PP_SENSOR_VDDNB, | |
750 | (void *)&ui32, &ui32_size)) { | |
751 | return -EINVAL; | |
752 | } | |
753 | break; | |
754 | case AMDGPU_INFO_SENSOR_VDDGFX: | |
755 | /* get VDDGFX in millivolts */ | |
756 | if (amdgpu_dpm_read_sensor(adev, | |
757 | AMDGPU_PP_SENSOR_VDDGFX, | |
758 | (void *)&ui32, &ui32_size)) { | |
759 | return -EINVAL; | |
760 | } | |
761 | break; | |
762 | default: | |
763 | DRM_DEBUG_KMS("Invalid request %d\n", | |
764 | info->sensor_info.type); | |
765 | return -EINVAL; | |
766 | } | |
767 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
768 | } | |
1f7251b7 CK |
769 | case AMDGPU_INFO_VRAM_LOST_COUNTER: |
770 | ui32 = atomic_read(&adev->vram_lost_counter); | |
771 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
d38ceaf9 AD |
772 | default: |
773 | DRM_DEBUG_KMS("Invalid request %d\n", info->query); | |
774 | return -EINVAL; | |
775 | } | |
776 | return 0; | |
777 | } | |
778 | ||
779 | ||
780 | /* | |
781 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
782 | */ | |
783 | /** | |
8b7530b1 | 784 | * amdgpu_driver_lastclose_kms - drm callback for last close |
d38ceaf9 AD |
785 | * |
786 | * @dev: drm dev pointer | |
787 | * | |
1694467b | 788 | * Switch vga_switcheroo state after last close (all asics). |
d38ceaf9 AD |
789 | */ |
790 | void amdgpu_driver_lastclose_kms(struct drm_device *dev) | |
791 | { | |
8b7530b1 AD |
792 | struct amdgpu_device *adev = dev->dev_private; |
793 | ||
794 | amdgpu_fbdev_restore_mode(adev); | |
d38ceaf9 AD |
795 | vga_switcheroo_process_delayed_switch(); |
796 | } | |
797 | ||
798 | /** | |
799 | * amdgpu_driver_open_kms - drm callback for open | |
800 | * | |
801 | * @dev: drm dev pointer | |
802 | * @file_priv: drm file | |
803 | * | |
804 | * On device open, init vm on cayman+ (all asics). | |
805 | * Returns 0 on success, error on failure. | |
806 | */ | |
807 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |
808 | { | |
809 | struct amdgpu_device *adev = dev->dev_private; | |
810 | struct amdgpu_fpriv *fpriv; | |
811 | int r; | |
812 | ||
813 | file_priv->driver_priv = NULL; | |
814 | ||
815 | r = pm_runtime_get_sync(dev->dev); | |
816 | if (r < 0) | |
817 | return r; | |
818 | ||
819 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
dc08267a AD |
820 | if (unlikely(!fpriv)) { |
821 | r = -ENOMEM; | |
822 | goto out_suspend; | |
823 | } | |
d38ceaf9 | 824 | |
9a4b7d4c | 825 | r = amdgpu_vm_init(adev, &fpriv->vm, |
02208441 | 826 | AMDGPU_VM_CONTEXT_GFX, 0); |
dc08267a AD |
827 | if (r) { |
828 | kfree(fpriv); | |
829 | goto out_suspend; | |
830 | } | |
d38ceaf9 | 831 | |
b85891bd JZ |
832 | fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); |
833 | if (!fpriv->prt_va) { | |
834 | r = -ENOMEM; | |
835 | amdgpu_vm_fini(adev, &fpriv->vm); | |
836 | kfree(fpriv); | |
837 | goto out_suspend; | |
838 | } | |
839 | ||
2493664f | 840 | if (amdgpu_sriov_vf(adev)) { |
0f4b3c68 | 841 | r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); |
ab5d6227 ML |
842 | if (r) { |
843 | amdgpu_vm_fini(adev, &fpriv->vm); | |
844 | kfree(fpriv); | |
2493664f | 845 | goto out_suspend; |
ab5d6227 | 846 | } |
2493664f ML |
847 | } |
848 | ||
d38ceaf9 AD |
849 | mutex_init(&fpriv->bo_list_lock); |
850 | idr_init(&fpriv->bo_list_handles); | |
851 | ||
efd4ccb5 | 852 | amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); |
d38ceaf9 AD |
853 | |
854 | file_priv->driver_priv = fpriv; | |
855 | ||
dc08267a | 856 | out_suspend: |
d38ceaf9 AD |
857 | pm_runtime_mark_last_busy(dev->dev); |
858 | pm_runtime_put_autosuspend(dev->dev); | |
d38ceaf9 AD |
859 | |
860 | return r; | |
861 | } | |
862 | ||
863 | /** | |
864 | * amdgpu_driver_postclose_kms - drm callback for post close | |
865 | * | |
866 | * @dev: drm dev pointer | |
867 | * @file_priv: drm file | |
868 | * | |
869 | * On device post close, tear down vm on cayman+ (all asics). | |
870 | */ | |
871 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
872 | struct drm_file *file_priv) | |
873 | { | |
874 | struct amdgpu_device *adev = dev->dev_private; | |
875 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
876 | struct amdgpu_bo_list *list; | |
877 | int handle; | |
878 | ||
879 | if (!fpriv) | |
880 | return; | |
881 | ||
04e30c9c DV |
882 | pm_runtime_get_sync(dev->dev); |
883 | ||
02537d63 CK |
884 | amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); |
885 | ||
ef80d30b LL |
886 | if (adev->asic_type != CHIP_RAVEN) { |
887 | amdgpu_uvd_free_handles(adev, file_priv); | |
888 | amdgpu_vce_free_handles(adev, file_priv); | |
889 | } | |
cd437e37 | 890 | |
b85891bd JZ |
891 | amdgpu_vm_bo_rmv(adev, fpriv->prt_va); |
892 | ||
2493664f ML |
893 | if (amdgpu_sriov_vf(adev)) { |
894 | /* TODO: how to handle reserve failure */ | |
c81a1a74 | 895 | BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); |
0f4b3c68 CK |
896 | amdgpu_vm_bo_rmv(adev, fpriv->csa_va); |
897 | fpriv->csa_va = NULL; | |
2493664f ML |
898 | amdgpu_bo_unreserve(adev->virt.csa_obj); |
899 | } | |
900 | ||
d38ceaf9 AD |
901 | amdgpu_vm_fini(adev, &fpriv->vm); |
902 | ||
903 | idr_for_each_entry(&fpriv->bo_list_handles, list, handle) | |
904 | amdgpu_bo_list_free(list); | |
905 | ||
906 | idr_destroy(&fpriv->bo_list_handles); | |
907 | mutex_destroy(&fpriv->bo_list_lock); | |
908 | ||
d38ceaf9 AD |
909 | kfree(fpriv); |
910 | file_priv->driver_priv = NULL; | |
d6bda7b4 AD |
911 | |
912 | pm_runtime_mark_last_busy(dev->dev); | |
913 | pm_runtime_put_autosuspend(dev->dev); | |
d38ceaf9 AD |
914 | } |
915 | ||
d38ceaf9 AD |
916 | /* |
917 | * VBlank related functions. | |
918 | */ | |
919 | /** | |
920 | * amdgpu_get_vblank_counter_kms - get frame count | |
921 | * | |
922 | * @dev: drm dev pointer | |
88e72717 | 923 | * @pipe: crtc to get the frame count from |
d38ceaf9 AD |
924 | * |
925 | * Gets the frame count on the requested crtc (all asics). | |
926 | * Returns frame count on success, -EINVAL on failure. | |
927 | */ | |
88e72717 | 928 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
929 | { |
930 | struct amdgpu_device *adev = dev->dev_private; | |
8e36f9d3 AD |
931 | int vpos, hpos, stat; |
932 | u32 count; | |
d38ceaf9 | 933 | |
88e72717 TR |
934 | if (pipe >= adev->mode_info.num_crtc) { |
935 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
d38ceaf9 AD |
936 | return -EINVAL; |
937 | } | |
938 | ||
8e36f9d3 AD |
939 | /* The hw increments its frame counter at start of vsync, not at start |
940 | * of vblank, as is required by DRM core vblank counter handling. | |
941 | * Cook the hw count here to make it appear to the caller as if it | |
942 | * incremented at start of vblank. We measure distance to start of | |
943 | * vblank in vpos. vpos therefore will be >= 0 between start of vblank | |
944 | * and start of vsync, so vpos >= 0 means to bump the hw frame counter | |
945 | * result by 1 to give the proper appearance to caller. | |
946 | */ | |
947 | if (adev->mode_info.crtcs[pipe]) { | |
948 | /* Repeat readout if needed to provide stable result if | |
949 | * we cross start of vsync during the queries. | |
950 | */ | |
951 | do { | |
952 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
953 | /* Ask amdgpu_get_crtc_scanoutpos to return vpos as | |
954 | * distance to start of vblank, instead of regular | |
955 | * vertical scanout pos. | |
956 | */ | |
957 | stat = amdgpu_get_crtc_scanoutpos( | |
958 | dev, pipe, GET_DISTANCE_TO_VBLANKSTART, | |
959 | &vpos, &hpos, NULL, NULL, | |
960 | &adev->mode_info.crtcs[pipe]->base.hwmode); | |
961 | } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); | |
962 | ||
963 | if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != | |
964 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { | |
965 | DRM_DEBUG_VBL("Query failed! stat %d\n", stat); | |
966 | } else { | |
967 | DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", | |
968 | pipe, vpos); | |
969 | ||
970 | /* Bump counter if we are at >= leading edge of vblank, | |
971 | * but before vsync where vpos would turn negative and | |
972 | * the hw counter really increments. | |
973 | */ | |
974 | if (vpos >= 0) | |
975 | count++; | |
976 | } | |
977 | } else { | |
978 | /* Fallback to use value as is. */ | |
979 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
980 | DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); | |
981 | } | |
982 | ||
983 | return count; | |
d38ceaf9 AD |
984 | } |
985 | ||
986 | /** | |
987 | * amdgpu_enable_vblank_kms - enable vblank interrupt | |
988 | * | |
989 | * @dev: drm dev pointer | |
88e72717 | 990 | * @pipe: crtc to enable vblank interrupt for |
d38ceaf9 AD |
991 | * |
992 | * Enable the interrupt on the requested crtc (all asics). | |
993 | * Returns 0 on success, -EINVAL on failure. | |
994 | */ | |
88e72717 | 995 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
996 | { |
997 | struct amdgpu_device *adev = dev->dev_private; | |
88e72717 | 998 | int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
999 | |
1000 | return amdgpu_irq_get(adev, &adev->crtc_irq, idx); | |
1001 | } | |
1002 | ||
1003 | /** | |
1004 | * amdgpu_disable_vblank_kms - disable vblank interrupt | |
1005 | * | |
1006 | * @dev: drm dev pointer | |
88e72717 | 1007 | * @pipe: crtc to disable vblank interrupt for |
d38ceaf9 AD |
1008 | * |
1009 | * Disable the interrupt on the requested crtc (all asics). | |
1010 | */ | |
88e72717 | 1011 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
1012 | { |
1013 | struct amdgpu_device *adev = dev->dev_private; | |
88e72717 | 1014 | int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
1015 | |
1016 | amdgpu_irq_put(adev, &adev->crtc_irq, idx); | |
1017 | } | |
1018 | ||
d38ceaf9 | 1019 | const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { |
f8c47144 DV |
1020 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
1021 | DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
cfbcacf4 | 1022 | DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
52c6a62c | 1023 | DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), |
f8c47144 | 1024 | DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
7ca24cf2 | 1025 | DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
d38ceaf9 | 1026 | /* KMS */ |
f8c47144 DV |
1027 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
1028 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1029 | DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1030 | DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1031 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
eef18a82 | 1032 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
f8c47144 DV |
1033 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
1034 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1035 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
4562236b | 1036 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) |
d38ceaf9 | 1037 | }; |
f498d9ed | 1038 | const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); |
50ab2533 HR |
1039 | |
1040 | /* | |
1041 | * Debugfs info | |
1042 | */ | |
1043 | #if defined(CONFIG_DEBUG_FS) | |
1044 | ||
1045 | static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) | |
1046 | { | |
1047 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1048 | struct drm_device *dev = node->minor->dev; | |
1049 | struct amdgpu_device *adev = dev->dev_private; | |
1050 | struct drm_amdgpu_info_firmware fw_info; | |
1051 | struct drm_amdgpu_query_fw query_fw; | |
1052 | int ret, i; | |
1053 | ||
1054 | /* VCE */ | |
1055 | query_fw.fw_type = AMDGPU_INFO_FW_VCE; | |
1056 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1057 | if (ret) | |
1058 | return ret; | |
1059 | seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", | |
1060 | fw_info.feature, fw_info.ver); | |
1061 | ||
1062 | /* UVD */ | |
1063 | query_fw.fw_type = AMDGPU_INFO_FW_UVD; | |
1064 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1065 | if (ret) | |
1066 | return ret; | |
1067 | seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", | |
1068 | fw_info.feature, fw_info.ver); | |
1069 | ||
1070 | /* GMC */ | |
1071 | query_fw.fw_type = AMDGPU_INFO_FW_GMC; | |
1072 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1073 | if (ret) | |
1074 | return ret; | |
1075 | seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", | |
1076 | fw_info.feature, fw_info.ver); | |
1077 | ||
1078 | /* ME */ | |
1079 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; | |
1080 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1081 | if (ret) | |
1082 | return ret; | |
1083 | seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", | |
1084 | fw_info.feature, fw_info.ver); | |
1085 | ||
1086 | /* PFP */ | |
1087 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; | |
1088 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1089 | if (ret) | |
1090 | return ret; | |
1091 | seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", | |
1092 | fw_info.feature, fw_info.ver); | |
1093 | ||
1094 | /* CE */ | |
1095 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; | |
1096 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1097 | if (ret) | |
1098 | return ret; | |
1099 | seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", | |
1100 | fw_info.feature, fw_info.ver); | |
1101 | ||
1102 | /* RLC */ | |
1103 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; | |
1104 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1105 | if (ret) | |
1106 | return ret; | |
1107 | seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", | |
1108 | fw_info.feature, fw_info.ver); | |
1109 | ||
1110 | /* MEC */ | |
1111 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; | |
1112 | query_fw.index = 0; | |
1113 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1114 | if (ret) | |
1115 | return ret; | |
1116 | seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", | |
1117 | fw_info.feature, fw_info.ver); | |
1118 | ||
1119 | /* MEC2 */ | |
1120 | if (adev->asic_type == CHIP_KAVERI || | |
1121 | (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { | |
1122 | query_fw.index = 1; | |
1123 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1124 | if (ret) | |
1125 | return ret; | |
1126 | seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", | |
1127 | fw_info.feature, fw_info.ver); | |
1128 | } | |
1129 | ||
6a7ed07e HR |
1130 | /* PSP SOS */ |
1131 | query_fw.fw_type = AMDGPU_INFO_FW_SOS; | |
1132 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1133 | if (ret) | |
1134 | return ret; | |
1135 | seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", | |
1136 | fw_info.feature, fw_info.ver); | |
1137 | ||
1138 | ||
1139 | /* PSP ASD */ | |
1140 | query_fw.fw_type = AMDGPU_INFO_FW_ASD; | |
1141 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1142 | if (ret) | |
1143 | return ret; | |
1144 | seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", | |
1145 | fw_info.feature, fw_info.ver); | |
1146 | ||
50ab2533 HR |
1147 | /* SMC */ |
1148 | query_fw.fw_type = AMDGPU_INFO_FW_SMC; | |
1149 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1150 | if (ret) | |
1151 | return ret; | |
1152 | seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", | |
1153 | fw_info.feature, fw_info.ver); | |
1154 | ||
1155 | /* SDMA */ | |
1156 | query_fw.fw_type = AMDGPU_INFO_FW_SDMA; | |
1157 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
1158 | query_fw.index = i; | |
1159 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1160 | if (ret) | |
1161 | return ret; | |
1162 | seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", | |
1163 | i, fw_info.feature, fw_info.ver); | |
1164 | } | |
1165 | ||
1166 | return 0; | |
1167 | } | |
1168 | ||
1169 | static const struct drm_info_list amdgpu_firmware_info_list[] = { | |
1170 | {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, | |
1171 | }; | |
1172 | #endif | |
1173 | ||
1174 | int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) | |
1175 | { | |
1176 | #if defined(CONFIG_DEBUG_FS) | |
1177 | return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, | |
1178 | ARRAY_SIZE(amdgpu_firmware_info_list)); | |
1179 | #else | |
1180 | return 0; | |
1181 | #endif | |
1182 | } |