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drm/amdgpu/virt: implement VI virt operation interfaces
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_kms.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33
34#include <linux/vga_switcheroo.h>
35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
130e0371 37#include "amdgpu_amdkfd.h"
d38ceaf9
AD		 38
39#if defined(CONFIG_VGA_SWITCHEROO)
40bool amdgpu_has_atpx(void);
41#else
42static inline bool amdgpu_has_atpx(void) { return false; }
43#endif
44
45/**
46 * amdgpu_driver_unload_kms - Main unload function for KMS.
47 *
48 * @dev: drm dev pointer
49 *
50 * This is the main unload function for KMS (all asics).
51 * Returns 0 on success.
52 */
11b3c20b 53void amdgpu_driver_unload_kms(struct drm_device *dev)
d38ceaf9
AD		 54{
55 struct amdgpu_device *adev = dev->dev_private;
56
57 if (adev == NULL)
11b3c20b 58 return;
d38ceaf9
AD		 59
60 if (adev->rmmio == NULL)
61 goto done_free;
62
4a788547
LW		 63 if (amdgpu_device_is_px(dev)) {
64 pm_runtime_get_sync(dev->dev);
6ce62d8b 65 pm_runtime_forbid(dev->dev);
4a788547 66 }
d38ceaf9 67
130e0371
OG		 68 amdgpu_amdkfd_device_fini(adev);
69
d38ceaf9
AD		 70 amdgpu_acpi_fini(adev);
71
72 amdgpu_device_fini(adev);
73
74done_free:
75 kfree(adev);
76 dev->dev_private = NULL;
d38ceaf9
AD		 77}
78
79/**
80 * amdgpu_driver_load_kms - Main load function for KMS.
81 *
82 * @dev: drm dev pointer
83 * @flags: device flags
84 *
85 * This is the main load function for KMS (all asics).
86 * Returns 0 on success, error on failure.
87 */
88int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
89{
90 struct amdgpu_device *adev;
91 int r, acpi_status;
92
93 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
94 if (adev == NULL) {
95 return -ENOMEM;
96 }
97 dev->dev_private = (void *)adev;
98
99 if ((amdgpu_runtime_pm != 0) &&
100 amdgpu_has_atpx() &&
84b1528e
AD		 101 (amdgpu_is_atpx_hybrid() ||
102 amdgpu_has_atpx_dgpu_power_cntl()) &&
2f7d10b3
JZ		 103 ((flags & AMD_IS_APU) == 0))
104 flags |= AMD_IS_PX;
d38ceaf9
AD		 105
106 /* amdgpu_device_init should report only fatal error
107 * like memory allocation failure or iomapping failure,
108 * or memory manager initialization failure, it must
109 * properly initialize the GPU MC controller and permit
110 * VRAM allocation
111 */
112 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
113 if (r) {
114 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
115 goto out;
116 }
117
118 /* Call ACPI methods: require modeset init
119 * but failure is not fatal
120 */
121 if (!r) {
122 acpi_status = amdgpu_acpi_init(adev);
123 if (acpi_status)
124 dev_dbg(&dev->pdev->dev,
125 "Error during ACPI methods call\n");
126 }
127
130e0371
OG		 128 amdgpu_amdkfd_load_interface(adev);
129 amdgpu_amdkfd_device_probe(adev);
130 amdgpu_amdkfd_device_init(adev);
131
d38ceaf9
AD		 132 if (amdgpu_device_is_px(dev)) {
133 pm_runtime_use_autosuspend(dev->dev);
134 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
135 pm_runtime_set_active(dev->dev);
136 pm_runtime_allow(dev->dev);
137 pm_runtime_mark_last_busy(dev->dev);
138 pm_runtime_put_autosuspend(dev->dev);
139 }
140
141out:
c9c9bbd7
LW		 142 if (r) {
143 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
144 if (adev->rmmio && amdgpu_device_is_px(dev))
145 pm_runtime_put_noidle(dev->dev);
d38ceaf9 146 amdgpu_driver_unload_kms(dev);
c9c9bbd7 147 }
d38ceaf9
AD		 148
149 return r;
150}
151
000cab9a
HR		 152static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
153 struct drm_amdgpu_query_fw *query_fw,
154 struct amdgpu_device *adev)
155{
156 switch (query_fw->fw_type) {
157 case AMDGPU_INFO_FW_VCE:
158 fw_info->ver = adev->vce.fw_version;
159 fw_info->feature = adev->vce.fb_version;
160 break;
161 case AMDGPU_INFO_FW_UVD:
162 fw_info->ver = adev->uvd.fw_version;
163 fw_info->feature = 0;
164 break;
165 case AMDGPU_INFO_FW_GMC:
166 fw_info->ver = adev->mc.fw_version;
167 fw_info->feature = 0;
168 break;
169 case AMDGPU_INFO_FW_GFX_ME:
170 fw_info->ver = adev->gfx.me_fw_version;
171 fw_info->feature = adev->gfx.me_feature_version;
172 break;
173 case AMDGPU_INFO_FW_GFX_PFP:
174 fw_info->ver = adev->gfx.pfp_fw_version;
175 fw_info->feature = adev->gfx.pfp_feature_version;
176 break;
177 case AMDGPU_INFO_FW_GFX_CE:
178 fw_info->ver = adev->gfx.ce_fw_version;
179 fw_info->feature = adev->gfx.ce_feature_version;
180 break;
181 case AMDGPU_INFO_FW_GFX_RLC:
182 fw_info->ver = adev->gfx.rlc_fw_version;
183 fw_info->feature = adev->gfx.rlc_feature_version;
184 break;
185 case AMDGPU_INFO_FW_GFX_MEC:
186 if (query_fw->index == 0) {
187 fw_info->ver = adev->gfx.mec_fw_version;
188 fw_info->feature = adev->gfx.mec_feature_version;
189 } else if (query_fw->index == 1) {
190 fw_info->ver = adev->gfx.mec2_fw_version;
191 fw_info->feature = adev->gfx.mec2_feature_version;
192 } else
193 return -EINVAL;
194 break;
195 case AMDGPU_INFO_FW_SMC:
196 fw_info->ver = adev->pm.fw_version;
197 fw_info->feature = 0;
198 break;
199 case AMDGPU_INFO_FW_SDMA:
200 if (query_fw->index >= adev->sdma.num_instances)
201 return -EINVAL;
202 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
203 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
204 break;
205 default:
206 return -EINVAL;
207 }
208 return 0;
209}
210
d38ceaf9
AD		 211/*
212 * Userspace get information ioctl
213 */
214/**
215 * amdgpu_info_ioctl - answer a device specific request.
216 *
217 * @adev: amdgpu device pointer
218 * @data: request object
219 * @filp: drm filp
220 *
221 * This function is used to pass device specific parameters to the userspace
222 * drivers. Examples include: pci device id, pipeline parms, tiling params,
223 * etc. (all asics).
224 * Returns 0 on success, -EINVAL on failure.
225 */
226static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
227{
228 struct amdgpu_device *adev = dev->dev_private;
229 struct drm_amdgpu_info *info = data;
230 struct amdgpu_mode_info *minfo = &adev->mode_info;
231 void __user *out = (void __user *)(long)info->return_pointer;
232 uint32_t size = info->return_size;
233 struct drm_crtc *crtc;
234 uint32_t ui32 = 0;
235 uint64_t ui64 = 0;
236 int i, found;
237
238 if (!info->return_size || !info->return_pointer)
239 return -EINVAL;
240
241 switch (info->query) {
242 case AMDGPU_INFO_ACCEL_WORKING:
243 ui32 = adev->accel_working;
244 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
245 case AMDGPU_INFO_CRTC_FROM_ID:
246 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
247 crtc = (struct drm_crtc *)minfo->crtcs[i];
248 if (crtc && crtc->base.id == info->mode_crtc.id) {
249 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
250 ui32 = amdgpu_crtc->crtc_id;
251 found = 1;
252 break;
253 }
254 }
255 if (!found) {
256 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
257 return -EINVAL;
258 }
259 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
260 case AMDGPU_INFO_HW_IP_INFO: {
261 struct drm_amdgpu_info_hw_ip ip = {};
5fc3aeeb 262 enum amd_ip_block_type type;
d38ceaf9 263 uint32_t ring_mask = 0;
71062f43
KW		 264 uint32_t ib_start_alignment = 0;
265 uint32_t ib_size_alignment = 0;
d38ceaf9
AD		 266
267 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
268 return -EINVAL;
269
270 switch (info->query_hw_ip.type) {
271 case AMDGPU_HW_IP_GFX:
5fc3aeeb 272 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 273 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
274 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
71062f43
KW		 275 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
276 ib_size_alignment = 8;
d38ceaf9
AD		 277 break;
278 case AMDGPU_HW_IP_COMPUTE:
5fc3aeeb 279 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 280 for (i = 0; i < adev->gfx.num_compute_rings; i++)
281 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
71062f43
KW		 282 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
283 ib_size_alignment = 8;
d38ceaf9
AD		 284 break;
285 case AMDGPU_HW_IP_DMA:
5fc3aeeb 286 type = AMD_IP_BLOCK_TYPE_SDMA;
c113ea1c
AD		 287 for (i = 0; i < adev->sdma.num_instances; i++)
288 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
71062f43
KW		 289 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
290 ib_size_alignment = 1;
d38ceaf9
AD		 291 break;
292 case AMDGPU_HW_IP_UVD:
5fc3aeeb 293 type = AMD_IP_BLOCK_TYPE_UVD;
d38ceaf9 294 ring_mask = adev->uvd.ring.ready ? 1 : 0;
71062f43 295 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
c4795ca6 296 ib_size_alignment = 16;
d38ceaf9
AD		 297 break;
298 case AMDGPU_HW_IP_VCE:
5fc3aeeb 299 type = AMD_IP_BLOCK_TYPE_VCE;
75c65480 300 for (i = 0; i < adev->vce.num_rings; i++)
d38ceaf9 301 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
71062f43 302 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
a22f803c 303 ib_size_alignment = 1;
d38ceaf9
AD		 304 break;
305 default:
306 return -EINVAL;
307 }
308
309 for (i = 0; i < adev->num_ip_blocks; i++) {
a1255107
AD		 310 if (adev->ip_blocks[i].version->type == type &&
311 adev->ip_blocks[i].status.valid) {
312 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
313 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
d38ceaf9
AD		 314 ip.capabilities_flags = 0;
315 ip.available_rings = ring_mask;
71062f43
KW		 316 ip.ib_start_alignment = ib_start_alignment;
317 ip.ib_size_alignment = ib_size_alignment;
d38ceaf9
AD		 318 break;
319 }
320 }
321 return copy_to_user(out, &ip,
322 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
323 }
324 case AMDGPU_INFO_HW_IP_COUNT: {
5fc3aeeb 325 enum amd_ip_block_type type;
d38ceaf9
AD		 326 uint32_t count = 0;
327
328 switch (info->query_hw_ip.type) {
329 case AMDGPU_HW_IP_GFX:
5fc3aeeb 330 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 331 break;
332 case AMDGPU_HW_IP_COMPUTE:
5fc3aeeb 333 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 334 break;
335 case AMDGPU_HW_IP_DMA:
5fc3aeeb 336 type = AMD_IP_BLOCK_TYPE_SDMA;
d38ceaf9
AD		 337 break;
338 case AMDGPU_HW_IP_UVD:
5fc3aeeb 339 type = AMD_IP_BLOCK_TYPE_UVD;
d38ceaf9
AD		 340 break;
341 case AMDGPU_HW_IP_VCE:
5fc3aeeb 342 type = AMD_IP_BLOCK_TYPE_VCE;
d38ceaf9
AD		 343 break;
344 default:
345 return -EINVAL;
346 }
347
348 for (i = 0; i < adev->num_ip_blocks; i++)
a1255107
AD		 349 if (adev->ip_blocks[i].version->type == type &&
350 adev->ip_blocks[i].status.valid &&
d38ceaf9
AD		 351 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
352 count++;
353
354 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
355 }
356 case AMDGPU_INFO_TIMESTAMP:
b95e31fd 357 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
d38ceaf9
AD		 358 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
359 case AMDGPU_INFO_FW_VERSION: {
360 struct drm_amdgpu_info_firmware fw_info;
000cab9a 361 int ret;
d38ceaf9
AD		 362
363 /* We only support one instance of each IP block right now. */
364 if (info->query_fw.ip_instance != 0)
365 return -EINVAL;
366
000cab9a
HR		 367 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
368 if (ret)
369 return ret;
370
d38ceaf9
AD		 371 return copy_to_user(out, &fw_info,
372 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
373 }
374 case AMDGPU_INFO_NUM_BYTES_MOVED:
375 ui64 = atomic64_read(&adev->num_bytes_moved);
376 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
83a59b63
MO		 377 case AMDGPU_INFO_NUM_EVICTIONS:
378 ui64 = atomic64_read(&adev->num_evictions);
379 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
d38ceaf9
AD		 380 case AMDGPU_INFO_VRAM_USAGE:
381 ui64 = atomic64_read(&adev->vram_usage);
382 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
383 case AMDGPU_INFO_VIS_VRAM_USAGE:
384 ui64 = atomic64_read(&adev->vram_vis_usage);
385 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
386 case AMDGPU_INFO_GTT_USAGE:
387 ui64 = atomic64_read(&adev->gtt_usage);
388 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
389 case AMDGPU_INFO_GDS_CONFIG: {
390 struct drm_amdgpu_info_gds gds_info;
391
c92b90cc 392 memset(&gds_info, 0, sizeof(gds_info));
d38ceaf9
AD		 393 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
394 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
395 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
396 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
397 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
398 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
399 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
400 return copy_to_user(out, &gds_info,
401 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
402 }
403 case AMDGPU_INFO_VRAM_GTT: {
404 struct drm_amdgpu_info_vram_gtt vram_gtt;
405
406 vram_gtt.vram_size = adev->mc.real_vram_size;
7c0ecda1 407 vram_gtt.vram_size -= adev->vram_pin_size;
d38ceaf9 408 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
e131b914 409 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
d38ceaf9
AD		 410 vram_gtt.gtt_size = adev->mc.gtt_size;
411 vram_gtt.gtt_size -= adev->gart_pin_size;
412 return copy_to_user(out, &vram_gtt,
413 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
414 }
e0adf6c8
JZ		 415 case AMDGPU_INFO_MEMORY: {
416 struct drm_amdgpu_memory_info mem;
417
418 memset(&mem, 0, sizeof(mem));
419 mem.vram.total_heap_size = adev->mc.real_vram_size;
420 mem.vram.usable_heap_size =
421 adev->mc.real_vram_size - adev->vram_pin_size;
422 mem.vram.heap_usage = atomic64_read(&adev->vram_usage);
423 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
424
425 mem.cpu_accessible_vram.total_heap_size =
426 adev->mc.visible_vram_size;
427 mem.cpu_accessible_vram.usable_heap_size =
428 adev->mc.visible_vram_size -
429 (adev->vram_pin_size - adev->invisible_pin_size);
430 mem.cpu_accessible_vram.heap_usage =
431 atomic64_read(&adev->vram_vis_usage);
432 mem.cpu_accessible_vram.max_allocation =
433 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
434
435 mem.gtt.total_heap_size = adev->mc.gtt_size;
436 mem.gtt.usable_heap_size =
437 adev->mc.gtt_size - adev->gart_pin_size;
438 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage);
439 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
440
441 return copy_to_user(out, &mem,
442 min((size_t)size, sizeof(mem)))
cfa32556
JZ		 443 ? -EFAULT : 0;
444 }
d38ceaf9 445 case AMDGPU_INFO_READ_MMR_REG: {
0d2edd37 446 unsigned n, alloc_size;
d38ceaf9
AD		 447 uint32_t *regs;
448 unsigned se_num = (info->read_mmr_reg.instance >>
449 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
450 AMDGPU_INFO_MMR_SE_INDEX_MASK;
451 unsigned sh_num = (info->read_mmr_reg.instance >>
452 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
453 AMDGPU_INFO_MMR_SH_INDEX_MASK;
454
455 /* set full masks if the userspace set all bits
456 * in the bitfields */
457 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
458 se_num = 0xffffffff;
459 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
460 sh_num = 0xffffffff;
461
0d2edd37 462 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
d38ceaf9
AD		 463 if (!regs)
464 return -ENOMEM;
0d2edd37 465 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
d38ceaf9
AD		 466
467 for (i = 0; i < info->read_mmr_reg.count; i++)
468 if (amdgpu_asic_read_register(adev, se_num, sh_num,
469 info->read_mmr_reg.dword_offset + i,
470 &regs[i])) {
471 DRM_DEBUG_KMS("unallowed offset %#x\n",
472 info->read_mmr_reg.dword_offset + i);
473 kfree(regs);
474 return -EFAULT;
475 }
476 n = copy_to_user(out, regs, min(size, alloc_size));
477 kfree(regs);
478 return n ? -EFAULT : 0;
479 }
480 case AMDGPU_INFO_DEV_INFO: {
c193fa91 481 struct drm_amdgpu_info_device dev_info = {};
d38ceaf9
AD		 482
483 dev_info.device_id = dev->pdev->device;
484 dev_info.chip_rev = adev->rev_id;
485 dev_info.external_rev = adev->external_rev_id;
486 dev_info.pci_rev = dev->pdev->revision;
487 dev_info.family = adev->family;
488 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
489 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
490 /* return all clocks in KHz */
491 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
32bf7106 492 if (adev->pm.dpm_enabled) {
1304f0c7
EQ		 493 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
494 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
32bf7106 495 } else {
d38ceaf9 496 dev_info.max_engine_clock = adev->pm.default_sclk * 10;
32bf7106
KW		 497 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
498 }
d38ceaf9 499 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
0b10029d
AD		 500 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
501 adev->gfx.config.max_shader_engines;
d38ceaf9
AD		 502 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
503 dev_info._pad = 0;
504 dev_info.ids_flags = 0;
2f7d10b3 505 if (adev->flags & AMD_IS_APU)
d38ceaf9 506 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
aafcafa0
ML		 507 if (amdgpu_sriov_vf(adev))
508 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
d38ceaf9 509 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
02b70c8c 510 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
c548b345 511 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
d38ceaf9
AD		 512 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
513 AMDGPU_GPU_PAGE_SIZE;
514 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
515
7dae69a2
AD		 516 dev_info.cu_active_number = adev->gfx.cu_info.number;
517 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
a101a899 518 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
7dae69a2
AD		 519 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
520 sizeof(adev->gfx.cu_info.bitmap));
81c59f54
KW		 521 dev_info.vram_type = adev->mc.vram_type;
522 dev_info.vram_bit_width = adev->mc.vram_width;
fa92754e 523 dev_info.vce_harvest_config = adev->vce.harvest_config;
d38ceaf9
AD		 524
525 return copy_to_user(out, &dev_info,
526 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
527 }
07fecde5
AD		 528 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
529 unsigned i;
530 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
531 struct amd_vce_state *vce_state;
532
533 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
534 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
535 if (vce_state) {
536 vce_clk_table.entries[i].sclk = vce_state->sclk;
537 vce_clk_table.entries[i].mclk = vce_state->mclk;
538 vce_clk_table.entries[i].eclk = vce_state->evclk;
539 vce_clk_table.num_valid_entries++;
540 }
541 }
542
543 return copy_to_user(out, &vce_clk_table,
544 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
545 }
40ee5888
EQ		 546 case AMDGPU_INFO_VBIOS: {
547 uint32_t bios_size = adev->bios_size;
548
549 switch (info->vbios_info.type) {
550 case AMDGPU_INFO_VBIOS_SIZE:
551 return copy_to_user(out, &bios_size,
552 min((size_t)size, sizeof(bios_size)))
553 ? -EFAULT : 0;
554 case AMDGPU_INFO_VBIOS_IMAGE: {
555 uint8_t *bios;
556 uint32_t bios_offset = info->vbios_info.offset;
557
558 if (bios_offset >= bios_size)
559 return -EINVAL;
560
561 bios = adev->bios + bios_offset;
562 return copy_to_user(out, bios,
563 min((size_t)size, (size_t)(bios_size - bios_offset)))
564 ? -EFAULT : 0;
565 }
566 default:
567 DRM_DEBUG_KMS("Invalid request %d\n",
568 info->vbios_info.type);
569 return -EINVAL;
570 }
571 }
44879b62
AN		 572 case AMDGPU_INFO_NUM_HANDLES: {
573 struct drm_amdgpu_info_num_handles handle;
574
575 switch (info->query_hw_ip.type) {
576 case AMDGPU_HW_IP_UVD:
577 /* Starting Polaris, we support unlimited UVD handles */
578 if (adev->asic_type < CHIP_POLARIS10) {
579 handle.uvd_max_handles = adev->uvd.max_handles;
580 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
581
582 return copy_to_user(out, &handle,
583 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
584 } else {
585 return -ENODATA;
586 }
587
588 break;
589 default:
590 return -EINVAL;
591 }
592 }
d38ceaf9
AD		 593 default:
594 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
595 return -EINVAL;
596 }
597 return 0;
598}
599
600
601/*
602 * Outdated mess for old drm with Xorg being in charge (void function now).
603 */
604/**
8b7530b1 605 * amdgpu_driver_lastclose_kms - drm callback for last close
d38ceaf9
AD		 606 *
607 * @dev: drm dev pointer
608 *
1694467b 609 * Switch vga_switcheroo state after last close (all asics).
d38ceaf9
AD		 610 */
611void amdgpu_driver_lastclose_kms(struct drm_device *dev)
612{
8b7530b1
AD		 613 struct amdgpu_device *adev = dev->dev_private;
614
615 amdgpu_fbdev_restore_mode(adev);
d38ceaf9
AD		 616 vga_switcheroo_process_delayed_switch();
617}
618
619/**
620 * amdgpu_driver_open_kms - drm callback for open
621 *
622 * @dev: drm dev pointer
623 * @file_priv: drm file
624 *
625 * On device open, init vm on cayman+ (all asics).
626 * Returns 0 on success, error on failure.
627 */
628int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
629{
630 struct amdgpu_device *adev = dev->dev_private;
631 struct amdgpu_fpriv *fpriv;
632 int r;
633
634 file_priv->driver_priv = NULL;
635
636 r = pm_runtime_get_sync(dev->dev);
637 if (r < 0)
638 return r;
639
640 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
dc08267a
AD		 641 if (unlikely(!fpriv)) {
642 r = -ENOMEM;
643 goto out_suspend;
644 }
d38ceaf9
AD		 645
646 r = amdgpu_vm_init(adev, &fpriv->vm);
dc08267a
AD		 647 if (r) {
648 kfree(fpriv);
649 goto out_suspend;
650 }
d38ceaf9 651
2493664f
ML		 652 if (amdgpu_sriov_vf(adev)) {
653 r = amdgpu_map_static_csa(adev, &fpriv->vm);
654 if (r)
655 goto out_suspend;
656 }
657
d38ceaf9
AD		 658 mutex_init(&fpriv->bo_list_lock);
659 idr_init(&fpriv->bo_list_handles);
660
efd4ccb5 661 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
d38ceaf9
AD		 662
663 file_priv->driver_priv = fpriv;
664
dc08267a 665out_suspend:
d38ceaf9
AD		 666 pm_runtime_mark_last_busy(dev->dev);
667 pm_runtime_put_autosuspend(dev->dev);
d38ceaf9
AD		 668
669 return r;
670}
671
672/**
673 * amdgpu_driver_postclose_kms - drm callback for post close
674 *
675 * @dev: drm dev pointer
676 * @file_priv: drm file
677 *
678 * On device post close, tear down vm on cayman+ (all asics).
679 */
680void amdgpu_driver_postclose_kms(struct drm_device *dev,
681 struct drm_file *file_priv)
682{
683 struct amdgpu_device *adev = dev->dev_private;
684 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
685 struct amdgpu_bo_list *list;
686 int handle;
687
688 if (!fpriv)
689 return;
690
02537d63
CK		 691 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
692
cd437e37
LL		 693 amdgpu_uvd_free_handles(adev, file_priv);
694 amdgpu_vce_free_handles(adev, file_priv);
695
2493664f
ML		 696 if (amdgpu_sriov_vf(adev)) {
697 /* TODO: how to handle reserve failure */
698 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
699 amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
700 fpriv->vm.csa_bo_va = NULL;
701 amdgpu_bo_unreserve(adev->virt.csa_obj);
702 }
703
d38ceaf9
AD		 704 amdgpu_vm_fini(adev, &fpriv->vm);
705
706 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
707 amdgpu_bo_list_free(list);
708
709 idr_destroy(&fpriv->bo_list_handles);
710 mutex_destroy(&fpriv->bo_list_lock);
711
d38ceaf9
AD		 712 kfree(fpriv);
713 file_priv->driver_priv = NULL;
d6bda7b4
AD		 714
715 pm_runtime_mark_last_busy(dev->dev);
716 pm_runtime_put_autosuspend(dev->dev);
d38ceaf9
AD		 717}
718
719/**
720 * amdgpu_driver_preclose_kms - drm callback for pre close
721 *
722 * @dev: drm dev pointer
723 * @file_priv: drm file
724 *
725 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
726 * (all asics).
727 */
728void amdgpu_driver_preclose_kms(struct drm_device *dev,
729 struct drm_file *file_priv)
730{
d6bda7b4 731 pm_runtime_get_sync(dev->dev);
d38ceaf9
AD		 732}
733
734/*
735 * VBlank related functions.
736 */
737/**
738 * amdgpu_get_vblank_counter_kms - get frame count
739 *
740 * @dev: drm dev pointer
88e72717 741 * @pipe: crtc to get the frame count from
d38ceaf9
AD		 742 *
743 * Gets the frame count on the requested crtc (all asics).
744 * Returns frame count on success, -EINVAL on failure.
745 */
88e72717 746u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
d38ceaf9
AD		 747{
748 struct amdgpu_device *adev = dev->dev_private;
8e36f9d3
AD		 749 int vpos, hpos, stat;
750 u32 count;
d38ceaf9 751
88e72717
TR		 752 if (pipe >= adev->mode_info.num_crtc) {
753 DRM_ERROR("Invalid crtc %u\n", pipe);
d38ceaf9
AD		 754 return -EINVAL;
755 }
756
8e36f9d3
AD		 757 /* The hw increments its frame counter at start of vsync, not at start
758 * of vblank, as is required by DRM core vblank counter handling.
759 * Cook the hw count here to make it appear to the caller as if it
760 * incremented at start of vblank. We measure distance to start of
761 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
762 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
763 * result by 1 to give the proper appearance to caller.
764 */
765 if (adev->mode_info.crtcs[pipe]) {
766 /* Repeat readout if needed to provide stable result if
767 * we cross start of vsync during the queries.
768 */
769 do {
770 count = amdgpu_display_vblank_get_counter(adev, pipe);
771 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
772 * distance to start of vblank, instead of regular
773 * vertical scanout pos.
774 */
775 stat = amdgpu_get_crtc_scanoutpos(
776 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
777 &vpos, &hpos, NULL, NULL,
778 &adev->mode_info.crtcs[pipe]->base.hwmode);
779 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
780
781 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
782 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
783 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
784 } else {
785 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
786 pipe, vpos);
787
788 /* Bump counter if we are at >= leading edge of vblank,
789 * but before vsync where vpos would turn negative and
790 * the hw counter really increments.
791 */
792 if (vpos >= 0)
793 count++;
794 }
795 } else {
796 /* Fallback to use value as is. */
797 count = amdgpu_display_vblank_get_counter(adev, pipe);
798 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
799 }
800
801 return count;
d38ceaf9
AD		 802}
803
804/**
805 * amdgpu_enable_vblank_kms - enable vblank interrupt
806 *
807 * @dev: drm dev pointer
88e72717 808 * @pipe: crtc to enable vblank interrupt for
d38ceaf9
AD		 809 *
810 * Enable the interrupt on the requested crtc (all asics).
811 * Returns 0 on success, -EINVAL on failure.
812 */
88e72717 813int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
d38ceaf9
AD		 814{
815 struct amdgpu_device *adev = dev->dev_private;
88e72717 816 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
d38ceaf9
AD		 817
818 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
819}
820
821/**
822 * amdgpu_disable_vblank_kms - disable vblank interrupt
823 *
824 * @dev: drm dev pointer
88e72717 825 * @pipe: crtc to disable vblank interrupt for
d38ceaf9
AD		 826 *
827 * Disable the interrupt on the requested crtc (all asics).
828 */
88e72717 829void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
d38ceaf9
AD		 830{
831 struct amdgpu_device *adev = dev->dev_private;
88e72717 832 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
d38ceaf9
AD		 833
834 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
835}
836
837/**
838 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
839 *
840 * @dev: drm dev pointer
841 * @crtc: crtc to get the timestamp for
842 * @max_error: max error
843 * @vblank_time: time value
844 * @flags: flags passed to the driver
845 *
846 * Gets the timestamp on the requested crtc based on the
847 * scanout position. (all asics).
848 * Returns postive status flags on success, negative error on failure.
849 */
88e72717 850int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
d38ceaf9
AD		 851 int *max_error,
852 struct timeval *vblank_time,
853 unsigned flags)
854{
88e72717 855 struct drm_crtc *crtc;
d38ceaf9
AD		 856 struct amdgpu_device *adev = dev->dev_private;
857
88e72717
TR		 858 if (pipe >= dev->num_crtcs) {
859 DRM_ERROR("Invalid crtc %u\n", pipe);
d38ceaf9
AD		 860 return -EINVAL;
861 }
862
863 /* Get associated drm_crtc: */
88e72717 864 crtc = &adev->mode_info.crtcs[pipe]->base;
9ddf940f
HW		 865 if (!crtc) {
866 /* This can occur on driver load if some component fails to
867 * initialize completely and driver is unloaded */
868 DRM_ERROR("Uninitialized crtc %d\n", pipe);
869 return -EINVAL;
870 }
d38ceaf9
AD		 871
872 /* Helper routine in DRM core does all the work: */
88e72717 873 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
d38ceaf9 874 vblank_time, flags,
88e72717 875 &crtc->hwmode);
d38ceaf9
AD		 876}
877
878const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
f8c47144
DV		 879 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
880 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
881 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
d38ceaf9 882 /* KMS */
f8c47144
DV		 883 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
884 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
885 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
886 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
887 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
eef18a82 888 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
f8c47144
DV		 889 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
890 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
891 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
892 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
d38ceaf9 893};
f498d9ed 894const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
50ab2533
HR		 895
896/*
897 * Debugfs info
898 */
899#if defined(CONFIG_DEBUG_FS)
900
901static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
902{
903 struct drm_info_node *node = (struct drm_info_node *) m->private;
904 struct drm_device *dev = node->minor->dev;
905 struct amdgpu_device *adev = dev->dev_private;
906 struct drm_amdgpu_info_firmware fw_info;
907 struct drm_amdgpu_query_fw query_fw;
908 int ret, i;
909
910 /* VCE */
911 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
912 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
913 if (ret)
914 return ret;
915 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
916 fw_info.feature, fw_info.ver);
917
918 /* UVD */
919 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
920 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
921 if (ret)
922 return ret;
923 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
924 fw_info.feature, fw_info.ver);
925
926 /* GMC */
927 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
928 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
929 if (ret)
930 return ret;
931 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
932 fw_info.feature, fw_info.ver);
933
934 /* ME */
935 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
936 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
937 if (ret)
938 return ret;
939 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
940 fw_info.feature, fw_info.ver);
941
942 /* PFP */
943 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
944 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
945 if (ret)
946 return ret;
947 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
948 fw_info.feature, fw_info.ver);
949
950 /* CE */
951 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
952 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
953 if (ret)
954 return ret;
955 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
956 fw_info.feature, fw_info.ver);
957
958 /* RLC */
959 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
960 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
961 if (ret)
962 return ret;
963 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
964 fw_info.feature, fw_info.ver);
965
966 /* MEC */
967 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
968 query_fw.index = 0;
969 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
970 if (ret)
971 return ret;
972 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
973 fw_info.feature, fw_info.ver);
974
975 /* MEC2 */
976 if (adev->asic_type == CHIP_KAVERI ||
977 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
978 query_fw.index = 1;
979 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
980 if (ret)
981 return ret;
982 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
983 fw_info.feature, fw_info.ver);
984 }
985
986 /* SMC */
987 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
988 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
989 if (ret)
990 return ret;
991 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
992 fw_info.feature, fw_info.ver);
993
994 /* SDMA */
995 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
996 for (i = 0; i < adev->sdma.num_instances; i++) {
997 query_fw.index = i;
998 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
999 if (ret)
1000 return ret;
1001 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1002 i, fw_info.feature, fw_info.ver);
1003 }
1004
1005 return 0;
1006}
1007
1008static const struct drm_info_list amdgpu_firmware_info_list[] = {
1009 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1010};
1011#endif
1012
1013int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1014{
1015#if defined(CONFIG_DEBUG_FS)
1016 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1017 ARRAY_SIZE(amdgpu_firmware_info_list));
1018#else
1019 return 0;
1020#endif
1021}
Linux 6.x block layer and io_uring tree(s)