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uapi/drm: add AMDGPU_HW_IP_UVD_ENC
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_kms.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33
34#include <linux/vga_switcheroo.h>
35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
130e0371 37#include "amdgpu_amdkfd.h"
d38ceaf9
AD		 38
39#if defined(CONFIG_VGA_SWITCHEROO)
40bool amdgpu_has_atpx(void);
41#else
42static inline bool amdgpu_has_atpx(void) { return false; }
43#endif
44
45/**
46 * amdgpu_driver_unload_kms - Main unload function for KMS.
47 *
48 * @dev: drm dev pointer
49 *
50 * This is the main unload function for KMS (all asics).
51 * Returns 0 on success.
52 */
11b3c20b 53void amdgpu_driver_unload_kms(struct drm_device *dev)
d38ceaf9
AD		 54{
55 struct amdgpu_device *adev = dev->dev_private;
56
57 if (adev == NULL)
11b3c20b 58 return;
d38ceaf9
AD		 59
60 if (adev->rmmio == NULL)
61 goto done_free;
62
3149d9da
XY		 63 if (amdgpu_sriov_vf(adev))
64 amdgpu_virt_request_full_gpu(adev, false);
65
4a788547
LW		 66 if (amdgpu_device_is_px(dev)) {
67 pm_runtime_get_sync(dev->dev);
6ce62d8b 68 pm_runtime_forbid(dev->dev);
4a788547 69 }
d38ceaf9 70
130e0371
OG		 71 amdgpu_amdkfd_device_fini(adev);
72
d38ceaf9
AD		 73 amdgpu_acpi_fini(adev);
74
75 amdgpu_device_fini(adev);
76
77done_free:
78 kfree(adev);
79 dev->dev_private = NULL;
d38ceaf9
AD		 80}
81
82/**
83 * amdgpu_driver_load_kms - Main load function for KMS.
84 *
85 * @dev: drm dev pointer
86 * @flags: device flags
87 *
88 * This is the main load function for KMS (all asics).
89 * Returns 0 on success, error on failure.
90 */
91int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
92{
93 struct amdgpu_device *adev;
94 int r, acpi_status;
95
96 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
97 if (adev == NULL) {
98 return -ENOMEM;
99 }
100 dev->dev_private = (void *)adev;
101
102 if ((amdgpu_runtime_pm != 0) &&
103 amdgpu_has_atpx() &&
84b1528e
AD		 104 (amdgpu_is_atpx_hybrid() ||
105 amdgpu_has_atpx_dgpu_power_cntl()) &&
2f7d10b3
JZ		 106 ((flags & AMD_IS_APU) == 0))
107 flags |= AMD_IS_PX;
d38ceaf9
AD		 108
109 /* amdgpu_device_init should report only fatal error
110 * like memory allocation failure or iomapping failure,
111 * or memory manager initialization failure, it must
112 * properly initialize the GPU MC controller and permit
113 * VRAM allocation
114 */
115 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
116 if (r) {
117 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
118 goto out;
119 }
120
121 /* Call ACPI methods: require modeset init
122 * but failure is not fatal
123 */
124 if (!r) {
125 acpi_status = amdgpu_acpi_init(adev);
126 if (acpi_status)
127 dev_dbg(&dev->pdev->dev,
128 "Error during ACPI methods call\n");
129 }
130
130e0371
OG		 131 amdgpu_amdkfd_load_interface(adev);
132 amdgpu_amdkfd_device_probe(adev);
133 amdgpu_amdkfd_device_init(adev);
134
d38ceaf9
AD		 135 if (amdgpu_device_is_px(dev)) {
136 pm_runtime_use_autosuspend(dev->dev);
137 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
138 pm_runtime_set_active(dev->dev);
139 pm_runtime_allow(dev->dev);
140 pm_runtime_mark_last_busy(dev->dev);
141 pm_runtime_put_autosuspend(dev->dev);
142 }
143
3149d9da
XY		 144 if (amdgpu_sriov_vf(adev))
145 amdgpu_virt_release_full_gpu(adev, true);
146
d38ceaf9 147out:
c9c9bbd7
LW		 148 if (r) {
149 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
150 if (adev->rmmio && amdgpu_device_is_px(dev))
151 pm_runtime_put_noidle(dev->dev);
d38ceaf9 152 amdgpu_driver_unload_kms(dev);
c9c9bbd7 153 }
d38ceaf9
AD		 154
155 return r;
156}
157
000cab9a
HR		 158static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
159 struct drm_amdgpu_query_fw *query_fw,
160 struct amdgpu_device *adev)
161{
162 switch (query_fw->fw_type) {
163 case AMDGPU_INFO_FW_VCE:
164 fw_info->ver = adev->vce.fw_version;
165 fw_info->feature = adev->vce.fb_version;
166 break;
167 case AMDGPU_INFO_FW_UVD:
168 fw_info->ver = adev->uvd.fw_version;
169 fw_info->feature = 0;
170 break;
171 case AMDGPU_INFO_FW_GMC:
172 fw_info->ver = adev->mc.fw_version;
173 fw_info->feature = 0;
174 break;
175 case AMDGPU_INFO_FW_GFX_ME:
176 fw_info->ver = adev->gfx.me_fw_version;
177 fw_info->feature = adev->gfx.me_feature_version;
178 break;
179 case AMDGPU_INFO_FW_GFX_PFP:
180 fw_info->ver = adev->gfx.pfp_fw_version;
181 fw_info->feature = adev->gfx.pfp_feature_version;
182 break;
183 case AMDGPU_INFO_FW_GFX_CE:
184 fw_info->ver = adev->gfx.ce_fw_version;
185 fw_info->feature = adev->gfx.ce_feature_version;
186 break;
187 case AMDGPU_INFO_FW_GFX_RLC:
188 fw_info->ver = adev->gfx.rlc_fw_version;
189 fw_info->feature = adev->gfx.rlc_feature_version;
190 break;
191 case AMDGPU_INFO_FW_GFX_MEC:
192 if (query_fw->index == 0) {
193 fw_info->ver = adev->gfx.mec_fw_version;
194 fw_info->feature = adev->gfx.mec_feature_version;
195 } else if (query_fw->index == 1) {
196 fw_info->ver = adev->gfx.mec2_fw_version;
197 fw_info->feature = adev->gfx.mec2_feature_version;
198 } else
199 return -EINVAL;
200 break;
201 case AMDGPU_INFO_FW_SMC:
202 fw_info->ver = adev->pm.fw_version;
203 fw_info->feature = 0;
204 break;
205 case AMDGPU_INFO_FW_SDMA:
206 if (query_fw->index >= adev->sdma.num_instances)
207 return -EINVAL;
208 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
209 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
210 break;
211 default:
212 return -EINVAL;
213 }
214 return 0;
215}
216
d38ceaf9
AD		 217/*
218 * Userspace get information ioctl
219 */
220/**
221 * amdgpu_info_ioctl - answer a device specific request.
222 *
223 * @adev: amdgpu device pointer
224 * @data: request object
225 * @filp: drm filp
226 *
227 * This function is used to pass device specific parameters to the userspace
228 * drivers. Examples include: pci device id, pipeline parms, tiling params,
229 * etc. (all asics).
230 * Returns 0 on success, -EINVAL on failure.
231 */
232static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
233{
234 struct amdgpu_device *adev = dev->dev_private;
235 struct drm_amdgpu_info *info = data;
236 struct amdgpu_mode_info *minfo = &adev->mode_info;
237 void __user *out = (void __user *)(long)info->return_pointer;
238 uint32_t size = info->return_size;
239 struct drm_crtc *crtc;
240 uint32_t ui32 = 0;
241 uint64_t ui64 = 0;
242 int i, found;
5ebbac4b 243 int ui32_size = sizeof(ui32);
d38ceaf9
AD		 244
245 if (!info->return_size || !info->return_pointer)
246 return -EINVAL;
247
248 switch (info->query) {
249 case AMDGPU_INFO_ACCEL_WORKING:
250 ui32 = adev->accel_working;
251 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
252 case AMDGPU_INFO_CRTC_FROM_ID:
253 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
254 crtc = (struct drm_crtc *)minfo->crtcs[i];
255 if (crtc && crtc->base.id == info->mode_crtc.id) {
256 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
257 ui32 = amdgpu_crtc->crtc_id;
258 found = 1;
259 break;
260 }
261 }
262 if (!found) {
263 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
264 return -EINVAL;
265 }
266 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
267 case AMDGPU_INFO_HW_IP_INFO: {
268 struct drm_amdgpu_info_hw_ip ip = {};
5fc3aeeb 269 enum amd_ip_block_type type;
d38ceaf9 270 uint32_t ring_mask = 0;
71062f43
KW		 271 uint32_t ib_start_alignment = 0;
272 uint32_t ib_size_alignment = 0;
d38ceaf9
AD		 273
274 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
275 return -EINVAL;
276
277 switch (info->query_hw_ip.type) {
278 case AMDGPU_HW_IP_GFX:
5fc3aeeb 279 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 280 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
281 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
71062f43
KW		 282 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
283 ib_size_alignment = 8;
d38ceaf9
AD		 284 break;
285 case AMDGPU_HW_IP_COMPUTE:
5fc3aeeb 286 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 287 for (i = 0; i < adev->gfx.num_compute_rings; i++)
288 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
71062f43
KW		 289 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
290 ib_size_alignment = 8;
d38ceaf9
AD		 291 break;
292 case AMDGPU_HW_IP_DMA:
5fc3aeeb 293 type = AMD_IP_BLOCK_TYPE_SDMA;
c113ea1c
AD		 294 for (i = 0; i < adev->sdma.num_instances; i++)
295 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
71062f43
KW		 296 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
297 ib_size_alignment = 1;
d38ceaf9
AD		 298 break;
299 case AMDGPU_HW_IP_UVD:
5fc3aeeb 300 type = AMD_IP_BLOCK_TYPE_UVD;
d38ceaf9 301 ring_mask = adev->uvd.ring.ready ? 1 : 0;
71062f43 302 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
c4795ca6 303 ib_size_alignment = 16;
d38ceaf9
AD		 304 break;
305 case AMDGPU_HW_IP_VCE:
5fc3aeeb 306 type = AMD_IP_BLOCK_TYPE_VCE;
75c65480 307 for (i = 0; i < adev->vce.num_rings; i++)
d38ceaf9 308 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
71062f43 309 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
a22f803c 310 ib_size_alignment = 1;
d38ceaf9
AD		 311 break;
312 default:
313 return -EINVAL;
314 }
315
316 for (i = 0; i < adev->num_ip_blocks; i++) {
a1255107
AD		 317 if (adev->ip_blocks[i].version->type == type &&
318 adev->ip_blocks[i].status.valid) {
319 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
320 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
d38ceaf9
AD		 321 ip.capabilities_flags = 0;
322 ip.available_rings = ring_mask;
71062f43
KW		 323 ip.ib_start_alignment = ib_start_alignment;
324 ip.ib_size_alignment = ib_size_alignment;
d38ceaf9
AD		 325 break;
326 }
327 }
328 return copy_to_user(out, &ip,
329 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
330 }
331 case AMDGPU_INFO_HW_IP_COUNT: {
5fc3aeeb 332 enum amd_ip_block_type type;
d38ceaf9
AD		 333 uint32_t count = 0;
334
335 switch (info->query_hw_ip.type) {
336 case AMDGPU_HW_IP_GFX:
5fc3aeeb 337 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 338 break;
339 case AMDGPU_HW_IP_COMPUTE:
5fc3aeeb 340 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 341 break;
342 case AMDGPU_HW_IP_DMA:
5fc3aeeb 343 type = AMD_IP_BLOCK_TYPE_SDMA;
d38ceaf9
AD		 344 break;
345 case AMDGPU_HW_IP_UVD:
5fc3aeeb 346 type = AMD_IP_BLOCK_TYPE_UVD;
d38ceaf9
AD		 347 break;
348 case AMDGPU_HW_IP_VCE:
5fc3aeeb 349 type = AMD_IP_BLOCK_TYPE_VCE;
d38ceaf9
AD		 350 break;
351 default:
352 return -EINVAL;
353 }
354
355 for (i = 0; i < adev->num_ip_blocks; i++)
a1255107
AD		 356 if (adev->ip_blocks[i].version->type == type &&
357 adev->ip_blocks[i].status.valid &&
d38ceaf9
AD		 358 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
359 count++;
360
361 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
362 }
363 case AMDGPU_INFO_TIMESTAMP:
b95e31fd 364 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
d38ceaf9
AD		 365 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
366 case AMDGPU_INFO_FW_VERSION: {
367 struct drm_amdgpu_info_firmware fw_info;
000cab9a 368 int ret;
d38ceaf9
AD		 369
370 /* We only support one instance of each IP block right now. */
371 if (info->query_fw.ip_instance != 0)
372 return -EINVAL;
373
000cab9a
HR		 374 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
375 if (ret)
376 return ret;
377
d38ceaf9
AD		 378 return copy_to_user(out, &fw_info,
379 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
380 }
381 case AMDGPU_INFO_NUM_BYTES_MOVED:
382 ui64 = atomic64_read(&adev->num_bytes_moved);
383 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
83a59b63
MO		 384 case AMDGPU_INFO_NUM_EVICTIONS:
385 ui64 = atomic64_read(&adev->num_evictions);
386 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
d38ceaf9
AD		 387 case AMDGPU_INFO_VRAM_USAGE:
388 ui64 = atomic64_read(&adev->vram_usage);
389 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
390 case AMDGPU_INFO_VIS_VRAM_USAGE:
391 ui64 = atomic64_read(&adev->vram_vis_usage);
392 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
393 case AMDGPU_INFO_GTT_USAGE:
394 ui64 = atomic64_read(&adev->gtt_usage);
395 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
396 case AMDGPU_INFO_GDS_CONFIG: {
397 struct drm_amdgpu_info_gds gds_info;
398
c92b90cc 399 memset(&gds_info, 0, sizeof(gds_info));
d38ceaf9
AD		 400 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
401 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
402 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
403 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
404 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
405 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
406 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
407 return copy_to_user(out, &gds_info,
408 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
409 }
410 case AMDGPU_INFO_VRAM_GTT: {
411 struct drm_amdgpu_info_vram_gtt vram_gtt;
412
413 vram_gtt.vram_size = adev->mc.real_vram_size;
7c0ecda1 414 vram_gtt.vram_size -= adev->vram_pin_size;
d38ceaf9 415 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
e131b914 416 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
d38ceaf9
AD		 417 vram_gtt.gtt_size = adev->mc.gtt_size;
418 vram_gtt.gtt_size -= adev->gart_pin_size;
419 return copy_to_user(out, &vram_gtt,
420 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
421 }
e0adf6c8
JZ		 422 case AMDGPU_INFO_MEMORY: {
423 struct drm_amdgpu_memory_info mem;
424
425 memset(&mem, 0, sizeof(mem));
426 mem.vram.total_heap_size = adev->mc.real_vram_size;
427 mem.vram.usable_heap_size =
428 adev->mc.real_vram_size - adev->vram_pin_size;
429 mem.vram.heap_usage = atomic64_read(&adev->vram_usage);
430 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
431
432 mem.cpu_accessible_vram.total_heap_size =
433 adev->mc.visible_vram_size;
434 mem.cpu_accessible_vram.usable_heap_size =
435 adev->mc.visible_vram_size -
436 (adev->vram_pin_size - adev->invisible_pin_size);
437 mem.cpu_accessible_vram.heap_usage =
438 atomic64_read(&adev->vram_vis_usage);
439 mem.cpu_accessible_vram.max_allocation =
440 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
441
442 mem.gtt.total_heap_size = adev->mc.gtt_size;
443 mem.gtt.usable_heap_size =
444 adev->mc.gtt_size - adev->gart_pin_size;
445 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage);
446 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
447
448 return copy_to_user(out, &mem,
449 min((size_t)size, sizeof(mem)))
cfa32556
JZ		 450 ? -EFAULT : 0;
451 }
d38ceaf9 452 case AMDGPU_INFO_READ_MMR_REG: {
0d2edd37 453 unsigned n, alloc_size;
d38ceaf9
AD		 454 uint32_t *regs;
455 unsigned se_num = (info->read_mmr_reg.instance >>
456 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
457 AMDGPU_INFO_MMR_SE_INDEX_MASK;
458 unsigned sh_num = (info->read_mmr_reg.instance >>
459 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
460 AMDGPU_INFO_MMR_SH_INDEX_MASK;
461
462 /* set full masks if the userspace set all bits
463 * in the bitfields */
464 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
465 se_num = 0xffffffff;
466 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
467 sh_num = 0xffffffff;
468
0d2edd37 469 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
d38ceaf9
AD		 470 if (!regs)
471 return -ENOMEM;
0d2edd37 472 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
d38ceaf9
AD		 473
474 for (i = 0; i < info->read_mmr_reg.count; i++)
475 if (amdgpu_asic_read_register(adev, se_num, sh_num,
476 info->read_mmr_reg.dword_offset + i,
477 &regs[i])) {
478 DRM_DEBUG_KMS("unallowed offset %#x\n",
479 info->read_mmr_reg.dword_offset + i);
480 kfree(regs);
481 return -EFAULT;
482 }
483 n = copy_to_user(out, regs, min(size, alloc_size));
484 kfree(regs);
485 return n ? -EFAULT : 0;
486 }
487 case AMDGPU_INFO_DEV_INFO: {
c193fa91 488 struct drm_amdgpu_info_device dev_info = {};
d38ceaf9
AD		 489
490 dev_info.device_id = dev->pdev->device;
491 dev_info.chip_rev = adev->rev_id;
492 dev_info.external_rev = adev->external_rev_id;
493 dev_info.pci_rev = dev->pdev->revision;
494 dev_info.family = adev->family;
495 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
496 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
497 /* return all clocks in KHz */
498 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
32bf7106 499 if (adev->pm.dpm_enabled) {
1304f0c7
EQ		 500 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
501 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
32bf7106 502 } else {
d38ceaf9 503 dev_info.max_engine_clock = adev->pm.default_sclk * 10;
32bf7106
KW		 504 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
505 }
d38ceaf9 506 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
0b10029d
AD		 507 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
508 adev->gfx.config.max_shader_engines;
d38ceaf9
AD		 509 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
510 dev_info._pad = 0;
511 dev_info.ids_flags = 0;
2f7d10b3 512 if (adev->flags & AMD_IS_APU)
d38ceaf9 513 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
aafcafa0
ML		 514 if (amdgpu_sriov_vf(adev))
515 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
d38ceaf9 516 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
02b70c8c 517 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
c548b345 518 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
d38ceaf9
AD		 519 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
520 AMDGPU_GPU_PAGE_SIZE;
521 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
522
7dae69a2
AD		 523 dev_info.cu_active_number = adev->gfx.cu_info.number;
524 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
a101a899 525 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
7dae69a2
AD		 526 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
527 sizeof(adev->gfx.cu_info.bitmap));
81c59f54
KW		 528 dev_info.vram_type = adev->mc.vram_type;
529 dev_info.vram_bit_width = adev->mc.vram_width;
fa92754e 530 dev_info.vce_harvest_config = adev->vce.harvest_config;
df6e2c4a
JZ		 531 dev_info.gc_double_offchip_lds_buf =
532 adev->gfx.config.double_offchip_lds_buf;
d38ceaf9
AD		 533
534 return copy_to_user(out, &dev_info,
535 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
536 }
07fecde5
AD		 537 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
538 unsigned i;
539 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
540 struct amd_vce_state *vce_state;
541
542 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
543 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
544 if (vce_state) {
545 vce_clk_table.entries[i].sclk = vce_state->sclk;
546 vce_clk_table.entries[i].mclk = vce_state->mclk;
547 vce_clk_table.entries[i].eclk = vce_state->evclk;
548 vce_clk_table.num_valid_entries++;
549 }
550 }
551
552 return copy_to_user(out, &vce_clk_table,
553 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
554 }
40ee5888
EQ		 555 case AMDGPU_INFO_VBIOS: {
556 uint32_t bios_size = adev->bios_size;
557
558 switch (info->vbios_info.type) {
559 case AMDGPU_INFO_VBIOS_SIZE:
560 return copy_to_user(out, &bios_size,
561 min((size_t)size, sizeof(bios_size)))
562 ? -EFAULT : 0;
563 case AMDGPU_INFO_VBIOS_IMAGE: {
564 uint8_t *bios;
565 uint32_t bios_offset = info->vbios_info.offset;
566
567 if (bios_offset >= bios_size)
568 return -EINVAL;
569
570 bios = adev->bios + bios_offset;
571 return copy_to_user(out, bios,
572 min((size_t)size, (size_t)(bios_size - bios_offset)))
573 ? -EFAULT : 0;
574 }
575 default:
576 DRM_DEBUG_KMS("Invalid request %d\n",
577 info->vbios_info.type);
578 return -EINVAL;
579 }
580 }
44879b62
AN		 581 case AMDGPU_INFO_NUM_HANDLES: {
582 struct drm_amdgpu_info_num_handles handle;
583
584 switch (info->query_hw_ip.type) {
585 case AMDGPU_HW_IP_UVD:
586 /* Starting Polaris, we support unlimited UVD handles */
587 if (adev->asic_type < CHIP_POLARIS10) {
588 handle.uvd_max_handles = adev->uvd.max_handles;
589 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
590
591 return copy_to_user(out, &handle,
592 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
593 } else {
594 return -ENODATA;
595 }
596
597 break;
598 default:
599 return -EINVAL;
600 }
601 }
5ebbac4b
AD		 602 case AMDGPU_INFO_SENSOR: {
603 struct pp_gpu_power query = {0};
604 int query_size = sizeof(query);
605
606 if (amdgpu_dpm == 0)
607 return -ENOENT;
608
609 switch (info->sensor_info.type) {
610 case AMDGPU_INFO_SENSOR_GFX_SCLK:
611 /* get sclk in Mhz */
612 if (amdgpu_dpm_read_sensor(adev,
613 AMDGPU_PP_SENSOR_GFX_SCLK,
614 (void *)&ui32, &ui32_size)) {
615 return -EINVAL;
616 }
617 ui32 /= 100;
618 break;
619 case AMDGPU_INFO_SENSOR_GFX_MCLK:
620 /* get mclk in Mhz */
621 if (amdgpu_dpm_read_sensor(adev,
622 AMDGPU_PP_SENSOR_GFX_MCLK,
623 (void *)&ui32, &ui32_size)) {
624 return -EINVAL;
625 }
626 ui32 /= 100;
627 break;
628 case AMDGPU_INFO_SENSOR_GPU_TEMP:
629 /* get temperature in millidegrees C */
630 if (amdgpu_dpm_read_sensor(adev,
631 AMDGPU_PP_SENSOR_GPU_TEMP,
632 (void *)&ui32, &ui32_size)) {
633 return -EINVAL;
634 }
635 break;
636 case AMDGPU_INFO_SENSOR_GPU_LOAD:
637 /* get GPU load */
638 if (amdgpu_dpm_read_sensor(adev,
639 AMDGPU_PP_SENSOR_GPU_LOAD,
640 (void *)&ui32, &ui32_size)) {
641 return -EINVAL;
642 }
643 break;
644 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
645 /* get average GPU power */
646 if (amdgpu_dpm_read_sensor(adev,
647 AMDGPU_PP_SENSOR_GPU_POWER,
648 (void *)&query, &query_size)) {
649 return -EINVAL;
650 }
651 ui32 = query.average_gpu_power >> 8;
652 break;
653 case AMDGPU_INFO_SENSOR_VDDNB:
654 /* get VDDNB in millivolts */
655 if (amdgpu_dpm_read_sensor(adev,
656 AMDGPU_PP_SENSOR_VDDNB,
657 (void *)&ui32, &ui32_size)) {
658 return -EINVAL;
659 }
660 break;
661 case AMDGPU_INFO_SENSOR_VDDGFX:
662 /* get VDDGFX in millivolts */
663 if (amdgpu_dpm_read_sensor(adev,
664 AMDGPU_PP_SENSOR_VDDGFX,
665 (void *)&ui32, &ui32_size)) {
666 return -EINVAL;
667 }
668 break;
669 default:
670 DRM_DEBUG_KMS("Invalid request %d\n",
671 info->sensor_info.type);
672 return -EINVAL;
673 }
674 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
675 }
d38ceaf9
AD		 676 default:
677 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
678 return -EINVAL;
679 }
680 return 0;
681}
682
683
684/*
685 * Outdated mess for old drm with Xorg being in charge (void function now).
686 */
687/**
8b7530b1 688 * amdgpu_driver_lastclose_kms - drm callback for last close
d38ceaf9
AD		 689 *
690 * @dev: drm dev pointer
691 *
1694467b 692 * Switch vga_switcheroo state after last close (all asics).
d38ceaf9
AD		 693 */
694void amdgpu_driver_lastclose_kms(struct drm_device *dev)
695{
8b7530b1
AD		 696 struct amdgpu_device *adev = dev->dev_private;
697
698 amdgpu_fbdev_restore_mode(adev);
d38ceaf9
AD		 699 vga_switcheroo_process_delayed_switch();
700}
701
702/**
703 * amdgpu_driver_open_kms - drm callback for open
704 *
705 * @dev: drm dev pointer
706 * @file_priv: drm file
707 *
708 * On device open, init vm on cayman+ (all asics).
709 * Returns 0 on success, error on failure.
710 */
711int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
712{
713 struct amdgpu_device *adev = dev->dev_private;
714 struct amdgpu_fpriv *fpriv;
715 int r;
716
717 file_priv->driver_priv = NULL;
718
719 r = pm_runtime_get_sync(dev->dev);
720 if (r < 0)
721 return r;
722
723 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
dc08267a
AD		 724 if (unlikely(!fpriv)) {
725 r = -ENOMEM;
726 goto out_suspend;
727 }
d38ceaf9
AD		 728
729 r = amdgpu_vm_init(adev, &fpriv->vm);
dc08267a
AD		 730 if (r) {
731 kfree(fpriv);
732 goto out_suspend;
733 }
d38ceaf9 734
b85891bd
JZ		 735 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
736 if (!fpriv->prt_va) {
737 r = -ENOMEM;
738 amdgpu_vm_fini(adev, &fpriv->vm);
739 kfree(fpriv);
740 goto out_suspend;
741 }
742
2493664f
ML		 743 if (amdgpu_sriov_vf(adev)) {
744 r = amdgpu_map_static_csa(adev, &fpriv->vm);
745 if (r)
746 goto out_suspend;
747 }
748
d38ceaf9
AD		 749 mutex_init(&fpriv->bo_list_lock);
750 idr_init(&fpriv->bo_list_handles);
751
efd4ccb5 752 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
d38ceaf9
AD		 753
754 file_priv->driver_priv = fpriv;
755
dc08267a 756out_suspend:
d38ceaf9
AD		 757 pm_runtime_mark_last_busy(dev->dev);
758 pm_runtime_put_autosuspend(dev->dev);
d38ceaf9
AD		 759
760 return r;
761}
762
763/**
764 * amdgpu_driver_postclose_kms - drm callback for post close
765 *
766 * @dev: drm dev pointer
767 * @file_priv: drm file
768 *
769 * On device post close, tear down vm on cayman+ (all asics).
770 */
771void amdgpu_driver_postclose_kms(struct drm_device *dev,
772 struct drm_file *file_priv)
773{
774 struct amdgpu_device *adev = dev->dev_private;
775 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
776 struct amdgpu_bo_list *list;
777 int handle;
778
779 if (!fpriv)
780 return;
781
04e30c9c
DV		 782 pm_runtime_get_sync(dev->dev);
783
02537d63
CK		 784 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
785
cd437e37
LL		 786 amdgpu_uvd_free_handles(adev, file_priv);
787 amdgpu_vce_free_handles(adev, file_priv);
788
b85891bd
JZ		 789 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
790
2493664f
ML		 791 if (amdgpu_sriov_vf(adev)) {
792 /* TODO: how to handle reserve failure */
793 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
794 amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
795 fpriv->vm.csa_bo_va = NULL;
796 amdgpu_bo_unreserve(adev->virt.csa_obj);
797 }
798
d38ceaf9
AD		 799 amdgpu_vm_fini(adev, &fpriv->vm);
800
801 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
802 amdgpu_bo_list_free(list);
803
804 idr_destroy(&fpriv->bo_list_handles);
805 mutex_destroy(&fpriv->bo_list_lock);
806
d38ceaf9
AD		 807 kfree(fpriv);
808 file_priv->driver_priv = NULL;
d6bda7b4
AD		 809
810 pm_runtime_mark_last_busy(dev->dev);
811 pm_runtime_put_autosuspend(dev->dev);
d38ceaf9
AD		 812}
813
d38ceaf9
AD		 814/*
815 * VBlank related functions.
816 */
817/**
818 * amdgpu_get_vblank_counter_kms - get frame count
819 *
820 * @dev: drm dev pointer
88e72717 821 * @pipe: crtc to get the frame count from
d38ceaf9
AD		 822 *
823 * Gets the frame count on the requested crtc (all asics).
824 * Returns frame count on success, -EINVAL on failure.
825 */
88e72717 826u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
d38ceaf9
AD		 827{
828 struct amdgpu_device *adev = dev->dev_private;
8e36f9d3
AD		 829 int vpos, hpos, stat;
830 u32 count;
d38ceaf9 831
88e72717
TR		 832 if (pipe >= adev->mode_info.num_crtc) {
833 DRM_ERROR("Invalid crtc %u\n", pipe);
d38ceaf9
AD		 834 return -EINVAL;
835 }
836
8e36f9d3
AD		 837 /* The hw increments its frame counter at start of vsync, not at start
838 * of vblank, as is required by DRM core vblank counter handling.
839 * Cook the hw count here to make it appear to the caller as if it
840 * incremented at start of vblank. We measure distance to start of
841 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
842 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
843 * result by 1 to give the proper appearance to caller.
844 */
845 if (adev->mode_info.crtcs[pipe]) {
846 /* Repeat readout if needed to provide stable result if
847 * we cross start of vsync during the queries.
848 */
849 do {
850 count = amdgpu_display_vblank_get_counter(adev, pipe);
851 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
852 * distance to start of vblank, instead of regular
853 * vertical scanout pos.
854 */
855 stat = amdgpu_get_crtc_scanoutpos(
856 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
857 &vpos, &hpos, NULL, NULL,
858 &adev->mode_info.crtcs[pipe]->base.hwmode);
859 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
860
861 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
862 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
863 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
864 } else {
865 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
866 pipe, vpos);
867
868 /* Bump counter if we are at >= leading edge of vblank,
869 * but before vsync where vpos would turn negative and
870 * the hw counter really increments.
871 */
872 if (vpos >= 0)
873 count++;
874 }
875 } else {
876 /* Fallback to use value as is. */
877 count = amdgpu_display_vblank_get_counter(adev, pipe);
878 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
879 }
880
881 return count;
d38ceaf9
AD		 882}
883
884/**
885 * amdgpu_enable_vblank_kms - enable vblank interrupt
886 *
887 * @dev: drm dev pointer
88e72717 888 * @pipe: crtc to enable vblank interrupt for
d38ceaf9
AD		 889 *
890 * Enable the interrupt on the requested crtc (all asics).
891 * Returns 0 on success, -EINVAL on failure.
892 */
88e72717 893int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
d38ceaf9
AD		 894{
895 struct amdgpu_device *adev = dev->dev_private;
88e72717 896 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
d38ceaf9
AD		 897
898 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
899}
900
901/**
902 * amdgpu_disable_vblank_kms - disable vblank interrupt
903 *
904 * @dev: drm dev pointer
88e72717 905 * @pipe: crtc to disable vblank interrupt for
d38ceaf9
AD		 906 *
907 * Disable the interrupt on the requested crtc (all asics).
908 */
88e72717 909void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
d38ceaf9
AD		 910{
911 struct amdgpu_device *adev = dev->dev_private;
88e72717 912 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
d38ceaf9
AD		 913
914 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
915}
916
917/**
918 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
919 *
920 * @dev: drm dev pointer
921 * @crtc: crtc to get the timestamp for
922 * @max_error: max error
923 * @vblank_time: time value
924 * @flags: flags passed to the driver
925 *
926 * Gets the timestamp on the requested crtc based on the
927 * scanout position. (all asics).
928 * Returns postive status flags on success, negative error on failure.
929 */
88e72717 930int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
d38ceaf9
AD		 931 int *max_error,
932 struct timeval *vblank_time,
933 unsigned flags)
934{
88e72717 935 struct drm_crtc *crtc;
d38ceaf9
AD		 936 struct amdgpu_device *adev = dev->dev_private;
937
88e72717
TR		 938 if (pipe >= dev->num_crtcs) {
939 DRM_ERROR("Invalid crtc %u\n", pipe);
d38ceaf9
AD		 940 return -EINVAL;
941 }
942
943 /* Get associated drm_crtc: */
88e72717 944 crtc = &adev->mode_info.crtcs[pipe]->base;
9ddf940f
HW		 945 if (!crtc) {
946 /* This can occur on driver load if some component fails to
947 * initialize completely and driver is unloaded */
948 DRM_ERROR("Uninitialized crtc %d\n", pipe);
949 return -EINVAL;
950 }
d38ceaf9
AD		 951
952 /* Helper routine in DRM core does all the work: */
88e72717 953 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
d38ceaf9 954 vblank_time, flags,
88e72717 955 &crtc->hwmode);
d38ceaf9
AD		 956}
957
958const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
f8c47144
DV		 959 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
961 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
d38ceaf9 962 /* KMS */
f8c47144
DV		 963 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
964 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
965 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
967 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
eef18a82 968 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
f8c47144
DV		 969 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
970 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
971 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
972 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
d38ceaf9 973};
f498d9ed 974const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
50ab2533
HR		 975
976/*
977 * Debugfs info
978 */
979#if defined(CONFIG_DEBUG_FS)
980
981static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
982{
983 struct drm_info_node *node = (struct drm_info_node *) m->private;
984 struct drm_device *dev = node->minor->dev;
985 struct amdgpu_device *adev = dev->dev_private;
986 struct drm_amdgpu_info_firmware fw_info;
987 struct drm_amdgpu_query_fw query_fw;
988 int ret, i;
989
990 /* VCE */
991 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
992 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
993 if (ret)
994 return ret;
995 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
996 fw_info.feature, fw_info.ver);
997
998 /* UVD */
999 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1000 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1001 if (ret)
1002 return ret;
1003 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1004 fw_info.feature, fw_info.ver);
1005
1006 /* GMC */
1007 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1008 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1009 if (ret)
1010 return ret;
1011 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1012 fw_info.feature, fw_info.ver);
1013
1014 /* ME */
1015 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1016 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1017 if (ret)
1018 return ret;
1019 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1020 fw_info.feature, fw_info.ver);
1021
1022 /* PFP */
1023 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1024 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1025 if (ret)
1026 return ret;
1027 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1028 fw_info.feature, fw_info.ver);
1029
1030 /* CE */
1031 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1032 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1033 if (ret)
1034 return ret;
1035 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1036 fw_info.feature, fw_info.ver);
1037
1038 /* RLC */
1039 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1040 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1041 if (ret)
1042 return ret;
1043 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1044 fw_info.feature, fw_info.ver);
1045
1046 /* MEC */
1047 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1048 query_fw.index = 0;
1049 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1050 if (ret)
1051 return ret;
1052 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1053 fw_info.feature, fw_info.ver);
1054
1055 /* MEC2 */
1056 if (adev->asic_type == CHIP_KAVERI ||
1057 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1058 query_fw.index = 1;
1059 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1060 if (ret)
1061 return ret;
1062 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1063 fw_info.feature, fw_info.ver);
1064 }
1065
1066 /* SMC */
1067 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1068 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1069 if (ret)
1070 return ret;
1071 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1072 fw_info.feature, fw_info.ver);
1073
1074 /* SDMA */
1075 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1076 for (i = 0; i < adev->sdma.num_instances; i++) {
1077 query_fw.index = i;
1078 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1079 if (ret)
1080 return ret;
1081 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1082 i, fw_info.feature, fw_info.ver);
1083 }
1084
1085 return 0;
1086}
1087
1088static const struct drm_info_list amdgpu_firmware_info_list[] = {
1089 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1090};
1091#endif
1092
1093int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1094{
1095#if defined(CONFIG_DEBUG_FS)
1096 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1097 ARRAY_SIZE(amdgpu_firmware_info_list));
1098#else
1099 return 0;
1100#endif
1101}
Linux 6.x block layer and io_uring tree(s)