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drm/amdgpu: add VRAM manager v2
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_kms.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33
34#include <linux/vga_switcheroo.h>
35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
130e0371 37#include "amdgpu_amdkfd.h"
d38ceaf9
AD		 38
39#if defined(CONFIG_VGA_SWITCHEROO)
40bool amdgpu_has_atpx(void);
41#else
42static inline bool amdgpu_has_atpx(void) { return false; }
43#endif
44
45/**
46 * amdgpu_driver_unload_kms - Main unload function for KMS.
47 *
48 * @dev: drm dev pointer
49 *
50 * This is the main unload function for KMS (all asics).
51 * Returns 0 on success.
52 */
53int amdgpu_driver_unload_kms(struct drm_device *dev)
54{
55 struct amdgpu_device *adev = dev->dev_private;
56
57 if (adev == NULL)
58 return 0;
59
60 if (adev->rmmio == NULL)
61 goto done_free;
62
4a788547
LW		 63 if (amdgpu_device_is_px(dev)) {
64 pm_runtime_get_sync(dev->dev);
6ce62d8b 65 pm_runtime_forbid(dev->dev);
4a788547 66 }
d38ceaf9 67
130e0371
OG		 68 amdgpu_amdkfd_device_fini(adev);
69
d38ceaf9
AD		 70 amdgpu_acpi_fini(adev);
71
72 amdgpu_device_fini(adev);
73
74done_free:
75 kfree(adev);
76 dev->dev_private = NULL;
77 return 0;
78}
79
80/**
81 * amdgpu_driver_load_kms - Main load function for KMS.
82 *
83 * @dev: drm dev pointer
84 * @flags: device flags
85 *
86 * This is the main load function for KMS (all asics).
87 * Returns 0 on success, error on failure.
88 */
89int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
90{
91 struct amdgpu_device *adev;
92 int r, acpi_status;
93
94 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
95 if (adev == NULL) {
96 return -ENOMEM;
97 }
98 dev->dev_private = (void *)adev;
99
100 if ((amdgpu_runtime_pm != 0) &&
101 amdgpu_has_atpx() &&
2f7d10b3
JZ		 102 ((flags & AMD_IS_APU) == 0))
103 flags |= AMD_IS_PX;
d38ceaf9
AD		 104
105 /* amdgpu_device_init should report only fatal error
106 * like memory allocation failure or iomapping failure,
107 * or memory manager initialization failure, it must
108 * properly initialize the GPU MC controller and permit
109 * VRAM allocation
110 */
111 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
112 if (r) {
113 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
114 goto out;
115 }
116
117 /* Call ACPI methods: require modeset init
118 * but failure is not fatal
119 */
120 if (!r) {
121 acpi_status = amdgpu_acpi_init(adev);
122 if (acpi_status)
123 dev_dbg(&dev->pdev->dev,
124 "Error during ACPI methods call\n");
125 }
126
130e0371
OG		 127 amdgpu_amdkfd_load_interface(adev);
128 amdgpu_amdkfd_device_probe(adev);
129 amdgpu_amdkfd_device_init(adev);
130
d38ceaf9
AD		 131 if (amdgpu_device_is_px(dev)) {
132 pm_runtime_use_autosuspend(dev->dev);
133 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
134 pm_runtime_set_active(dev->dev);
135 pm_runtime_allow(dev->dev);
136 pm_runtime_mark_last_busy(dev->dev);
137 pm_runtime_put_autosuspend(dev->dev);
138 }
139
140out:
c9c9bbd7
LW		 141 if (r) {
142 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
143 if (adev->rmmio && amdgpu_device_is_px(dev))
144 pm_runtime_put_noidle(dev->dev);
d38ceaf9 145 amdgpu_driver_unload_kms(dev);
c9c9bbd7 146 }
d38ceaf9
AD		 147
148 return r;
149}
150
000cab9a
HR		 151static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
152 struct drm_amdgpu_query_fw *query_fw,
153 struct amdgpu_device *adev)
154{
155 switch (query_fw->fw_type) {
156 case AMDGPU_INFO_FW_VCE:
157 fw_info->ver = adev->vce.fw_version;
158 fw_info->feature = adev->vce.fb_version;
159 break;
160 case AMDGPU_INFO_FW_UVD:
161 fw_info->ver = adev->uvd.fw_version;
162 fw_info->feature = 0;
163 break;
164 case AMDGPU_INFO_FW_GMC:
165 fw_info->ver = adev->mc.fw_version;
166 fw_info->feature = 0;
167 break;
168 case AMDGPU_INFO_FW_GFX_ME:
169 fw_info->ver = adev->gfx.me_fw_version;
170 fw_info->feature = adev->gfx.me_feature_version;
171 break;
172 case AMDGPU_INFO_FW_GFX_PFP:
173 fw_info->ver = adev->gfx.pfp_fw_version;
174 fw_info->feature = adev->gfx.pfp_feature_version;
175 break;
176 case AMDGPU_INFO_FW_GFX_CE:
177 fw_info->ver = adev->gfx.ce_fw_version;
178 fw_info->feature = adev->gfx.ce_feature_version;
179 break;
180 case AMDGPU_INFO_FW_GFX_RLC:
181 fw_info->ver = adev->gfx.rlc_fw_version;
182 fw_info->feature = adev->gfx.rlc_feature_version;
183 break;
184 case AMDGPU_INFO_FW_GFX_MEC:
185 if (query_fw->index == 0) {
186 fw_info->ver = adev->gfx.mec_fw_version;
187 fw_info->feature = adev->gfx.mec_feature_version;
188 } else if (query_fw->index == 1) {
189 fw_info->ver = adev->gfx.mec2_fw_version;
190 fw_info->feature = adev->gfx.mec2_feature_version;
191 } else
192 return -EINVAL;
193 break;
194 case AMDGPU_INFO_FW_SMC:
195 fw_info->ver = adev->pm.fw_version;
196 fw_info->feature = 0;
197 break;
198 case AMDGPU_INFO_FW_SDMA:
199 if (query_fw->index >= adev->sdma.num_instances)
200 return -EINVAL;
201 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
202 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
203 break;
204 default:
205 return -EINVAL;
206 }
207 return 0;
208}
209
d38ceaf9
AD		 210/*
211 * Userspace get information ioctl
212 */
213/**
214 * amdgpu_info_ioctl - answer a device specific request.
215 *
216 * @adev: amdgpu device pointer
217 * @data: request object
218 * @filp: drm filp
219 *
220 * This function is used to pass device specific parameters to the userspace
221 * drivers. Examples include: pci device id, pipeline parms, tiling params,
222 * etc. (all asics).
223 * Returns 0 on success, -EINVAL on failure.
224 */
225static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
226{
227 struct amdgpu_device *adev = dev->dev_private;
228 struct drm_amdgpu_info *info = data;
229 struct amdgpu_mode_info *minfo = &adev->mode_info;
230 void __user *out = (void __user *)(long)info->return_pointer;
231 uint32_t size = info->return_size;
232 struct drm_crtc *crtc;
233 uint32_t ui32 = 0;
234 uint64_t ui64 = 0;
235 int i, found;
236
237 if (!info->return_size || !info->return_pointer)
238 return -EINVAL;
239
240 switch (info->query) {
241 case AMDGPU_INFO_ACCEL_WORKING:
242 ui32 = adev->accel_working;
243 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
244 case AMDGPU_INFO_CRTC_FROM_ID:
245 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
246 crtc = (struct drm_crtc *)minfo->crtcs[i];
247 if (crtc && crtc->base.id == info->mode_crtc.id) {
248 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
249 ui32 = amdgpu_crtc->crtc_id;
250 found = 1;
251 break;
252 }
253 }
254 if (!found) {
255 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
256 return -EINVAL;
257 }
258 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
259 case AMDGPU_INFO_HW_IP_INFO: {
260 struct drm_amdgpu_info_hw_ip ip = {};
5fc3aeeb 261 enum amd_ip_block_type type;
d38ceaf9 262 uint32_t ring_mask = 0;
71062f43
KW		 263 uint32_t ib_start_alignment = 0;
264 uint32_t ib_size_alignment = 0;
d38ceaf9
AD		 265
266 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
267 return -EINVAL;
268
269 switch (info->query_hw_ip.type) {
270 case AMDGPU_HW_IP_GFX:
5fc3aeeb 271 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 272 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
273 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
71062f43
KW		 274 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
275 ib_size_alignment = 8;
d38ceaf9
AD		 276 break;
277 case AMDGPU_HW_IP_COMPUTE:
5fc3aeeb 278 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 279 for (i = 0; i < adev->gfx.num_compute_rings; i++)
280 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
71062f43
KW		 281 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
282 ib_size_alignment = 8;
d38ceaf9
AD		 283 break;
284 case AMDGPU_HW_IP_DMA:
5fc3aeeb 285 type = AMD_IP_BLOCK_TYPE_SDMA;
c113ea1c
AD		 286 for (i = 0; i < adev->sdma.num_instances; i++)
287 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
71062f43
KW		 288 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
289 ib_size_alignment = 1;
d38ceaf9
AD		 290 break;
291 case AMDGPU_HW_IP_UVD:
5fc3aeeb 292 type = AMD_IP_BLOCK_TYPE_UVD;
d38ceaf9 293 ring_mask = adev->uvd.ring.ready ? 1 : 0;
71062f43 294 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
c4795ca6 295 ib_size_alignment = 16;
d38ceaf9
AD		 296 break;
297 case AMDGPU_HW_IP_VCE:
5fc3aeeb 298 type = AMD_IP_BLOCK_TYPE_VCE;
75c65480 299 for (i = 0; i < adev->vce.num_rings; i++)
d38ceaf9 300 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
71062f43 301 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
a22f803c 302 ib_size_alignment = 1;
d38ceaf9
AD		 303 break;
304 default:
305 return -EINVAL;
306 }
307
308 for (i = 0; i < adev->num_ip_blocks; i++) {
309 if (adev->ip_blocks[i].type == type &&
8faf0e08 310 adev->ip_block_status[i].valid) {
d38ceaf9
AD		 311 ip.hw_ip_version_major = adev->ip_blocks[i].major;
312 ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
313 ip.capabilities_flags = 0;
314 ip.available_rings = ring_mask;
71062f43
KW		 315 ip.ib_start_alignment = ib_start_alignment;
316 ip.ib_size_alignment = ib_size_alignment;
d38ceaf9
AD		 317 break;
318 }
319 }
320 return copy_to_user(out, &ip,
321 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
322 }
323 case AMDGPU_INFO_HW_IP_COUNT: {
5fc3aeeb 324 enum amd_ip_block_type type;
d38ceaf9
AD		 325 uint32_t count = 0;
326
327 switch (info->query_hw_ip.type) {
328 case AMDGPU_HW_IP_GFX:
5fc3aeeb 329 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 330 break;
331 case AMDGPU_HW_IP_COMPUTE:
5fc3aeeb 332 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf9
AD		 333 break;
334 case AMDGPU_HW_IP_DMA:
5fc3aeeb 335 type = AMD_IP_BLOCK_TYPE_SDMA;
d38ceaf9
AD		 336 break;
337 case AMDGPU_HW_IP_UVD:
5fc3aeeb 338 type = AMD_IP_BLOCK_TYPE_UVD;
d38ceaf9
AD		 339 break;
340 case AMDGPU_HW_IP_VCE:
5fc3aeeb 341 type = AMD_IP_BLOCK_TYPE_VCE;
d38ceaf9
AD		 342 break;
343 default:
344 return -EINVAL;
345 }
346
347 for (i = 0; i < adev->num_ip_blocks; i++)
348 if (adev->ip_blocks[i].type == type &&
8faf0e08 349 adev->ip_block_status[i].valid &&
d38ceaf9
AD		 350 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
351 count++;
352
353 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
354 }
355 case AMDGPU_INFO_TIMESTAMP:
b95e31fd 356 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
d38ceaf9
AD		 357 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
358 case AMDGPU_INFO_FW_VERSION: {
359 struct drm_amdgpu_info_firmware fw_info;
000cab9a 360 int ret;
d38ceaf9
AD		 361
362 /* We only support one instance of each IP block right now. */
363 if (info->query_fw.ip_instance != 0)
364 return -EINVAL;
365
000cab9a
HR		 366 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
367 if (ret)
368 return ret;
369
d38ceaf9
AD		 370 return copy_to_user(out, &fw_info,
371 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
372 }
373 case AMDGPU_INFO_NUM_BYTES_MOVED:
374 ui64 = atomic64_read(&adev->num_bytes_moved);
375 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
83a59b63
MO		 376 case AMDGPU_INFO_NUM_EVICTIONS:
377 ui64 = atomic64_read(&adev->num_evictions);
378 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
d38ceaf9
AD		 379 case AMDGPU_INFO_VRAM_USAGE:
380 ui64 = atomic64_read(&adev->vram_usage);
381 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
382 case AMDGPU_INFO_VIS_VRAM_USAGE:
383 ui64 = atomic64_read(&adev->vram_vis_usage);
384 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
385 case AMDGPU_INFO_GTT_USAGE:
386 ui64 = atomic64_read(&adev->gtt_usage);
387 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
388 case AMDGPU_INFO_GDS_CONFIG: {
389 struct drm_amdgpu_info_gds gds_info;
390
c92b90cc 391 memset(&gds_info, 0, sizeof(gds_info));
d38ceaf9
AD		 392 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
393 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
394 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
395 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
396 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
397 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
398 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
399 return copy_to_user(out, &gds_info,
400 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
401 }
402 case AMDGPU_INFO_VRAM_GTT: {
403 struct drm_amdgpu_info_vram_gtt vram_gtt;
404
405 vram_gtt.vram_size = adev->mc.real_vram_size;
7c0ecda1 406 vram_gtt.vram_size -= adev->vram_pin_size;
d38ceaf9 407 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
e131b914 408 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
d38ceaf9
AD		 409 vram_gtt.gtt_size = adev->mc.gtt_size;
410 vram_gtt.gtt_size -= adev->gart_pin_size;
411 return copy_to_user(out, &vram_gtt,
412 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
413 }
9f6163e7
JZ		 414 case AMDGPU_INFO_VRAM_GTT_TOTAL: {
415 struct drm_amdgpu_info_vram_gtt_total vram_gtt_total;
416
417 vram_gtt_total.vram_total_size = adev->mc.real_vram_size;
418 vram_gtt_total.vram_cpu_accessible_total_size = adev->mc.visible_vram_size;
419 vram_gtt_total.gtt_total_size = adev->mc.gtt_size;
420 return copy_to_user(out, &vram_gtt_total,
421 min((size_t)size, sizeof(vram_gtt_total)))
422 ? -EFAULT : 0;
423 }
cfa32556
JZ		 424 case AMDGPU_INFO_VRAM_GTT_MAX: {
425 struct drm_amdgpu_info_vram_gtt_max vram_gtt_max;
426 u64 max_size;
427
428 max_size = adev->mc.real_vram_size - adev->vram_pin_size;
429 vram_gtt_max.vram_max_size = max_size * 3 / 4;
430
431 max_size = adev->mc.visible_vram_size - (adev->vram_pin_size -
432 adev->invisible_pin_size);
433 vram_gtt_max.vram_cpu_accessible_max_size = max_size * 3 / 4;
434
435 max_size = adev->mc.gtt_size - adev->gart_pin_size;
436 vram_gtt_max.gtt_max_size = max_size * 3 / 4;
437
438 return copy_to_user(out, &vram_gtt_max,
439 min((size_t)size, sizeof(vram_gtt_max)))
440 ? -EFAULT : 0;
441 }
d38ceaf9 442 case AMDGPU_INFO_READ_MMR_REG: {
0d2edd37 443 unsigned n, alloc_size;
d38ceaf9
AD		 444 uint32_t *regs;
445 unsigned se_num = (info->read_mmr_reg.instance >>
446 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
447 AMDGPU_INFO_MMR_SE_INDEX_MASK;
448 unsigned sh_num = (info->read_mmr_reg.instance >>
449 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
450 AMDGPU_INFO_MMR_SH_INDEX_MASK;
451
452 /* set full masks if the userspace set all bits
453 * in the bitfields */
454 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
455 se_num = 0xffffffff;
456 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
457 sh_num = 0xffffffff;
458
0d2edd37 459 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
d38ceaf9
AD		 460 if (!regs)
461 return -ENOMEM;
0d2edd37 462 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
d38ceaf9
AD		 463
464 for (i = 0; i < info->read_mmr_reg.count; i++)
465 if (amdgpu_asic_read_register(adev, se_num, sh_num,
466 info->read_mmr_reg.dword_offset + i,
467 &regs[i])) {
468 DRM_DEBUG_KMS("unallowed offset %#x\n",
469 info->read_mmr_reg.dword_offset + i);
470 kfree(regs);
471 return -EFAULT;
472 }
473 n = copy_to_user(out, regs, min(size, alloc_size));
474 kfree(regs);
475 return n ? -EFAULT : 0;
476 }
477 case AMDGPU_INFO_DEV_INFO: {
c193fa91 478 struct drm_amdgpu_info_device dev_info = {};
d38ceaf9
AD		 479
480 dev_info.device_id = dev->pdev->device;
481 dev_info.chip_rev = adev->rev_id;
482 dev_info.external_rev = adev->external_rev_id;
483 dev_info.pci_rev = dev->pdev->revision;
484 dev_info.family = adev->family;
485 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
486 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
487 /* return all clocks in KHz */
488 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
32bf7106 489 if (adev->pm.dpm_enabled) {
d38ceaf9
AD		 490 dev_info.max_engine_clock =
491 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
32bf7106
KW		 492 dev_info.max_memory_clock =
493 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10;
494 } else {
d38ceaf9 495 dev_info.max_engine_clock = adev->pm.default_sclk * 10;
32bf7106
KW		 496 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
497 }
d38ceaf9 498 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
0b10029d
AD		 499 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
500 adev->gfx.config.max_shader_engines;
d38ceaf9
AD		 501 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
502 dev_info._pad = 0;
503 dev_info.ids_flags = 0;
2f7d10b3 504 if (adev->flags & AMD_IS_APU)
d38ceaf9
AD		 505 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
506 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
02b70c8c 507 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
c548b345 508 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
d38ceaf9
AD		 509 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
510 AMDGPU_GPU_PAGE_SIZE;
511 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
512
7dae69a2
AD		 513 dev_info.cu_active_number = adev->gfx.cu_info.number;
514 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
a101a899 515 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
7dae69a2
AD		 516 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
517 sizeof(adev->gfx.cu_info.bitmap));
81c59f54
KW		 518 dev_info.vram_type = adev->mc.vram_type;
519 dev_info.vram_bit_width = adev->mc.vram_width;
fa92754e 520 dev_info.vce_harvest_config = adev->vce.harvest_config;
d38ceaf9
AD		 521
522 return copy_to_user(out, &dev_info,
523 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
524 }
525 default:
526 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
527 return -EINVAL;
528 }
529 return 0;
530}
531
532
533/*
534 * Outdated mess for old drm with Xorg being in charge (void function now).
535 */
536/**
8b7530b1 537 * amdgpu_driver_lastclose_kms - drm callback for last close
d38ceaf9
AD		 538 *
539 * @dev: drm dev pointer
540 *
1694467b 541 * Switch vga_switcheroo state after last close (all asics).
d38ceaf9
AD		 542 */
543void amdgpu_driver_lastclose_kms(struct drm_device *dev)
544{
8b7530b1
AD		 545 struct amdgpu_device *adev = dev->dev_private;
546
547 amdgpu_fbdev_restore_mode(adev);
d38ceaf9
AD		 548 vga_switcheroo_process_delayed_switch();
549}
550
551/**
552 * amdgpu_driver_open_kms - drm callback for open
553 *
554 * @dev: drm dev pointer
555 * @file_priv: drm file
556 *
557 * On device open, init vm on cayman+ (all asics).
558 * Returns 0 on success, error on failure.
559 */
560int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
561{
562 struct amdgpu_device *adev = dev->dev_private;
563 struct amdgpu_fpriv *fpriv;
564 int r;
565
566 file_priv->driver_priv = NULL;
567
568 r = pm_runtime_get_sync(dev->dev);
569 if (r < 0)
570 return r;
571
572 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
dc08267a
AD		 573 if (unlikely(!fpriv)) {
574 r = -ENOMEM;
575 goto out_suspend;
576 }
d38ceaf9
AD		 577
578 r = amdgpu_vm_init(adev, &fpriv->vm);
dc08267a
AD		 579 if (r) {
580 kfree(fpriv);
581 goto out_suspend;
582 }
d38ceaf9
AD		 583
584 mutex_init(&fpriv->bo_list_lock);
585 idr_init(&fpriv->bo_list_handles);
586
efd4ccb5 587 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
d38ceaf9
AD		 588
589 file_priv->driver_priv = fpriv;
590
dc08267a 591out_suspend:
d38ceaf9
AD		 592 pm_runtime_mark_last_busy(dev->dev);
593 pm_runtime_put_autosuspend(dev->dev);
d38ceaf9
AD		 594
595 return r;
596}
597
598/**
599 * amdgpu_driver_postclose_kms - drm callback for post close
600 *
601 * @dev: drm dev pointer
602 * @file_priv: drm file
603 *
604 * On device post close, tear down vm on cayman+ (all asics).
605 */
606void amdgpu_driver_postclose_kms(struct drm_device *dev,
607 struct drm_file *file_priv)
608{
609 struct amdgpu_device *adev = dev->dev_private;
610 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
611 struct amdgpu_bo_list *list;
612 int handle;
613
614 if (!fpriv)
615 return;
616
02537d63
CK		 617 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
618
cd437e37
LL		 619 amdgpu_uvd_free_handles(adev, file_priv);
620 amdgpu_vce_free_handles(adev, file_priv);
621
d38ceaf9
AD		 622 amdgpu_vm_fini(adev, &fpriv->vm);
623
624 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
625 amdgpu_bo_list_free(list);
626
627 idr_destroy(&fpriv->bo_list_handles);
628 mutex_destroy(&fpriv->bo_list_lock);
629
d38ceaf9
AD		 630 kfree(fpriv);
631 file_priv->driver_priv = NULL;
d6bda7b4
AD		 632
633 pm_runtime_mark_last_busy(dev->dev);
634 pm_runtime_put_autosuspend(dev->dev);
d38ceaf9
AD		 635}
636
637/**
638 * amdgpu_driver_preclose_kms - drm callback for pre close
639 *
640 * @dev: drm dev pointer
641 * @file_priv: drm file
642 *
643 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
644 * (all asics).
645 */
646void amdgpu_driver_preclose_kms(struct drm_device *dev,
647 struct drm_file *file_priv)
648{
d6bda7b4 649 pm_runtime_get_sync(dev->dev);
d38ceaf9
AD		 650}
651
652/*
653 * VBlank related functions.
654 */
655/**
656 * amdgpu_get_vblank_counter_kms - get frame count
657 *
658 * @dev: drm dev pointer
88e72717 659 * @pipe: crtc to get the frame count from
d38ceaf9
AD		 660 *
661 * Gets the frame count on the requested crtc (all asics).
662 * Returns frame count on success, -EINVAL on failure.
663 */
88e72717 664u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
d38ceaf9
AD		 665{
666 struct amdgpu_device *adev = dev->dev_private;
8e36f9d3
AD		 667 int vpos, hpos, stat;
668 u32 count;
d38ceaf9 669
88e72717
TR		 670 if (pipe >= adev->mode_info.num_crtc) {
671 DRM_ERROR("Invalid crtc %u\n", pipe);
d38ceaf9
AD		 672 return -EINVAL;
673 }
674
8e36f9d3
AD		 675 /* The hw increments its frame counter at start of vsync, not at start
676 * of vblank, as is required by DRM core vblank counter handling.
677 * Cook the hw count here to make it appear to the caller as if it
678 * incremented at start of vblank. We measure distance to start of
679 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
680 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
681 * result by 1 to give the proper appearance to caller.
682 */
683 if (adev->mode_info.crtcs[pipe]) {
684 /* Repeat readout if needed to provide stable result if
685 * we cross start of vsync during the queries.
686 */
687 do {
688 count = amdgpu_display_vblank_get_counter(adev, pipe);
689 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
690 * distance to start of vblank, instead of regular
691 * vertical scanout pos.
692 */
693 stat = amdgpu_get_crtc_scanoutpos(
694 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
695 &vpos, &hpos, NULL, NULL,
696 &adev->mode_info.crtcs[pipe]->base.hwmode);
697 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
698
699 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
700 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
701 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
702 } else {
703 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
704 pipe, vpos);
705
706 /* Bump counter if we are at >= leading edge of vblank,
707 * but before vsync where vpos would turn negative and
708 * the hw counter really increments.
709 */
710 if (vpos >= 0)
711 count++;
712 }
713 } else {
714 /* Fallback to use value as is. */
715 count = amdgpu_display_vblank_get_counter(adev, pipe);
716 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
717 }
718
719 return count;
d38ceaf9
AD		 720}
721
722/**
723 * amdgpu_enable_vblank_kms - enable vblank interrupt
724 *
725 * @dev: drm dev pointer
88e72717 726 * @pipe: crtc to enable vblank interrupt for
d38ceaf9
AD		 727 *
728 * Enable the interrupt on the requested crtc (all asics).
729 * Returns 0 on success, -EINVAL on failure.
730 */
88e72717 731int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
d38ceaf9
AD		 732{
733 struct amdgpu_device *adev = dev->dev_private;
88e72717 734 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
d38ceaf9
AD		 735
736 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
737}
738
739/**
740 * amdgpu_disable_vblank_kms - disable vblank interrupt
741 *
742 * @dev: drm dev pointer
88e72717 743 * @pipe: crtc to disable vblank interrupt for
d38ceaf9
AD		 744 *
745 * Disable the interrupt on the requested crtc (all asics).
746 */
88e72717 747void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
d38ceaf9
AD		 748{
749 struct amdgpu_device *adev = dev->dev_private;
88e72717 750 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
d38ceaf9
AD		 751
752 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
753}
754
755/**
756 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
757 *
758 * @dev: drm dev pointer
759 * @crtc: crtc to get the timestamp for
760 * @max_error: max error
761 * @vblank_time: time value
762 * @flags: flags passed to the driver
763 *
764 * Gets the timestamp on the requested crtc based on the
765 * scanout position. (all asics).
766 * Returns postive status flags on success, negative error on failure.
767 */
88e72717 768int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
d38ceaf9
AD		 769 int *max_error,
770 struct timeval *vblank_time,
771 unsigned flags)
772{
88e72717 773 struct drm_crtc *crtc;
d38ceaf9
AD		 774 struct amdgpu_device *adev = dev->dev_private;
775
88e72717
TR		 776 if (pipe >= dev->num_crtcs) {
777 DRM_ERROR("Invalid crtc %u\n", pipe);
d38ceaf9
AD		 778 return -EINVAL;
779 }
780
781 /* Get associated drm_crtc: */
88e72717 782 crtc = &adev->mode_info.crtcs[pipe]->base;
9ddf940f
HW		 783 if (!crtc) {
784 /* This can occur on driver load if some component fails to
785 * initialize completely and driver is unloaded */
786 DRM_ERROR("Uninitialized crtc %d\n", pipe);
787 return -EINVAL;
788 }
d38ceaf9
AD		 789
790 /* Helper routine in DRM core does all the work: */
88e72717 791 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
d38ceaf9 792 vblank_time, flags,
88e72717 793 &crtc->hwmode);
d38ceaf9
AD		 794}
795
796const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
f8c47144
DV		 797 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
798 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
799 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
d38ceaf9 800 /* KMS */
f8c47144
DV		 801 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
802 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
803 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
804 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
805 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
806 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
807 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
808 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
809 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
d38ceaf9 810};
f498d9ed 811const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
50ab2533
HR		 812
813/*
814 * Debugfs info
815 */
816#if defined(CONFIG_DEBUG_FS)
817
818static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
819{
820 struct drm_info_node *node = (struct drm_info_node *) m->private;
821 struct drm_device *dev = node->minor->dev;
822 struct amdgpu_device *adev = dev->dev_private;
823 struct drm_amdgpu_info_firmware fw_info;
824 struct drm_amdgpu_query_fw query_fw;
825 int ret, i;
826
827 /* VCE */
828 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
829 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
830 if (ret)
831 return ret;
832 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
833 fw_info.feature, fw_info.ver);
834
835 /* UVD */
836 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
837 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
838 if (ret)
839 return ret;
840 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
841 fw_info.feature, fw_info.ver);
842
843 /* GMC */
844 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
845 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
846 if (ret)
847 return ret;
848 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
849 fw_info.feature, fw_info.ver);
850
851 /* ME */
852 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
853 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
854 if (ret)
855 return ret;
856 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
857 fw_info.feature, fw_info.ver);
858
859 /* PFP */
860 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
861 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
862 if (ret)
863 return ret;
864 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
865 fw_info.feature, fw_info.ver);
866
867 /* CE */
868 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
869 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
870 if (ret)
871 return ret;
872 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
873 fw_info.feature, fw_info.ver);
874
875 /* RLC */
876 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
877 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
878 if (ret)
879 return ret;
880 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
881 fw_info.feature, fw_info.ver);
882
883 /* MEC */
884 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
885 query_fw.index = 0;
886 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
887 if (ret)
888 return ret;
889 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
890 fw_info.feature, fw_info.ver);
891
892 /* MEC2 */
893 if (adev->asic_type == CHIP_KAVERI ||
894 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
895 query_fw.index = 1;
896 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
897 if (ret)
898 return ret;
899 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
900 fw_info.feature, fw_info.ver);
901 }
902
903 /* SMC */
904 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
905 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
906 if (ret)
907 return ret;
908 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
909 fw_info.feature, fw_info.ver);
910
911 /* SDMA */
912 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
913 for (i = 0; i < adev->sdma.num_instances; i++) {
914 query_fw.index = i;
915 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
916 if (ret)
917 return ret;
918 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
919 i, fw_info.feature, fw_info.ver);
920 }
921
922 return 0;
923}
924
925static const struct drm_info_list amdgpu_firmware_info_list[] = {
926 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
927};
928#endif
929
930int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
931{
932#if defined(CONFIG_DEBUG_FS)
933 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
934 ARRAY_SIZE(amdgpu_firmware_info_list));
935#else
936 return 0;
937#endif
938}
Linux 6.x block layer and io_uring tree(s)