projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gpu/drm/amdgpu: Fix build when CONFIG_DEBUG_FS is not set
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
45#include <drm/drm_gem.h>
7e5a547f 46#include <drm/amdgpu_drm.h>
97b2e202 47
5fc3aeeb 48#include "amd_shared.h"
97b2e202
AD		 49#include "amdgpu_family.h"
50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
55
56/*
57 * Modules parameters.
58 */
59extern int amdgpu_modeset;
60extern int amdgpu_vram_limit;
61extern int amdgpu_gart_size;
62extern int amdgpu_benchmarking;
63extern int amdgpu_testing;
64extern int amdgpu_audio;
65extern int amdgpu_disp_priority;
66extern int amdgpu_hw_i2c;
67extern int amdgpu_pcie_gen2;
68extern int amdgpu_msi;
69extern int amdgpu_lockup_timeout;
70extern int amdgpu_dpm;
71extern int amdgpu_smc_load_fw;
72extern int amdgpu_aspm;
73extern int amdgpu_runtime_pm;
74extern int amdgpu_hard_reset;
75extern unsigned amdgpu_ip_block_mask;
76extern int amdgpu_bapm;
77extern int amdgpu_deep_color;
78extern int amdgpu_vm_size;
79extern int amdgpu_vm_block_size;
80
81#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
82#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
83/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
84#define AMDGPU_IB_POOL_SIZE 16
85#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
86#define AMDGPUFB_CONN_LIMIT 4
87#define AMDGPU_BIOS_NUM_SCRATCH 8
88
97b2e202
AD		 89/* max number of rings */
90#define AMDGPU_MAX_RINGS 16
91#define AMDGPU_MAX_GFX_RINGS 1
92#define AMDGPU_MAX_COMPUTE_RINGS 8
93#define AMDGPU_MAX_VCE_RINGS 2
94
95/* number of hw syncs before falling back on blocking */
96#define AMDGPU_NUM_SYNCS 4
97
98/* hardcode that limit for now */
99#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
100
101/* hard reset data */
102#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
103
104/* reset flags */
105#define AMDGPU_RESET_GFX (1 << 0)
106#define AMDGPU_RESET_COMPUTE (1 << 1)
107#define AMDGPU_RESET_DMA (1 << 2)
108#define AMDGPU_RESET_CP (1 << 3)
109#define AMDGPU_RESET_GRBM (1 << 4)
110#define AMDGPU_RESET_DMA1 (1 << 5)
111#define AMDGPU_RESET_RLC (1 << 6)
112#define AMDGPU_RESET_SEM (1 << 7)
113#define AMDGPU_RESET_IH (1 << 8)
114#define AMDGPU_RESET_VMC (1 << 9)
115#define AMDGPU_RESET_MC (1 << 10)
116#define AMDGPU_RESET_DISPLAY (1 << 11)
117#define AMDGPU_RESET_UVD (1 << 12)
118#define AMDGPU_RESET_VCE (1 << 13)
119#define AMDGPU_RESET_VCE1 (1 << 14)
120
121/* CG block flags */
122#define AMDGPU_CG_BLOCK_GFX (1 << 0)
123#define AMDGPU_CG_BLOCK_MC (1 << 1)
124#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
125#define AMDGPU_CG_BLOCK_UVD (1 << 3)
126#define AMDGPU_CG_BLOCK_VCE (1 << 4)
127#define AMDGPU_CG_BLOCK_HDP (1 << 5)
128#define AMDGPU_CG_BLOCK_BIF (1 << 6)
129
130/* CG flags */
131#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
132#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
133#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
134#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
135#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
136#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
137#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
138#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
139#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
140#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
141#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
142#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
143#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
144#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
145#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
146#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
147#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
148
149/* PG flags */
150#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
151#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
152#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
153#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
154#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
155#define AMDGPU_PG_SUPPORT_CP (1 << 5)
156#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
157#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
158#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
159#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
160#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
161
162/* GFX current status */
163#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
164#define AMDGPU_GFX_SAFE_MODE 0x00000001L
165#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
166#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
167#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
168
169/* max cursor sizes (in pixels) */
170#define CIK_CURSOR_WIDTH 128
171#define CIK_CURSOR_HEIGHT 128
172
173struct amdgpu_device;
174struct amdgpu_fence;
175struct amdgpu_ib;
176struct amdgpu_vm;
177struct amdgpu_ring;
178struct amdgpu_semaphore;
179struct amdgpu_cs_parser;
180struct amdgpu_irq_src;
181
182enum amdgpu_cp_irq {
183 AMDGPU_CP_IRQ_GFX_EOP = 0,
184 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
192
193 AMDGPU_CP_IRQ_LAST
194};
195
196enum amdgpu_sdma_irq {
197 AMDGPU_SDMA_IRQ_TRAP0 = 0,
198 AMDGPU_SDMA_IRQ_TRAP1,
199
200 AMDGPU_SDMA_IRQ_LAST
201};
202
203enum amdgpu_thermal_irq {
204 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
205 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
206
207 AMDGPU_THERMAL_IRQ_LAST
208};
209
97b2e202 210int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 211 enum amd_ip_block_type block_type,
212 enum amd_clockgating_state state);
97b2e202 213int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 214 enum amd_ip_block_type block_type,
215 enum amd_powergating_state state);
97b2e202
AD		 216
217struct amdgpu_ip_block_version {
5fc3aeeb 218 enum amd_ip_block_type type;
97b2e202
AD		 219 u32 major;
220 u32 minor;
221 u32 rev;
5fc3aeeb 222 const struct amd_ip_funcs *funcs;
97b2e202
AD		 223};
224
225int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 226 enum amd_ip_block_type type,
97b2e202
AD		 227 u32 major, u32 minor);
228
229const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
230 struct amdgpu_device *adev,
5fc3aeeb 231 enum amd_ip_block_type type);
97b2e202
AD		 232
233/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
234struct amdgpu_buffer_funcs {
235 /* maximum bytes in a single operation */
236 uint32_t copy_max_bytes;
237
238 /* number of dw to reserve per operation */
239 unsigned copy_num_dw;
240
241 /* used for buffer migration */
242 void (*emit_copy_buffer)(struct amdgpu_ring *ring,
243 /* src addr in bytes */
244 uint64_t src_offset,
245 /* dst addr in bytes */
246 uint64_t dst_offset,
247 /* number of byte to transfer */
248 uint32_t byte_count);
249
250 /* maximum bytes in a single operation */
251 uint32_t fill_max_bytes;
252
253 /* number of dw to reserve per operation */
254 unsigned fill_num_dw;
255
256 /* used for buffer clearing */
257 void (*emit_fill_buffer)(struct amdgpu_ring *ring,
258 /* value to write to memory */
259 uint32_t src_data,
260 /* dst addr in bytes */
261 uint64_t dst_offset,
262 /* number of byte to fill */
263 uint32_t byte_count);
264};
265
266/* provided by hw blocks that can write ptes, e.g., sdma */
267struct amdgpu_vm_pte_funcs {
268 /* copy pte entries from GART */
269 void (*copy_pte)(struct amdgpu_ib *ib,
270 uint64_t pe, uint64_t src,
271 unsigned count);
272 /* write pte one entry at a time with addr mapping */
273 void (*write_pte)(struct amdgpu_ib *ib,
274 uint64_t pe,
275 uint64_t addr, unsigned count,
276 uint32_t incr, uint32_t flags);
277 /* for linear pte/pde updates without addr mapping */
278 void (*set_pte_pde)(struct amdgpu_ib *ib,
279 uint64_t pe,
280 uint64_t addr, unsigned count,
281 uint32_t incr, uint32_t flags);
282 /* pad the indirect buffer to the necessary number of dw */
283 void (*pad_ib)(struct amdgpu_ib *ib);
284};
285
286/* provided by the gmc block */
287struct amdgpu_gart_funcs {
288 /* flush the vm tlb via mmio */
289 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
290 uint32_t vmid);
291 /* write pte/pde updates using the cpu */
292 int (*set_pte_pde)(struct amdgpu_device *adev,
293 void *cpu_pt_addr, /* cpu addr of page table */
294 uint32_t gpu_page_idx, /* pte/pde to update */
295 uint64_t addr, /* addr to write into pte/pde */
296 uint32_t flags); /* access flags */
297};
298
299/* provided by the ih block */
300struct amdgpu_ih_funcs {
301 /* ring read/write ptr handling, called from interrupt context */
302 u32 (*get_wptr)(struct amdgpu_device *adev);
303 void (*decode_iv)(struct amdgpu_device *adev,
304 struct amdgpu_iv_entry *entry);
305 void (*set_rptr)(struct amdgpu_device *adev);
306};
307
308/* provided by hw blocks that expose a ring buffer for commands */
309struct amdgpu_ring_funcs {
310 /* ring read/write ptr handling */
311 u32 (*get_rptr)(struct amdgpu_ring *ring);
312 u32 (*get_wptr)(struct amdgpu_ring *ring);
313 void (*set_wptr)(struct amdgpu_ring *ring);
314 /* validating and patching of IBs */
315 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
316 /* command emit functions */
317 void (*emit_ib)(struct amdgpu_ring *ring,
318 struct amdgpu_ib *ib);
319 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 320 uint64_t seq, unsigned flags);
97b2e202
AD		 321 bool (*emit_semaphore)(struct amdgpu_ring *ring,
322 struct amdgpu_semaphore *semaphore,
323 bool emit_wait);
324 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
325 uint64_t pd_addr);
d2edb07b 326 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 327 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
328 uint32_t gds_base, uint32_t gds_size,
329 uint32_t gws_base, uint32_t gws_size,
330 uint32_t oa_base, uint32_t oa_size);
331 /* testing functions */
332 int (*test_ring)(struct amdgpu_ring *ring);
333 int (*test_ib)(struct amdgpu_ring *ring);
334 bool (*is_lockup)(struct amdgpu_ring *ring);
335};
336
337/*
338 * BIOS.
339 */
340bool amdgpu_get_bios(struct amdgpu_device *adev);
341bool amdgpu_read_bios(struct amdgpu_device *adev);
342
343/*
344 * Dummy page
345 */
346struct amdgpu_dummy_page {
347 struct page *page;
348 dma_addr_t addr;
349};
350int amdgpu_dummy_page_init(struct amdgpu_device *adev);
351void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
352
353
354/*
355 * Clocks
356 */
357
358#define AMDGPU_MAX_PPLL 3
359
360struct amdgpu_clock {
361 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
362 struct amdgpu_pll spll;
363 struct amdgpu_pll mpll;
364 /* 10 Khz units */
365 uint32_t default_mclk;
366 uint32_t default_sclk;
367 uint32_t default_dispclk;
368 uint32_t current_dispclk;
369 uint32_t dp_extclk;
370 uint32_t max_pixel_clock;
371};
372
373/*
374 * Fences.
375 */
376struct amdgpu_fence_driver {
377 struct amdgpu_ring *ring;
378 uint64_t gpu_addr;
379 volatile uint32_t *cpu_addr;
380 /* sync_seq is protected by ring emission lock */
381 uint64_t sync_seq[AMDGPU_MAX_RINGS];
382 atomic64_t last_seq;
383 bool initialized;
384 bool delayed_irq;
385 struct amdgpu_irq_src *irq_src;
386 unsigned irq_type;
387 struct delayed_work lockup_work;
388};
389
390/* some special values for the owner field */
391#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
392#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
393#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
394
890ee23f
CZ		 395#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
396#define AMDGPU_FENCE_FLAG_INT (1 << 1)
397
97b2e202
AD		 398struct amdgpu_fence {
399 struct fence base;
400
401 /* RB, DMA, etc. */
402 struct amdgpu_ring *ring;
403 uint64_t seq;
404
405 /* filp or special value for fence creator */
406 void *owner;
407
408 wait_queue_t fence_wake;
409};
410
411struct amdgpu_user_fence {
412 /* write-back bo */
413 struct amdgpu_bo *bo;
414 /* write-back address offset to bo start */
415 uint32_t offset;
416};
417
418int amdgpu_fence_driver_init(struct amdgpu_device *adev);
419void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
420void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
421
422void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
423int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
424 struct amdgpu_irq_src *irq_src,
425 unsigned irq_type);
426int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
427 struct amdgpu_fence **fence);
428void amdgpu_fence_process(struct amdgpu_ring *ring);
429int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
430int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
431unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
432
433bool amdgpu_fence_signaled(struct amdgpu_fence *fence);
434int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible);
435int amdgpu_fence_wait_any(struct amdgpu_device *adev,
436 struct amdgpu_fence **fences,
437 bool intr);
438long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev,
439 u64 *target_seq, bool intr,
440 long timeout);
441struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
442void amdgpu_fence_unref(struct amdgpu_fence **fence);
443
444bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
445 struct amdgpu_ring *ring);
446void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
447 struct amdgpu_ring *ring);
448
449static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
450 struct amdgpu_fence *b)
451{
452 if (!a) {
453 return b;
454 }
455
456 if (!b) {
457 return a;
458 }
459
460 BUG_ON(a->ring != b->ring);
461
462 if (a->seq > b->seq) {
463 return a;
464 } else {
465 return b;
466 }
467}
468
469static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
470 struct amdgpu_fence *b)
471{
472 if (!a) {
473 return false;
474 }
475
476 if (!b) {
477 return true;
478 }
479
480 BUG_ON(a->ring != b->ring);
481
482 return a->seq < b->seq;
483}
484
485int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
486 void *owner, struct amdgpu_fence **fence);
487
488/*
489 * TTM.
490 */
491struct amdgpu_mman {
492 struct ttm_bo_global_ref bo_global_ref;
493 struct drm_global_reference mem_global_ref;
494 struct ttm_bo_device bdev;
495 bool mem_global_referenced;
496 bool initialized;
497
498#if defined(CONFIG_DEBUG_FS)
499 struct dentry *vram;
500 struct dentry *gtt;
501#endif
502
503 /* buffer handling */
504 const struct amdgpu_buffer_funcs *buffer_funcs;
505 struct amdgpu_ring *buffer_funcs_ring;
506};
507
508int amdgpu_copy_buffer(struct amdgpu_ring *ring,
509 uint64_t src_offset,
510 uint64_t dst_offset,
511 uint32_t byte_count,
512 struct reservation_object *resv,
513 struct amdgpu_fence **fence);
514int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
515
516struct amdgpu_bo_list_entry {
517 struct amdgpu_bo *robj;
518 struct ttm_validate_buffer tv;
519 struct amdgpu_bo_va *bo_va;
520 unsigned prefered_domains;
521 unsigned allowed_domains;
522 uint32_t priority;
523};
524
525struct amdgpu_bo_va_mapping {
526 struct list_head list;
527 struct interval_tree_node it;
528 uint64_t offset;
529 uint32_t flags;
530};
531
532/* bo virtual addresses in a specific vm */
533struct amdgpu_bo_va {
534 /* protected by bo being reserved */
535 struct list_head bo_list;
536 uint64_t addr;
537 struct amdgpu_fence *last_pt_update;
538 unsigned ref_count;
539
540 /* protected by vm mutex */
541 struct list_head mappings;
542 struct list_head vm_status;
543
544 /* constant after initialization */
545 struct amdgpu_vm *vm;
546 struct amdgpu_bo *bo;
547};
548
7e5a547f
CZ		 549#define AMDGPU_GEM_DOMAIN_MAX 0x3
550
97b2e202
AD		 551struct amdgpu_bo {
552 /* Protected by gem.mutex */
553 struct list_head list;
554 /* Protected by tbo.reserved */
555 u32 initial_domain;
7e5a547f 556 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 557 struct ttm_placement placement;
558 struct ttm_buffer_object tbo;
559 struct ttm_bo_kmap_obj kmap;
560 u64 flags;
561 unsigned pin_count;
562 void *kptr;
563 u64 tiling_flags;
564 u64 metadata_flags;
565 void *metadata;
566 u32 metadata_size;
567 /* list of all virtual address to which this bo
568 * is associated to
569 */
570 struct list_head va;
571 /* Constant after initialization */
572 struct amdgpu_device *adev;
573 struct drm_gem_object gem_base;
574
575 struct ttm_bo_kmap_obj dma_buf_vmap;
576 pid_t pid;
577 struct amdgpu_mn *mn;
578 struct list_head mn_list;
579};
580#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
581
582void amdgpu_gem_object_free(struct drm_gem_object *obj);
583int amdgpu_gem_object_open(struct drm_gem_object *obj,
584 struct drm_file *file_priv);
585void amdgpu_gem_object_close(struct drm_gem_object *obj,
586 struct drm_file *file_priv);
587unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
588struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
589struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
590 struct dma_buf_attachment *attach,
591 struct sg_table *sg);
592struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
593 struct drm_gem_object *gobj,
594 int flags);
595int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
596void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
597struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
598void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
599void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
600int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
601
602/* sub-allocation manager, it has to be protected by another lock.
603 * By conception this is an helper for other part of the driver
604 * like the indirect buffer or semaphore, which both have their
605 * locking.
606 *
607 * Principe is simple, we keep a list of sub allocation in offset
608 * order (first entry has offset == 0, last entry has the highest
609 * offset).
610 *
611 * When allocating new object we first check if there is room at
612 * the end total_size - (last_object_offset + last_object_size) >=
613 * alloc_size. If so we allocate new object there.
614 *
615 * When there is not enough room at the end, we start waiting for
616 * each sub object until we reach object_offset+object_size >=
617 * alloc_size, this object then become the sub object we return.
618 *
619 * Alignment can't be bigger than page size.
620 *
621 * Hole are not considered for allocation to keep things simple.
622 * Assumption is that there won't be hole (all object on same
623 * alignment).
624 */
625struct amdgpu_sa_manager {
626 wait_queue_head_t wq;
627 struct amdgpu_bo *bo;
628 struct list_head *hole;
629 struct list_head flist[AMDGPU_MAX_RINGS];
630 struct list_head olist;
631 unsigned size;
632 uint64_t gpu_addr;
633 void *cpu_ptr;
634 uint32_t domain;
635 uint32_t align;
636};
637
638struct amdgpu_sa_bo;
639
640/* sub-allocation buffer */
641struct amdgpu_sa_bo {
642 struct list_head olist;
643 struct list_head flist;
644 struct amdgpu_sa_manager *manager;
645 unsigned soffset;
646 unsigned eoffset;
647 struct amdgpu_fence *fence;
648};
649
650/*
651 * GEM objects.
652 */
653struct amdgpu_gem {
654 struct mutex mutex;
655 struct list_head objects;
656};
657
658int amdgpu_gem_init(struct amdgpu_device *adev);
659void amdgpu_gem_fini(struct amdgpu_device *adev);
660int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
661 int alignment, u32 initial_domain,
662 u64 flags, bool kernel,
663 struct drm_gem_object **obj);
664
665int amdgpu_mode_dumb_create(struct drm_file *file_priv,
666 struct drm_device *dev,
667 struct drm_mode_create_dumb *args);
668int amdgpu_mode_dumb_mmap(struct drm_file *filp,
669 struct drm_device *dev,
670 uint32_t handle, uint64_t *offset_p);
671
672/*
673 * Semaphores.
674 */
675struct amdgpu_semaphore {
676 struct amdgpu_sa_bo *sa_bo;
677 signed waiters;
678 uint64_t gpu_addr;
679};
680
681int amdgpu_semaphore_create(struct amdgpu_device *adev,
682 struct amdgpu_semaphore **semaphore);
683bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
684 struct amdgpu_semaphore *semaphore);
685bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
686 struct amdgpu_semaphore *semaphore);
687void amdgpu_semaphore_free(struct amdgpu_device *adev,
688 struct amdgpu_semaphore **semaphore,
689 struct amdgpu_fence *fence);
690
691/*
692 * Synchronization
693 */
694struct amdgpu_sync {
695 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
696 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
697 struct amdgpu_fence *last_vm_update;
698};
699
700void amdgpu_sync_create(struct amdgpu_sync *sync);
701void amdgpu_sync_fence(struct amdgpu_sync *sync,
702 struct amdgpu_fence *fence);
703int amdgpu_sync_resv(struct amdgpu_device *adev,
704 struct amdgpu_sync *sync,
705 struct reservation_object *resv,
706 void *owner);
707int amdgpu_sync_rings(struct amdgpu_sync *sync,
708 struct amdgpu_ring *ring);
709void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
710 struct amdgpu_fence *fence);
711
712/*
713 * GART structures, functions & helpers
714 */
715struct amdgpu_mc;
716
717#define AMDGPU_GPU_PAGE_SIZE 4096
718#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
719#define AMDGPU_GPU_PAGE_SHIFT 12
720#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
721
722struct amdgpu_gart {
723 dma_addr_t table_addr;
724 struct amdgpu_bo *robj;
725 void *ptr;
726 unsigned num_gpu_pages;
727 unsigned num_cpu_pages;
728 unsigned table_size;
729 struct page **pages;
730 dma_addr_t *pages_addr;
731 bool ready;
732 const struct amdgpu_gart_funcs *gart_funcs;
733};
734
735int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
736void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
737int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
738void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
739int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
740void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
741int amdgpu_gart_init(struct amdgpu_device *adev);
742void amdgpu_gart_fini(struct amdgpu_device *adev);
743void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
744 int pages);
745int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
746 int pages, struct page **pagelist,
747 dma_addr_t *dma_addr, uint32_t flags);
748
749/*
750 * GPU MC structures, functions & helpers
751 */
752struct amdgpu_mc {
753 resource_size_t aper_size;
754 resource_size_t aper_base;
755 resource_size_t agp_base;
756 /* for some chips with <= 32MB we need to lie
757 * about vram size near mc fb location */
758 u64 mc_vram_size;
759 u64 visible_vram_size;
760 u64 gtt_size;
761 u64 gtt_start;
762 u64 gtt_end;
763 u64 vram_start;
764 u64 vram_end;
765 unsigned vram_width;
766 u64 real_vram_size;
767 int vram_mtrr;
768 u64 gtt_base_align;
769 u64 mc_mask;
770 const struct firmware *fw; /* MC firmware */
771 uint32_t fw_version;
772 struct amdgpu_irq_src vm_fault;
81c59f54 773 uint32_t vram_type;
97b2e202
AD		 774};
775
776/*
777 * GPU doorbell structures, functions & helpers
778 */
779typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
780{
781 AMDGPU_DOORBELL_KIQ = 0x000,
782 AMDGPU_DOORBELL_HIQ = 0x001,
783 AMDGPU_DOORBELL_DIQ = 0x002,
784 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
785 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
786 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
787 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
788 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
789 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
790 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
791 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
792 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
793 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
794 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
795 AMDGPU_DOORBELL_IH = 0x1E8,
796 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
797 AMDGPU_DOORBELL_INVALID = 0xFFFF
798} AMDGPU_DOORBELL_ASSIGNMENT;
799
800struct amdgpu_doorbell {
801 /* doorbell mmio */
802 resource_size_t base;
803 resource_size_t size;
804 u32 __iomem *ptr;
805 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
806};
807
808void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
809 phys_addr_t *aperture_base,
810 size_t *aperture_size,
811 size_t *start_offset);
812
813/*
814 * IRQS.
815 */
816
817struct amdgpu_flip_work {
818 struct work_struct flip_work;
819 struct work_struct unpin_work;
820 struct amdgpu_device *adev;
821 int crtc_id;
822 uint64_t base;
823 struct drm_pending_vblank_event *event;
824 struct amdgpu_bo *old_rbo;
825 struct fence *fence;
826};
827
828
829/*
830 * CP & rings.
831 */
832
833struct amdgpu_ib {
834 struct amdgpu_sa_bo *sa_bo;
835 uint32_t length_dw;
836 uint64_t gpu_addr;
837 uint32_t *ptr;
838 struct amdgpu_ring *ring;
839 struct amdgpu_fence *fence;
840 struct amdgpu_user_fence *user;
841 struct amdgpu_vm *vm;
3cb485f3 842 struct amdgpu_ctx *ctx;
97b2e202 843 struct amdgpu_sync sync;
97b2e202
AD		 844 uint32_t gds_base, gds_size;
845 uint32_t gws_base, gws_size;
846 uint32_t oa_base, oa_size;
de807f81 847 uint32_t flags;
97b2e202
AD		 848};
849
850enum amdgpu_ring_type {
851 AMDGPU_RING_TYPE_GFX,
852 AMDGPU_RING_TYPE_COMPUTE,
853 AMDGPU_RING_TYPE_SDMA,
854 AMDGPU_RING_TYPE_UVD,
855 AMDGPU_RING_TYPE_VCE
856};
857
858struct amdgpu_ring {
859 struct amdgpu_device *adev;
860 const struct amdgpu_ring_funcs *funcs;
861 struct amdgpu_fence_driver fence_drv;
862
863 struct mutex *ring_lock;
864 struct amdgpu_bo *ring_obj;
865 volatile uint32_t *ring;
866 unsigned rptr_offs;
867 u64 next_rptr_gpu_addr;
868 volatile u32 *next_rptr_cpu_addr;
869 unsigned wptr;
870 unsigned wptr_old;
871 unsigned ring_size;
872 unsigned ring_free_dw;
873 int count_dw;
874 atomic_t last_rptr;
875 atomic64_t last_activity;
876 uint64_t gpu_addr;
877 uint32_t align_mask;
878 uint32_t ptr_mask;
879 bool ready;
880 u32 nop;
881 u32 idx;
882 u64 last_semaphore_signal_addr;
883 u64 last_semaphore_wait_addr;
884 u32 me;
885 u32 pipe;
886 u32 queue;
887 struct amdgpu_bo *mqd_obj;
888 u32 doorbell_index;
889 bool use_doorbell;
890 unsigned wptr_offs;
891 unsigned next_rptr_offs;
892 unsigned fence_offs;
3cb485f3 893 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 894 enum amdgpu_ring_type type;
895 char name[16];
896};
897
898/*
899 * VM
900 */
901
902/* maximum number of VMIDs */
903#define AMDGPU_NUM_VM 16
904
905/* number of entries in page table */
906#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
907
908/* PTBs (Page Table Blocks) need to be aligned to 32K */
909#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
910#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
911#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
912
913#define AMDGPU_PTE_VALID (1 << 0)
914#define AMDGPU_PTE_SYSTEM (1 << 1)
915#define AMDGPU_PTE_SNOOPED (1 << 2)
916
917/* VI only */
918#define AMDGPU_PTE_EXECUTABLE (1 << 4)
919
920#define AMDGPU_PTE_READABLE (1 << 5)
921#define AMDGPU_PTE_WRITEABLE (1 << 6)
922
923/* PTE (Page Table Entry) fragment field for different page sizes */
924#define AMDGPU_PTE_FRAG_4KB (0 << 7)
925#define AMDGPU_PTE_FRAG_64KB (4 << 7)
926#define AMDGPU_LOG2_PAGES_PER_FRAG 4
927
928struct amdgpu_vm_pt {
929 struct amdgpu_bo *bo;
930 uint64_t addr;
931};
932
933struct amdgpu_vm_id {
934 unsigned id;
935 uint64_t pd_gpu_addr;
936 /* last flushed PD/PT update */
937 struct amdgpu_fence *flushed_updates;
938 /* last use of vmid */
939 struct amdgpu_fence *last_id_use;
940};
941
942struct amdgpu_vm {
943 struct mutex mutex;
944
945 struct rb_root va;
946
947 /* protecting invalidated and freed */
948 spinlock_t status_lock;
949
950 /* BOs moved, but not yet updated in the PT */
951 struct list_head invalidated;
952
953 /* BOs freed, but not yet updated in the PT */
954 struct list_head freed;
955
956 /* contains the page directory */
957 struct amdgpu_bo *page_directory;
958 unsigned max_pde_used;
959
960 /* array of page tables, one for each page directory entry */
961 struct amdgpu_vm_pt *page_tables;
962
963 /* for id and flush management per ring */
964 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
965};
966
967struct amdgpu_vm_manager {
968 struct amdgpu_fence *active[AMDGPU_NUM_VM];
969 uint32_t max_pfn;
970 /* number of VMIDs */
971 unsigned nvm;
972 /* vram base address for page table entry */
973 u64 vram_base_offset;
974 /* is vm enabled? */
975 bool enabled;
976 /* for hw to save the PD addr on suspend/resume */
977 uint32_t saved_table_addr[AMDGPU_NUM_VM];
978 /* vm pte handling */
979 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
980 struct amdgpu_ring *vm_pte_funcs_ring;
981};
982
983/*
984 * context related structures
985 */
986
987struct amdgpu_ctx_state {
988 uint64_t flags;
d94aed5a 989 uint32_t hangs;
97b2e202
AD		 990};
991
992struct amdgpu_ctx {
993 /* call kref_get()before CS start and kref_put() after CS fence signaled */
994 struct kref refcount;
995 struct amdgpu_fpriv *fpriv;
996 struct amdgpu_ctx_state state;
997 uint32_t id;
d94aed5a 998 unsigned reset_counter;
97b2e202
AD		 999};
1000
1001struct amdgpu_ctx_mgr {
1002 struct amdgpu_device *adev;
1003 struct idr ctx_handles;
1004 /* lock for IDR system */
0147ee0f 1005 struct mutex lock;
97b2e202
AD		 1006};
1007
1008/*
1009 * file private structure
1010 */
1011
1012struct amdgpu_fpriv {
1013 struct amdgpu_vm vm;
1014 struct mutex bo_list_lock;
1015 struct idr bo_list_handles;
1016 struct amdgpu_ctx_mgr ctx_mgr;
1017};
1018
1019/*
1020 * residency list
1021 */
1022
1023struct amdgpu_bo_list {
1024 struct mutex lock;
1025 struct amdgpu_bo *gds_obj;
1026 struct amdgpu_bo *gws_obj;
1027 struct amdgpu_bo *oa_obj;
1028 bool has_userptr;
1029 unsigned num_entries;
1030 struct amdgpu_bo_list_entry *array;
1031};
1032
1033struct amdgpu_bo_list *
1034amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1035void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1036void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1037
1038/*
1039 * GFX stuff
1040 */
1041#include "clearstate_defs.h"
1042
1043struct amdgpu_rlc {
1044 /* for power gating */
1045 struct amdgpu_bo *save_restore_obj;
1046 uint64_t save_restore_gpu_addr;
1047 volatile uint32_t *sr_ptr;
1048 const u32 *reg_list;
1049 u32 reg_list_size;
1050 /* for clear state */
1051 struct amdgpu_bo *clear_state_obj;
1052 uint64_t clear_state_gpu_addr;
1053 volatile uint32_t *cs_ptr;
1054 const struct cs_section_def *cs_data;
1055 u32 clear_state_size;
1056 /* for cp tables */
1057 struct amdgpu_bo *cp_table_obj;
1058 uint64_t cp_table_gpu_addr;
1059 volatile uint32_t *cp_table_ptr;
1060 u32 cp_table_size;
1061};
1062
1063struct amdgpu_mec {
1064 struct amdgpu_bo *hpd_eop_obj;
1065 u64 hpd_eop_gpu_addr;
1066 u32 num_pipe;
1067 u32 num_mec;
1068 u32 num_queue;
1069};
1070
1071/*
1072 * GPU scratch registers structures, functions & helpers
1073 */
1074struct amdgpu_scratch {
1075 unsigned num_reg;
1076 uint32_t reg_base;
1077 bool free[32];
1078 uint32_t reg[32];
1079};
1080
1081/*
1082 * GFX configurations
1083 */
1084struct amdgpu_gca_config {
1085 unsigned max_shader_engines;
1086 unsigned max_tile_pipes;
1087 unsigned max_cu_per_sh;
1088 unsigned max_sh_per_se;
1089 unsigned max_backends_per_se;
1090 unsigned max_texture_channel_caches;
1091 unsigned max_gprs;
1092 unsigned max_gs_threads;
1093 unsigned max_hw_contexts;
1094 unsigned sc_prim_fifo_size_frontend;
1095 unsigned sc_prim_fifo_size_backend;
1096 unsigned sc_hiz_tile_fifo_size;
1097 unsigned sc_earlyz_tile_fifo_size;
1098
1099 unsigned num_tile_pipes;
1100 unsigned backend_enable_mask;
1101 unsigned mem_max_burst_length_bytes;
1102 unsigned mem_row_size_in_kb;
1103 unsigned shader_engine_tile_size;
1104 unsigned num_gpus;
1105 unsigned multi_gpu_tile_size;
1106 unsigned mc_arb_ramcfg;
1107 unsigned gb_addr_config;
1108
1109 uint32_t tile_mode_array[32];
1110 uint32_t macrotile_mode_array[16];
1111};
1112
1113struct amdgpu_gfx {
1114 struct mutex gpu_clock_mutex;
1115 struct amdgpu_gca_config config;
1116 struct amdgpu_rlc rlc;
1117 struct amdgpu_mec mec;
1118 struct amdgpu_scratch scratch;
1119 const struct firmware *me_fw; /* ME firmware */
1120 uint32_t me_fw_version;
1121 const struct firmware *pfp_fw; /* PFP firmware */
1122 uint32_t pfp_fw_version;
1123 const struct firmware *ce_fw; /* CE firmware */
1124 uint32_t ce_fw_version;
1125 const struct firmware *rlc_fw; /* RLC firmware */
1126 uint32_t rlc_fw_version;
1127 const struct firmware *mec_fw; /* MEC firmware */
1128 uint32_t mec_fw_version;
1129 const struct firmware *mec2_fw; /* MEC2 firmware */
1130 uint32_t mec2_fw_version;
02558a00
KW		 1131 uint32_t me_feature_version;
1132 uint32_t ce_feature_version;
1133 uint32_t pfp_feature_version;
97b2e202
AD		 1134 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1135 unsigned num_gfx_rings;
1136 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1137 unsigned num_compute_rings;
1138 struct amdgpu_irq_src eop_irq;
1139 struct amdgpu_irq_src priv_reg_irq;
1140 struct amdgpu_irq_src priv_inst_irq;
1141 /* gfx status */
1142 uint32_t gfx_current_status;
1143 /* sync signal for const engine */
1144 unsigned ce_sync_offs;
a101a899
KW		 1145 /* ce ram size*/
1146 unsigned ce_ram_size;
97b2e202
AD		 1147};
1148
1149int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1150 unsigned size, struct amdgpu_ib *ib);
1151void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1152int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1153 struct amdgpu_ib *ib, void *owner);
1154int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1155void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1156int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1157/* Ring access between begin & end cannot sleep */
1158void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1159int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1160int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1161void amdgpu_ring_commit(struct amdgpu_ring *ring);
1162void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1163void amdgpu_ring_undo(struct amdgpu_ring *ring);
1164void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1165void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1166bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1167unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1168 uint32_t **data);
1169int amdgpu_ring_restore(struct amdgpu_ring *ring,
1170 unsigned size, uint32_t *data);
1171int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1172 unsigned ring_size, u32 nop, u32 align_mask,
1173 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1174 enum amdgpu_ring_type ring_type);
1175void amdgpu_ring_fini(struct amdgpu_ring *ring);
1176
1177/*
1178 * CS.
1179 */
1180struct amdgpu_cs_chunk {
1181 uint32_t chunk_id;
1182 uint32_t length_dw;
1183 uint32_t *kdata;
1184 void __user *user_ptr;
1185};
1186
1187struct amdgpu_cs_parser {
1188 struct amdgpu_device *adev;
1189 struct drm_file *filp;
3cb485f3 1190 struct amdgpu_ctx *ctx;
97b2e202
AD		 1191 struct amdgpu_bo_list *bo_list;
1192 /* chunks */
1193 unsigned nchunks;
1194 struct amdgpu_cs_chunk *chunks;
1195 /* relocations */
1196 struct amdgpu_bo_list_entry *vm_bos;
97b2e202
AD		 1197 struct list_head validated;
1198
1199 struct amdgpu_ib *ibs;
1200 uint32_t num_ibs;
1201
1202 struct ww_acquire_ctx ticket;
1203
1204 /* user fence */
1205 struct amdgpu_user_fence uf;
1206};
1207
1208static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1209{
1210 return p->ibs[ib_idx].ptr[idx];
1211}
1212
1213/*
1214 * Writeback
1215 */
1216#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1217
1218struct amdgpu_wb {
1219 struct amdgpu_bo *wb_obj;
1220 volatile uint32_t *wb;
1221 uint64_t gpu_addr;
1222 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1223 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1224};
1225
1226int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1227void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1228
1229/**
1230 * struct amdgpu_pm - power management datas
1231 * It keeps track of various data needed to take powermanagement decision.
1232 */
1233
1234enum amdgpu_pm_state_type {
1235 /* not used for dpm */
1236 POWER_STATE_TYPE_DEFAULT,
1237 POWER_STATE_TYPE_POWERSAVE,
1238 /* user selectable states */
1239 POWER_STATE_TYPE_BATTERY,
1240 POWER_STATE_TYPE_BALANCED,
1241 POWER_STATE_TYPE_PERFORMANCE,
1242 /* internal states */
1243 POWER_STATE_TYPE_INTERNAL_UVD,
1244 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1245 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1246 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1247 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1248 POWER_STATE_TYPE_INTERNAL_BOOT,
1249 POWER_STATE_TYPE_INTERNAL_THERMAL,
1250 POWER_STATE_TYPE_INTERNAL_ACPI,
1251 POWER_STATE_TYPE_INTERNAL_ULV,
1252 POWER_STATE_TYPE_INTERNAL_3DPERF,
1253};
1254
1255enum amdgpu_int_thermal_type {
1256 THERMAL_TYPE_NONE,
1257 THERMAL_TYPE_EXTERNAL,
1258 THERMAL_TYPE_EXTERNAL_GPIO,
1259 THERMAL_TYPE_RV6XX,
1260 THERMAL_TYPE_RV770,
1261 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1262 THERMAL_TYPE_EVERGREEN,
1263 THERMAL_TYPE_SUMO,
1264 THERMAL_TYPE_NI,
1265 THERMAL_TYPE_SI,
1266 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1267 THERMAL_TYPE_CI,
1268 THERMAL_TYPE_KV,
1269};
1270
1271enum amdgpu_dpm_auto_throttle_src {
1272 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1273 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1274};
1275
1276enum amdgpu_dpm_event_src {
1277 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1278 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1279 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1280 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1281 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1282};
1283
1284#define AMDGPU_MAX_VCE_LEVELS 6
1285
1286enum amdgpu_vce_level {
1287 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1288 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1289 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1290 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1291 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1292 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1293};
1294
1295struct amdgpu_ps {
1296 u32 caps; /* vbios flags */
1297 u32 class; /* vbios flags */
1298 u32 class2; /* vbios flags */
1299 /* UVD clocks */
1300 u32 vclk;
1301 u32 dclk;
1302 /* VCE clocks */
1303 u32 evclk;
1304 u32 ecclk;
1305 bool vce_active;
1306 enum amdgpu_vce_level vce_level;
1307 /* asic priv */
1308 void *ps_priv;
1309};
1310
1311struct amdgpu_dpm_thermal {
1312 /* thermal interrupt work */
1313 struct work_struct work;
1314 /* low temperature threshold */
1315 int min_temp;
1316 /* high temperature threshold */
1317 int max_temp;
1318 /* was last interrupt low to high or high to low */
1319 bool high_to_low;
1320 /* interrupt source */
1321 struct amdgpu_irq_src irq;
1322};
1323
1324enum amdgpu_clk_action
1325{
1326 AMDGPU_SCLK_UP = 1,
1327 AMDGPU_SCLK_DOWN
1328};
1329
1330struct amdgpu_blacklist_clocks
1331{
1332 u32 sclk;
1333 u32 mclk;
1334 enum amdgpu_clk_action action;
1335};
1336
1337struct amdgpu_clock_and_voltage_limits {
1338 u32 sclk;
1339 u32 mclk;
1340 u16 vddc;
1341 u16 vddci;
1342};
1343
1344struct amdgpu_clock_array {
1345 u32 count;
1346 u32 *values;
1347};
1348
1349struct amdgpu_clock_voltage_dependency_entry {
1350 u32 clk;
1351 u16 v;
1352};
1353
1354struct amdgpu_clock_voltage_dependency_table {
1355 u32 count;
1356 struct amdgpu_clock_voltage_dependency_entry *entries;
1357};
1358
1359union amdgpu_cac_leakage_entry {
1360 struct {
1361 u16 vddc;
1362 u32 leakage;
1363 };
1364 struct {
1365 u16 vddc1;
1366 u16 vddc2;
1367 u16 vddc3;
1368 };
1369};
1370
1371struct amdgpu_cac_leakage_table {
1372 u32 count;
1373 union amdgpu_cac_leakage_entry *entries;
1374};
1375
1376struct amdgpu_phase_shedding_limits_entry {
1377 u16 voltage;
1378 u32 sclk;
1379 u32 mclk;
1380};
1381
1382struct amdgpu_phase_shedding_limits_table {
1383 u32 count;
1384 struct amdgpu_phase_shedding_limits_entry *entries;
1385};
1386
1387struct amdgpu_uvd_clock_voltage_dependency_entry {
1388 u32 vclk;
1389 u32 dclk;
1390 u16 v;
1391};
1392
1393struct amdgpu_uvd_clock_voltage_dependency_table {
1394 u8 count;
1395 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1396};
1397
1398struct amdgpu_vce_clock_voltage_dependency_entry {
1399 u32 ecclk;
1400 u32 evclk;
1401 u16 v;
1402};
1403
1404struct amdgpu_vce_clock_voltage_dependency_table {
1405 u8 count;
1406 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1407};
1408
1409struct amdgpu_ppm_table {
1410 u8 ppm_design;
1411 u16 cpu_core_number;
1412 u32 platform_tdp;
1413 u32 small_ac_platform_tdp;
1414 u32 platform_tdc;
1415 u32 small_ac_platform_tdc;
1416 u32 apu_tdp;
1417 u32 dgpu_tdp;
1418 u32 dgpu_ulv_power;
1419 u32 tj_max;
1420};
1421
1422struct amdgpu_cac_tdp_table {
1423 u16 tdp;
1424 u16 configurable_tdp;
1425 u16 tdc;
1426 u16 battery_power_limit;
1427 u16 small_power_limit;
1428 u16 low_cac_leakage;
1429 u16 high_cac_leakage;
1430 u16 maximum_power_delivery_limit;
1431};
1432
1433struct amdgpu_dpm_dynamic_state {
1434 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1435 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1436 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1437 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1438 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1439 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1440 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1441 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1442 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1443 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1444 struct amdgpu_clock_array valid_sclk_values;
1445 struct amdgpu_clock_array valid_mclk_values;
1446 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1447 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1448 u32 mclk_sclk_ratio;
1449 u32 sclk_mclk_delta;
1450 u16 vddc_vddci_delta;
1451 u16 min_vddc_for_pcie_gen2;
1452 struct amdgpu_cac_leakage_table cac_leakage_table;
1453 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1454 struct amdgpu_ppm_table *ppm_table;
1455 struct amdgpu_cac_tdp_table *cac_tdp_table;
1456};
1457
1458struct amdgpu_dpm_fan {
1459 u16 t_min;
1460 u16 t_med;
1461 u16 t_high;
1462 u16 pwm_min;
1463 u16 pwm_med;
1464 u16 pwm_high;
1465 u8 t_hyst;
1466 u32 cycle_delay;
1467 u16 t_max;
1468 u8 control_mode;
1469 u16 default_max_fan_pwm;
1470 u16 default_fan_output_sensitivity;
1471 u16 fan_output_sensitivity;
1472 bool ucode_fan_control;
1473};
1474
1475enum amdgpu_pcie_gen {
1476 AMDGPU_PCIE_GEN1 = 0,
1477 AMDGPU_PCIE_GEN2 = 1,
1478 AMDGPU_PCIE_GEN3 = 2,
1479 AMDGPU_PCIE_GEN_INVALID = 0xffff
1480};
1481
1482enum amdgpu_dpm_forced_level {
1483 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1484 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1485 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1486};
1487
1488struct amdgpu_vce_state {
1489 /* vce clocks */
1490 u32 evclk;
1491 u32 ecclk;
1492 /* gpu clocks */
1493 u32 sclk;
1494 u32 mclk;
1495 u8 clk_idx;
1496 u8 pstate;
1497};
1498
1499struct amdgpu_dpm_funcs {
1500 int (*get_temperature)(struct amdgpu_device *adev);
1501 int (*pre_set_power_state)(struct amdgpu_device *adev);
1502 int (*set_power_state)(struct amdgpu_device *adev);
1503 void (*post_set_power_state)(struct amdgpu_device *adev);
1504 void (*display_configuration_changed)(struct amdgpu_device *adev);
1505 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1506 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1507 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1508 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1509 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1510 bool (*vblank_too_short)(struct amdgpu_device *adev);
1511 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1512 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1513 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1514 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1515 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1516 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1517 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1518};
1519
1520struct amdgpu_dpm {
1521 struct amdgpu_ps *ps;
1522 /* number of valid power states */
1523 int num_ps;
1524 /* current power state that is active */
1525 struct amdgpu_ps *current_ps;
1526 /* requested power state */
1527 struct amdgpu_ps *requested_ps;
1528 /* boot up power state */
1529 struct amdgpu_ps *boot_ps;
1530 /* default uvd power state */
1531 struct amdgpu_ps *uvd_ps;
1532 /* vce requirements */
1533 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1534 enum amdgpu_vce_level vce_level;
1535 enum amdgpu_pm_state_type state;
1536 enum amdgpu_pm_state_type user_state;
1537 u32 platform_caps;
1538 u32 voltage_response_time;
1539 u32 backbias_response_time;
1540 void *priv;
1541 u32 new_active_crtcs;
1542 int new_active_crtc_count;
1543 u32 current_active_crtcs;
1544 int current_active_crtc_count;
1545 struct amdgpu_dpm_dynamic_state dyn_state;
1546 struct amdgpu_dpm_fan fan;
1547 u32 tdp_limit;
1548 u32 near_tdp_limit;
1549 u32 near_tdp_limit_adjusted;
1550 u32 sq_ramping_threshold;
1551 u32 cac_leakage;
1552 u16 tdp_od_limit;
1553 u32 tdp_adjustment;
1554 u16 load_line_slope;
1555 bool power_control;
1556 bool ac_power;
1557 /* special states active */
1558 bool thermal_active;
1559 bool uvd_active;
1560 bool vce_active;
1561 /* thermal handling */
1562 struct amdgpu_dpm_thermal thermal;
1563 /* forced levels */
1564 enum amdgpu_dpm_forced_level forced_level;
1565};
1566
1567struct amdgpu_pm {
1568 struct mutex mutex;
97b2e202
AD		 1569 u32 current_sclk;
1570 u32 current_mclk;
1571 u32 default_sclk;
1572 u32 default_mclk;
1573 struct amdgpu_i2c_chan *i2c_bus;
1574 /* internal thermal controller on rv6xx+ */
1575 enum amdgpu_int_thermal_type int_thermal_type;
1576 struct device *int_hwmon_dev;
1577 /* fan control parameters */
1578 bool no_fan;
1579 u8 fan_pulses_per_revolution;
1580 u8 fan_min_rpm;
1581 u8 fan_max_rpm;
1582 /* dpm */
1583 bool dpm_enabled;
1584 struct amdgpu_dpm dpm;
1585 const struct firmware *fw; /* SMC firmware */
1586 uint32_t fw_version;
1587 const struct amdgpu_dpm_funcs *funcs;
1588};
1589
1590/*
1591 * UVD
1592 */
1593#define AMDGPU_MAX_UVD_HANDLES 10
1594#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1595#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1596#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1597
1598struct amdgpu_uvd {
1599 struct amdgpu_bo *vcpu_bo;
1600 void *cpu_addr;
1601 uint64_t gpu_addr;
1602 void *saved_bo;
1603 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1604 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1605 struct delayed_work idle_work;
1606 const struct firmware *fw; /* UVD firmware */
1607 struct amdgpu_ring ring;
1608 struct amdgpu_irq_src irq;
1609 bool address_64_bit;
1610};
1611
1612/*
1613 * VCE
1614 */
1615#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1616#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1617
1618struct amdgpu_vce {
1619 struct amdgpu_bo *vcpu_bo;
1620 uint64_t gpu_addr;
1621 unsigned fw_version;
1622 unsigned fb_version;
1623 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1624 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1625 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1626 struct delayed_work idle_work;
1627 const struct firmware *fw; /* VCE firmware */
1628 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1629 struct amdgpu_irq_src irq;
1630};
1631
1632/*
1633 * SDMA
1634 */
1635struct amdgpu_sdma {
1636 /* SDMA firmware */
1637 const struct firmware *fw;
1638 uint32_t fw_version;
1639
1640 struct amdgpu_ring ring;
1641};
1642
1643/*
1644 * Firmware
1645 */
1646struct amdgpu_firmware {
1647 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1648 bool smu_load;
1649 struct amdgpu_bo *fw_buf;
1650 unsigned int fw_size;
1651};
1652
1653/*
1654 * Benchmarking
1655 */
1656void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1657
1658
1659/*
1660 * Testing
1661 */
1662void amdgpu_test_moves(struct amdgpu_device *adev);
1663void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1664 struct amdgpu_ring *cpA,
1665 struct amdgpu_ring *cpB);
1666void amdgpu_test_syncing(struct amdgpu_device *adev);
1667
1668/*
1669 * MMU Notifier
1670 */
1671#if defined(CONFIG_MMU_NOTIFIER)
1672int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1673void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1674#else
1675static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1676{
1677 return -ENODEV;
1678}
1679static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1680#endif
1681
1682/*
1683 * Debugfs
1684 */
1685struct amdgpu_debugfs {
1686 struct drm_info_list *files;
1687 unsigned num_files;
1688};
1689
1690int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1691 struct drm_info_list *files,
1692 unsigned nfiles);
1693int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1694
1695#if defined(CONFIG_DEBUG_FS)
1696int amdgpu_debugfs_init(struct drm_minor *minor);
1697void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1698#endif
1699
1700/*
1701 * amdgpu smumgr functions
1702 */
1703struct amdgpu_smumgr_funcs {
1704 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1705 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1706 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1707};
1708
1709/*
1710 * amdgpu smumgr
1711 */
1712struct amdgpu_smumgr {
1713 struct amdgpu_bo *toc_buf;
1714 struct amdgpu_bo *smu_buf;
1715 /* asic priv smu data */
1716 void *priv;
1717 spinlock_t smu_lock;
1718 /* smumgr functions */
1719 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1720 /* ucode loading complete flag */
1721 uint32_t fw_flags;
1722};
1723
1724/*
1725 * ASIC specific register table accessible by UMD
1726 */
1727struct amdgpu_allowed_register_entry {
1728 uint32_t reg_offset;
1729 bool untouched;
1730 bool grbm_indexed;
1731};
1732
1733struct amdgpu_cu_info {
1734 uint32_t number; /* total active CU number */
1735 uint32_t ao_cu_mask;
1736 uint32_t bitmap[4][4];
1737};
1738
1739
1740/*
1741 * ASIC specific functions.
1742 */
1743struct amdgpu_asic_funcs {
1744 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1745 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1746 u32 sh_num, u32 reg_offset, u32 *value);
1747 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1748 int (*reset)(struct amdgpu_device *adev);
1749 /* wait for mc_idle */
1750 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1751 /* get the reference clock */
1752 u32 (*get_xclk)(struct amdgpu_device *adev);
1753 /* get the gpu clock counter */
1754 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1755 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1756 /* MM block clocks */
1757 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1758 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1759};
1760
1761/*
1762 * IOCTL.
1763 */
1764int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1765 struct drm_file *filp);
1766int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1767 struct drm_file *filp);
1768
1769int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1770 struct drm_file *filp);
1771int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1772 struct drm_file *filp);
1773int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1774 struct drm_file *filp);
1775int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1776 struct drm_file *filp);
1777int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1778 struct drm_file *filp);
1779int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1780 struct drm_file *filp);
1781int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1782int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1783
1784int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1785 struct drm_file *filp);
1786
1787/* VRAM scratch page for HDP bug, default vram page */
1788struct amdgpu_vram_scratch {
1789 struct amdgpu_bo *robj;
1790 volatile uint32_t *ptr;
1791 u64 gpu_addr;
1792};
1793
1794/*
1795 * ACPI
1796 */
1797struct amdgpu_atif_notification_cfg {
1798 bool enabled;
1799 int command_code;
1800};
1801
1802struct amdgpu_atif_notifications {
1803 bool display_switch;
1804 bool expansion_mode_change;
1805 bool thermal_state;
1806 bool forced_power_state;
1807 bool system_power_state;
1808 bool display_conf_change;
1809 bool px_gfx_switch;
1810 bool brightness_change;
1811 bool dgpu_display_event;
1812};
1813
1814struct amdgpu_atif_functions {
1815 bool system_params;
1816 bool sbios_requests;
1817 bool select_active_disp;
1818 bool lid_state;
1819 bool get_tv_standard;
1820 bool set_tv_standard;
1821 bool get_panel_expansion_mode;
1822 bool set_panel_expansion_mode;
1823 bool temperature_change;
1824 bool graphics_device_types;
1825};
1826
1827struct amdgpu_atif {
1828 struct amdgpu_atif_notifications notifications;
1829 struct amdgpu_atif_functions functions;
1830 struct amdgpu_atif_notification_cfg notification_cfg;
1831 struct amdgpu_encoder *encoder_for_bl;
1832};
1833
1834struct amdgpu_atcs_functions {
1835 bool get_ext_state;
1836 bool pcie_perf_req;
1837 bool pcie_dev_rdy;
1838 bool pcie_bus_width;
1839};
1840
1841struct amdgpu_atcs {
1842 struct amdgpu_atcs_functions functions;
1843};
1844
1845int amdgpu_ctx_alloc(struct amdgpu_device *adev,struct amdgpu_fpriv *fpriv,
1846 uint32_t *id,uint32_t flags);
1847int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1848 uint32_t id);
97b2e202
AD		 1849
1850void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
66b3cf2a
JZ		 1851struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1852int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
97b2e202
AD		 1853
1854extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1855 struct drm_file *filp);
1856
1857/*
1858 * Core structure, functions and helpers.
1859 */
1860typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1861typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1862
1863typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1864typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1865
1866struct amdgpu_device {
1867 struct device *dev;
1868 struct drm_device *ddev;
1869 struct pci_dev *pdev;
1870 struct rw_semaphore exclusive_lock;
1871
1872 /* ASIC */
1873 enum amdgpu_asic_type asic_type;
1874 uint32_t family;
1875 uint32_t rev_id;
1876 uint32_t external_rev_id;
1877 unsigned long flags;
1878 int usec_timeout;
1879 const struct amdgpu_asic_funcs *asic_funcs;
1880 bool shutdown;
1881 bool suspend;
1882 bool need_dma32;
1883 bool accel_working;
1884 bool needs_reset;
1885 struct work_struct reset_work;
1886 struct notifier_block acpi_nb;
1887 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1888 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1889 unsigned debugfs_count;
1890#if defined(CONFIG_DEBUG_FS)
1891 struct dentry *debugfs_regs;
1892#endif
1893 struct amdgpu_atif atif;
1894 struct amdgpu_atcs atcs;
1895 struct mutex srbm_mutex;
1896 /* GRBM index mutex. Protects concurrent access to GRBM index */
1897 struct mutex grbm_idx_mutex;
1898 struct dev_pm_domain vga_pm_domain;
1899 bool have_disp_power_ref;
1900
1901 /* BIOS */
1902 uint8_t *bios;
1903 bool is_atom_bios;
1904 uint16_t bios_header_start;
1905 struct amdgpu_bo *stollen_vga_memory;
1906 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1907
1908 /* Register/doorbell mmio */
1909 resource_size_t rmmio_base;
1910 resource_size_t rmmio_size;
1911 void __iomem *rmmio;
1912 /* protects concurrent MM_INDEX/DATA based register access */
1913 spinlock_t mmio_idx_lock;
1914 /* protects concurrent SMC based register access */
1915 spinlock_t smc_idx_lock;
1916 amdgpu_rreg_t smc_rreg;
1917 amdgpu_wreg_t smc_wreg;
1918 /* protects concurrent PCIE register access */
1919 spinlock_t pcie_idx_lock;
1920 amdgpu_rreg_t pcie_rreg;
1921 amdgpu_wreg_t pcie_wreg;
1922 /* protects concurrent UVD register access */
1923 spinlock_t uvd_ctx_idx_lock;
1924 amdgpu_rreg_t uvd_ctx_rreg;
1925 amdgpu_wreg_t uvd_ctx_wreg;
1926 /* protects concurrent DIDT register access */
1927 spinlock_t didt_idx_lock;
1928 amdgpu_rreg_t didt_rreg;
1929 amdgpu_wreg_t didt_wreg;
1930 /* protects concurrent ENDPOINT (audio) register access */
1931 spinlock_t audio_endpt_idx_lock;
1932 amdgpu_block_rreg_t audio_endpt_rreg;
1933 amdgpu_block_wreg_t audio_endpt_wreg;
1934 void __iomem *rio_mem;
1935 resource_size_t rio_mem_size;
1936 struct amdgpu_doorbell doorbell;
1937
1938 /* clock/pll info */
1939 struct amdgpu_clock clock;
1940
1941 /* MC */
1942 struct amdgpu_mc mc;
1943 struct amdgpu_gart gart;
1944 struct amdgpu_dummy_page dummy_page;
1945 struct amdgpu_vm_manager vm_manager;
1946
1947 /* memory management */
1948 struct amdgpu_mman mman;
1949 struct amdgpu_gem gem;
1950 struct amdgpu_vram_scratch vram_scratch;
1951 struct amdgpu_wb wb;
1952 atomic64_t vram_usage;
1953 atomic64_t vram_vis_usage;
1954 atomic64_t gtt_usage;
1955 atomic64_t num_bytes_moved;
d94aed5a 1956 atomic_t gpu_reset_counter;
97b2e202
AD		 1957
1958 /* display */
1959 struct amdgpu_mode_info mode_info;
1960 struct work_struct hotplug_work;
1961 struct amdgpu_irq_src crtc_irq;
1962 struct amdgpu_irq_src pageflip_irq;
1963 struct amdgpu_irq_src hpd_irq;
1964
1965 /* rings */
1966 wait_queue_head_t fence_queue;
1967 unsigned fence_context;
1968 struct mutex ring_lock;
1969 unsigned num_rings;
1970 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1971 bool ib_pool_ready;
1972 struct amdgpu_sa_manager ring_tmp_bo;
1973
1974 /* interrupts */
1975 struct amdgpu_irq irq;
1976
1977 /* dpm */
1978 struct amdgpu_pm pm;
1979 u32 cg_flags;
1980 u32 pg_flags;
1981
1982 /* amdgpu smumgr */
1983 struct amdgpu_smumgr smu;
1984
1985 /* gfx */
1986 struct amdgpu_gfx gfx;
1987
1988 /* sdma */
1989 struct amdgpu_sdma sdma[2];
1990 struct amdgpu_irq_src sdma_trap_irq;
1991 struct amdgpu_irq_src sdma_illegal_inst_irq;
1992
1993 /* uvd */
1994 bool has_uvd;
1995 struct amdgpu_uvd uvd;
1996
1997 /* vce */
1998 struct amdgpu_vce vce;
1999
2000 /* firmwares */
2001 struct amdgpu_firmware firmware;
2002
2003 /* GDS */
2004 struct amdgpu_gds gds;
2005
2006 const struct amdgpu_ip_block_version *ip_blocks;
2007 int num_ip_blocks;
2008 bool *ip_block_enabled;
2009 struct mutex mn_lock;
2010 DECLARE_HASHTABLE(mn_hash, 7);
2011
2012 /* tracking pinned memory */
2013 u64 vram_pin_size;
2014 u64 gart_pin_size;
2015};
2016
2017bool amdgpu_device_is_px(struct drm_device *dev);
2018int amdgpu_device_init(struct amdgpu_device *adev,
2019 struct drm_device *ddev,
2020 struct pci_dev *pdev,
2021 uint32_t flags);
2022void amdgpu_device_fini(struct amdgpu_device *adev);
2023int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2024
2025uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2026 bool always_indirect);
2027void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2028 bool always_indirect);
2029u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2030void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2031
2032u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2033void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2034
2035/*
2036 * Cast helper
2037 */
2038extern const struct fence_ops amdgpu_fence_ops;
2039static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2040{
2041 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2042
2043 if (__f->base.ops == &amdgpu_fence_ops)
2044 return __f;
2045
2046 return NULL;
2047}
2048
2049/*
2050 * Registers read & write functions.
2051 */
2052#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2053#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2054#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2055#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2056#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2057#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2058#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2059#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2060#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2061#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2062#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2063#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2064#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2065#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2066#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2067#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2068#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2069#define WREG32_P(reg, val, mask) \
2070 do { \
2071 uint32_t tmp_ = RREG32(reg); \
2072 tmp_ &= (mask); \
2073 tmp_ |= ((val) & ~(mask)); \
2074 WREG32(reg, tmp_); \
2075 } while (0)
2076#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2077#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2078#define WREG32_PLL_P(reg, val, mask) \
2079 do { \
2080 uint32_t tmp_ = RREG32_PLL(reg); \
2081 tmp_ &= (mask); \
2082 tmp_ |= ((val) & ~(mask)); \
2083 WREG32_PLL(reg, tmp_); \
2084 } while (0)
2085#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2086#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2087#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2088
2089#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2090#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2091
2092#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2093#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2094
2095#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2096 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2097 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2098
2099#define REG_GET_FIELD(value, reg, field) \
2100 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2101
2102/*
2103 * BIOS helpers.
2104 */
2105#define RBIOS8(i) (adev->bios[i])
2106#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2107#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2108
2109/*
2110 * RING helpers.
2111 */
2112static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2113{
2114 if (ring->count_dw <= 0)
86c2b790 2115 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2116 ring->ring[ring->wptr++] = v;
2117 ring->wptr &= ring->ptr_mask;
2118 ring->count_dw--;
2119 ring->ring_free_dw--;
2120}
2121
2122/*
2123 * ASICs macro.
2124 */
2125#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2126#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2127#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2128#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2129#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2130#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2131#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2132#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2133#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2134#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2135#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2136#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2137#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2138#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2139#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2140#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2141#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2142#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2143#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2144#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2145#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2146#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2147#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2148#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2149#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2150#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202
AD		 2151#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2152#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2153#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2154#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2155#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2156#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2157#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2158#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2159#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2160#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2161#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2162#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2163#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2164#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2165#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2166#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2167#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2168#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2169#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2170#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2171#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2172#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2173#define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2174#define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2175#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2176#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2177#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2178#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2179#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2180#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2181#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2182#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2183#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2184#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2185#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2186#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
b7a07769 2187#define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
97b2e202
AD		 2188#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2189#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2190#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2191#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2192#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2193
2194#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2195
2196/* Common functions */
2197int amdgpu_gpu_reset(struct amdgpu_device *adev);
2198void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2199bool amdgpu_card_posted(struct amdgpu_device *adev);
2200void amdgpu_update_display_priority(struct amdgpu_device *adev);
2201bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2202int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2203int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2204 u32 ip_instance, u32 ring,
2205 struct amdgpu_ring **out_ring);
2206void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2207bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2208int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2209 uint32_t flags);
2210bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2211bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2212uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2213 struct ttm_mem_reg *mem);
2214void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2215void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2216void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2217void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2218 const u32 *registers,
2219 const u32 array_size);
2220
2221bool amdgpu_device_is_px(struct drm_device *dev);
2222/* atpx handler */
2223#if defined(CONFIG_VGA_SWITCHEROO)
2224void amdgpu_register_atpx_handler(void);
2225void amdgpu_unregister_atpx_handler(void);
2226#else
2227static inline void amdgpu_register_atpx_handler(void) {}
2228static inline void amdgpu_unregister_atpx_handler(void) {}
2229#endif
2230
2231/*
2232 * KMS
2233 */
2234extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2235extern int amdgpu_max_kms_ioctl;
2236
2237int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2238int amdgpu_driver_unload_kms(struct drm_device *dev);
2239void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2240int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2241void amdgpu_driver_postclose_kms(struct drm_device *dev,
2242 struct drm_file *file_priv);
2243void amdgpu_driver_preclose_kms(struct drm_device *dev,
2244 struct drm_file *file_priv);
2245int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2246int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2247u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2248int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2249void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2250int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2251 int *max_error,
2252 struct timeval *vblank_time,
2253 unsigned flags);
2254long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2255 unsigned long arg);
2256
2257/*
2258 * vm
2259 */
2260int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2261void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2262struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2263 struct amdgpu_vm *vm,
2264 struct list_head *head);
2265struct amdgpu_fence *amdgpu_vm_grab_id(struct amdgpu_ring *ring,
2266 struct amdgpu_vm *vm);
2267void amdgpu_vm_flush(struct amdgpu_ring *ring,
2268 struct amdgpu_vm *vm,
2269 struct amdgpu_fence *updates);
2270void amdgpu_vm_fence(struct amdgpu_device *adev,
2271 struct amdgpu_vm *vm,
2272 struct amdgpu_fence *fence);
2273uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2274int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2275 struct amdgpu_vm *vm);
2276int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2277 struct amdgpu_vm *vm);
2278int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
cfe2c978 2279 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
97b2e202
AD		 2280int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2281 struct amdgpu_bo_va *bo_va,
2282 struct ttm_mem_reg *mem);
2283void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2284 struct amdgpu_bo *bo);
2285struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2286 struct amdgpu_bo *bo);
2287struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2288 struct amdgpu_vm *vm,
2289 struct amdgpu_bo *bo);
2290int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2291 struct amdgpu_bo_va *bo_va,
2292 uint64_t addr, uint64_t offset,
2293 uint64_t size, uint32_t flags);
2294int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2295 struct amdgpu_bo_va *bo_va,
2296 uint64_t addr);
2297void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2298 struct amdgpu_bo_va *bo_va);
2299
2300/*
2301 * functions used by amdgpu_encoder.c
2302 */
2303struct amdgpu_afmt_acr {
2304 u32 clock;
2305
2306 int n_32khz;
2307 int cts_32khz;
2308
2309 int n_44_1khz;
2310 int cts_44_1khz;
2311
2312 int n_48khz;
2313 int cts_48khz;
2314
2315};
2316
2317struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2318
2319/* amdgpu_acpi.c */
2320#if defined(CONFIG_ACPI)
2321int amdgpu_acpi_init(struct amdgpu_device *adev);
2322void amdgpu_acpi_fini(struct amdgpu_device *adev);
2323bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2324int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2325 u8 perf_req, bool advertise);
2326int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2327#else
2328static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2329static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2330#endif
2331
2332struct amdgpu_bo_va_mapping *
2333amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2334 uint64_t addr, struct amdgpu_bo **bo);
2335
2336#include "amdgpu_object.h"
2337
2338#endif
Linux 6.x block layer and io_uring tree(s)