projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: check context id for context switching (v2)
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
45#include <drm/drm_gem.h>
46
47#include "amdgpu_family.h"
48#include "amdgpu_mode.h"
49#include "amdgpu_ih.h"
50#include "amdgpu_irq.h"
51#include "amdgpu_ucode.h"
52#include "amdgpu_gds.h"
53
54/*
55 * Modules parameters.
56 */
57extern int amdgpu_modeset;
58extern int amdgpu_vram_limit;
59extern int amdgpu_gart_size;
60extern int amdgpu_benchmarking;
61extern int amdgpu_testing;
62extern int amdgpu_audio;
63extern int amdgpu_disp_priority;
64extern int amdgpu_hw_i2c;
65extern int amdgpu_pcie_gen2;
66extern int amdgpu_msi;
67extern int amdgpu_lockup_timeout;
68extern int amdgpu_dpm;
69extern int amdgpu_smc_load_fw;
70extern int amdgpu_aspm;
71extern int amdgpu_runtime_pm;
72extern int amdgpu_hard_reset;
73extern unsigned amdgpu_ip_block_mask;
74extern int amdgpu_bapm;
75extern int amdgpu_deep_color;
76extern int amdgpu_vm_size;
77extern int amdgpu_vm_block_size;
78
79#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
80#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
81/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
82#define AMDGPU_IB_POOL_SIZE 16
83#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
84#define AMDGPUFB_CONN_LIMIT 4
85#define AMDGPU_BIOS_NUM_SCRATCH 8
86
87/* fence seq are set to this number when signaled */
88#define AMDGPU_FENCE_SIGNALED_SEQ 0LL
89
90/* max number of rings */
91#define AMDGPU_MAX_RINGS 16
92#define AMDGPU_MAX_GFX_RINGS 1
93#define AMDGPU_MAX_COMPUTE_RINGS 8
94#define AMDGPU_MAX_VCE_RINGS 2
95
96/* number of hw syncs before falling back on blocking */
97#define AMDGPU_NUM_SYNCS 4
98
99/* hardcode that limit for now */
100#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
101
102/* hard reset data */
103#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
104
105/* reset flags */
106#define AMDGPU_RESET_GFX (1 << 0)
107#define AMDGPU_RESET_COMPUTE (1 << 1)
108#define AMDGPU_RESET_DMA (1 << 2)
109#define AMDGPU_RESET_CP (1 << 3)
110#define AMDGPU_RESET_GRBM (1 << 4)
111#define AMDGPU_RESET_DMA1 (1 << 5)
112#define AMDGPU_RESET_RLC (1 << 6)
113#define AMDGPU_RESET_SEM (1 << 7)
114#define AMDGPU_RESET_IH (1 << 8)
115#define AMDGPU_RESET_VMC (1 << 9)
116#define AMDGPU_RESET_MC (1 << 10)
117#define AMDGPU_RESET_DISPLAY (1 << 11)
118#define AMDGPU_RESET_UVD (1 << 12)
119#define AMDGPU_RESET_VCE (1 << 13)
120#define AMDGPU_RESET_VCE1 (1 << 14)
121
122/* CG block flags */
123#define AMDGPU_CG_BLOCK_GFX (1 << 0)
124#define AMDGPU_CG_BLOCK_MC (1 << 1)
125#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
126#define AMDGPU_CG_BLOCK_UVD (1 << 3)
127#define AMDGPU_CG_BLOCK_VCE (1 << 4)
128#define AMDGPU_CG_BLOCK_HDP (1 << 5)
129#define AMDGPU_CG_BLOCK_BIF (1 << 6)
130
131/* CG flags */
132#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
133#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
134#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
135#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
136#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
137#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
138#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
139#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
140#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
141#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
142#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
143#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
144#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
145#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
146#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
147#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
148#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
149
150/* PG flags */
151#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
152#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
153#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
154#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
155#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
156#define AMDGPU_PG_SUPPORT_CP (1 << 5)
157#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
158#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
159#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
160#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
161#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
162
163/* GFX current status */
164#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
165#define AMDGPU_GFX_SAFE_MODE 0x00000001L
166#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
167#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
168#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
169
170/* max cursor sizes (in pixels) */
171#define CIK_CURSOR_WIDTH 128
172#define CIK_CURSOR_HEIGHT 128
173
174struct amdgpu_device;
175struct amdgpu_fence;
176struct amdgpu_ib;
177struct amdgpu_vm;
178struct amdgpu_ring;
179struct amdgpu_semaphore;
180struct amdgpu_cs_parser;
181struct amdgpu_irq_src;
182
183enum amdgpu_cp_irq {
184 AMDGPU_CP_IRQ_GFX_EOP = 0,
185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
193
194 AMDGPU_CP_IRQ_LAST
195};
196
197enum amdgpu_sdma_irq {
198 AMDGPU_SDMA_IRQ_TRAP0 = 0,
199 AMDGPU_SDMA_IRQ_TRAP1,
200
201 AMDGPU_SDMA_IRQ_LAST
202};
203
204enum amdgpu_thermal_irq {
205 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
206 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
207
208 AMDGPU_THERMAL_IRQ_LAST
209};
210
211/*
212 * IP block functions
213 */
214enum amdgpu_ip_block_type {
215 AMDGPU_IP_BLOCK_TYPE_COMMON,
216 AMDGPU_IP_BLOCK_TYPE_GMC,
217 AMDGPU_IP_BLOCK_TYPE_IH,
218 AMDGPU_IP_BLOCK_TYPE_SMC,
219 AMDGPU_IP_BLOCK_TYPE_DCE,
220 AMDGPU_IP_BLOCK_TYPE_GFX,
221 AMDGPU_IP_BLOCK_TYPE_SDMA,
222 AMDGPU_IP_BLOCK_TYPE_UVD,
223 AMDGPU_IP_BLOCK_TYPE_VCE,
224};
225
226enum amdgpu_clockgating_state {
227 AMDGPU_CG_STATE_GATE = 0,
228 AMDGPU_CG_STATE_UNGATE,
229};
230
231enum amdgpu_powergating_state {
232 AMDGPU_PG_STATE_GATE = 0,
233 AMDGPU_PG_STATE_UNGATE,
234};
235
236struct amdgpu_ip_funcs {
237 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
238 int (*early_init)(struct amdgpu_device *adev);
239 /* sets up late driver/hw state (post hw_init) - Optional */
240 int (*late_init)(struct amdgpu_device *adev);
241 /* sets up driver state, does not configure hw */
242 int (*sw_init)(struct amdgpu_device *adev);
243 /* tears down driver state, does not configure hw */
244 int (*sw_fini)(struct amdgpu_device *adev);
245 /* sets up the hw state */
246 int (*hw_init)(struct amdgpu_device *adev);
247 /* tears down the hw state */
248 int (*hw_fini)(struct amdgpu_device *adev);
249 /* handles IP specific hw/sw changes for suspend */
250 int (*suspend)(struct amdgpu_device *adev);
251 /* handles IP specific hw/sw changes for resume */
252 int (*resume)(struct amdgpu_device *adev);
253 /* returns current IP block idle status */
254 bool (*is_idle)(struct amdgpu_device *adev);
255 /* poll for idle */
256 int (*wait_for_idle)(struct amdgpu_device *adev);
257 /* soft reset the IP block */
258 int (*soft_reset)(struct amdgpu_device *adev);
259 /* dump the IP block status registers */
260 void (*print_status)(struct amdgpu_device *adev);
261 /* enable/disable cg for the IP block */
262 int (*set_clockgating_state)(struct amdgpu_device *adev,
263 enum amdgpu_clockgating_state state);
264 /* enable/disable pg for the IP block */
265 int (*set_powergating_state)(struct amdgpu_device *adev,
266 enum amdgpu_powergating_state state);
267};
268
269int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
270 enum amdgpu_ip_block_type block_type,
271 enum amdgpu_clockgating_state state);
272int amdgpu_set_powergating_state(struct amdgpu_device *adev,
273 enum amdgpu_ip_block_type block_type,
274 enum amdgpu_powergating_state state);
275
276struct amdgpu_ip_block_version {
277 enum amdgpu_ip_block_type type;
278 u32 major;
279 u32 minor;
280 u32 rev;
281 const struct amdgpu_ip_funcs *funcs;
282};
283
284int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
285 enum amdgpu_ip_block_type type,
286 u32 major, u32 minor);
287
288const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
289 struct amdgpu_device *adev,
290 enum amdgpu_ip_block_type type);
291
292/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
293struct amdgpu_buffer_funcs {
294 /* maximum bytes in a single operation */
295 uint32_t copy_max_bytes;
296
297 /* number of dw to reserve per operation */
298 unsigned copy_num_dw;
299
300 /* used for buffer migration */
301 void (*emit_copy_buffer)(struct amdgpu_ring *ring,
302 /* src addr in bytes */
303 uint64_t src_offset,
304 /* dst addr in bytes */
305 uint64_t dst_offset,
306 /* number of byte to transfer */
307 uint32_t byte_count);
308
309 /* maximum bytes in a single operation */
310 uint32_t fill_max_bytes;
311
312 /* number of dw to reserve per operation */
313 unsigned fill_num_dw;
314
315 /* used for buffer clearing */
316 void (*emit_fill_buffer)(struct amdgpu_ring *ring,
317 /* value to write to memory */
318 uint32_t src_data,
319 /* dst addr in bytes */
320 uint64_t dst_offset,
321 /* number of byte to fill */
322 uint32_t byte_count);
323};
324
325/* provided by hw blocks that can write ptes, e.g., sdma */
326struct amdgpu_vm_pte_funcs {
327 /* copy pte entries from GART */
328 void (*copy_pte)(struct amdgpu_ib *ib,
329 uint64_t pe, uint64_t src,
330 unsigned count);
331 /* write pte one entry at a time with addr mapping */
332 void (*write_pte)(struct amdgpu_ib *ib,
333 uint64_t pe,
334 uint64_t addr, unsigned count,
335 uint32_t incr, uint32_t flags);
336 /* for linear pte/pde updates without addr mapping */
337 void (*set_pte_pde)(struct amdgpu_ib *ib,
338 uint64_t pe,
339 uint64_t addr, unsigned count,
340 uint32_t incr, uint32_t flags);
341 /* pad the indirect buffer to the necessary number of dw */
342 void (*pad_ib)(struct amdgpu_ib *ib);
343};
344
345/* provided by the gmc block */
346struct amdgpu_gart_funcs {
347 /* flush the vm tlb via mmio */
348 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
349 uint32_t vmid);
350 /* write pte/pde updates using the cpu */
351 int (*set_pte_pde)(struct amdgpu_device *adev,
352 void *cpu_pt_addr, /* cpu addr of page table */
353 uint32_t gpu_page_idx, /* pte/pde to update */
354 uint64_t addr, /* addr to write into pte/pde */
355 uint32_t flags); /* access flags */
356};
357
358/* provided by the ih block */
359struct amdgpu_ih_funcs {
360 /* ring read/write ptr handling, called from interrupt context */
361 u32 (*get_wptr)(struct amdgpu_device *adev);
362 void (*decode_iv)(struct amdgpu_device *adev,
363 struct amdgpu_iv_entry *entry);
364 void (*set_rptr)(struct amdgpu_device *adev);
365};
366
367/* provided by hw blocks that expose a ring buffer for commands */
368struct amdgpu_ring_funcs {
369 /* ring read/write ptr handling */
370 u32 (*get_rptr)(struct amdgpu_ring *ring);
371 u32 (*get_wptr)(struct amdgpu_ring *ring);
372 void (*set_wptr)(struct amdgpu_ring *ring);
373 /* validating and patching of IBs */
374 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
375 /* command emit functions */
376 void (*emit_ib)(struct amdgpu_ring *ring,
377 struct amdgpu_ib *ib);
378 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
379 uint64_t seq, bool write64bit);
380 bool (*emit_semaphore)(struct amdgpu_ring *ring,
381 struct amdgpu_semaphore *semaphore,
382 bool emit_wait);
383 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
384 uint64_t pd_addr);
385 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
386 uint32_t gds_base, uint32_t gds_size,
387 uint32_t gws_base, uint32_t gws_size,
388 uint32_t oa_base, uint32_t oa_size);
389 /* testing functions */
390 int (*test_ring)(struct amdgpu_ring *ring);
391 int (*test_ib)(struct amdgpu_ring *ring);
392 bool (*is_lockup)(struct amdgpu_ring *ring);
393};
394
395/*
396 * BIOS.
397 */
398bool amdgpu_get_bios(struct amdgpu_device *adev);
399bool amdgpu_read_bios(struct amdgpu_device *adev);
400
401/*
402 * Dummy page
403 */
404struct amdgpu_dummy_page {
405 struct page *page;
406 dma_addr_t addr;
407};
408int amdgpu_dummy_page_init(struct amdgpu_device *adev);
409void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
410
411
412/*
413 * Clocks
414 */
415
416#define AMDGPU_MAX_PPLL 3
417
418struct amdgpu_clock {
419 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
420 struct amdgpu_pll spll;
421 struct amdgpu_pll mpll;
422 /* 10 Khz units */
423 uint32_t default_mclk;
424 uint32_t default_sclk;
425 uint32_t default_dispclk;
426 uint32_t current_dispclk;
427 uint32_t dp_extclk;
428 uint32_t max_pixel_clock;
429};
430
431/*
432 * Fences.
433 */
434struct amdgpu_fence_driver {
435 struct amdgpu_ring *ring;
436 uint64_t gpu_addr;
437 volatile uint32_t *cpu_addr;
438 /* sync_seq is protected by ring emission lock */
439 uint64_t sync_seq[AMDGPU_MAX_RINGS];
440 atomic64_t last_seq;
441 bool initialized;
442 bool delayed_irq;
443 struct amdgpu_irq_src *irq_src;
444 unsigned irq_type;
445 struct delayed_work lockup_work;
446};
447
448/* some special values for the owner field */
449#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
450#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
451#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
452
453struct amdgpu_fence {
454 struct fence base;
455
456 /* RB, DMA, etc. */
457 struct amdgpu_ring *ring;
458 uint64_t seq;
459
460 /* filp or special value for fence creator */
461 void *owner;
462
463 wait_queue_t fence_wake;
464};
465
466struct amdgpu_user_fence {
467 /* write-back bo */
468 struct amdgpu_bo *bo;
469 /* write-back address offset to bo start */
470 uint32_t offset;
471};
472
473int amdgpu_fence_driver_init(struct amdgpu_device *adev);
474void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
475void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
476
477void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
478int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
479 struct amdgpu_irq_src *irq_src,
480 unsigned irq_type);
481int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
482 struct amdgpu_fence **fence);
483void amdgpu_fence_process(struct amdgpu_ring *ring);
484int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
485int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
486unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
487
488bool amdgpu_fence_signaled(struct amdgpu_fence *fence);
489int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible);
490int amdgpu_fence_wait_any(struct amdgpu_device *adev,
491 struct amdgpu_fence **fences,
492 bool intr);
493long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev,
494 u64 *target_seq, bool intr,
495 long timeout);
496struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
497void amdgpu_fence_unref(struct amdgpu_fence **fence);
498
499bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
500 struct amdgpu_ring *ring);
501void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
502 struct amdgpu_ring *ring);
503
504static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
505 struct amdgpu_fence *b)
506{
507 if (!a) {
508 return b;
509 }
510
511 if (!b) {
512 return a;
513 }
514
515 BUG_ON(a->ring != b->ring);
516
517 if (a->seq > b->seq) {
518 return a;
519 } else {
520 return b;
521 }
522}
523
524static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
525 struct amdgpu_fence *b)
526{
527 if (!a) {
528 return false;
529 }
530
531 if (!b) {
532 return true;
533 }
534
535 BUG_ON(a->ring != b->ring);
536
537 return a->seq < b->seq;
538}
539
540int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
541 void *owner, struct amdgpu_fence **fence);
542
543/*
544 * TTM.
545 */
546struct amdgpu_mman {
547 struct ttm_bo_global_ref bo_global_ref;
548 struct drm_global_reference mem_global_ref;
549 struct ttm_bo_device bdev;
550 bool mem_global_referenced;
551 bool initialized;
552
553#if defined(CONFIG_DEBUG_FS)
554 struct dentry *vram;
555 struct dentry *gtt;
556#endif
557
558 /* buffer handling */
559 const struct amdgpu_buffer_funcs *buffer_funcs;
560 struct amdgpu_ring *buffer_funcs_ring;
561};
562
563int amdgpu_copy_buffer(struct amdgpu_ring *ring,
564 uint64_t src_offset,
565 uint64_t dst_offset,
566 uint32_t byte_count,
567 struct reservation_object *resv,
568 struct amdgpu_fence **fence);
569int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
570
571struct amdgpu_bo_list_entry {
572 struct amdgpu_bo *robj;
573 struct ttm_validate_buffer tv;
574 struct amdgpu_bo_va *bo_va;
575 unsigned prefered_domains;
576 unsigned allowed_domains;
577 uint32_t priority;
578};
579
580struct amdgpu_bo_va_mapping {
581 struct list_head list;
582 struct interval_tree_node it;
583 uint64_t offset;
584 uint32_t flags;
585};
586
587/* bo virtual addresses in a specific vm */
588struct amdgpu_bo_va {
589 /* protected by bo being reserved */
590 struct list_head bo_list;
591 uint64_t addr;
592 struct amdgpu_fence *last_pt_update;
593 unsigned ref_count;
594
595 /* protected by vm mutex */
596 struct list_head mappings;
597 struct list_head vm_status;
598
599 /* constant after initialization */
600 struct amdgpu_vm *vm;
601 struct amdgpu_bo *bo;
602};
603
604struct amdgpu_bo {
605 /* Protected by gem.mutex */
606 struct list_head list;
607 /* Protected by tbo.reserved */
608 u32 initial_domain;
609 struct ttm_place placements[4];
610 struct ttm_placement placement;
611 struct ttm_buffer_object tbo;
612 struct ttm_bo_kmap_obj kmap;
613 u64 flags;
614 unsigned pin_count;
615 void *kptr;
616 u64 tiling_flags;
617 u64 metadata_flags;
618 void *metadata;
619 u32 metadata_size;
620 /* list of all virtual address to which this bo
621 * is associated to
622 */
623 struct list_head va;
624 /* Constant after initialization */
625 struct amdgpu_device *adev;
626 struct drm_gem_object gem_base;
627
628 struct ttm_bo_kmap_obj dma_buf_vmap;
629 pid_t pid;
630 struct amdgpu_mn *mn;
631 struct list_head mn_list;
632};
633#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
634
635void amdgpu_gem_object_free(struct drm_gem_object *obj);
636int amdgpu_gem_object_open(struct drm_gem_object *obj,
637 struct drm_file *file_priv);
638void amdgpu_gem_object_close(struct drm_gem_object *obj,
639 struct drm_file *file_priv);
640unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
641struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
642struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
643 struct dma_buf_attachment *attach,
644 struct sg_table *sg);
645struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
646 struct drm_gem_object *gobj,
647 int flags);
648int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
649void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
650struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
651void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
652void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
653int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
654
655/* sub-allocation manager, it has to be protected by another lock.
656 * By conception this is an helper for other part of the driver
657 * like the indirect buffer or semaphore, which both have their
658 * locking.
659 *
660 * Principe is simple, we keep a list of sub allocation in offset
661 * order (first entry has offset == 0, last entry has the highest
662 * offset).
663 *
664 * When allocating new object we first check if there is room at
665 * the end total_size - (last_object_offset + last_object_size) >=
666 * alloc_size. If so we allocate new object there.
667 *
668 * When there is not enough room at the end, we start waiting for
669 * each sub object until we reach object_offset+object_size >=
670 * alloc_size, this object then become the sub object we return.
671 *
672 * Alignment can't be bigger than page size.
673 *
674 * Hole are not considered for allocation to keep things simple.
675 * Assumption is that there won't be hole (all object on same
676 * alignment).
677 */
678struct amdgpu_sa_manager {
679 wait_queue_head_t wq;
680 struct amdgpu_bo *bo;
681 struct list_head *hole;
682 struct list_head flist[AMDGPU_MAX_RINGS];
683 struct list_head olist;
684 unsigned size;
685 uint64_t gpu_addr;
686 void *cpu_ptr;
687 uint32_t domain;
688 uint32_t align;
689};
690
691struct amdgpu_sa_bo;
692
693/* sub-allocation buffer */
694struct amdgpu_sa_bo {
695 struct list_head olist;
696 struct list_head flist;
697 struct amdgpu_sa_manager *manager;
698 unsigned soffset;
699 unsigned eoffset;
700 struct amdgpu_fence *fence;
701};
702
703/*
704 * GEM objects.
705 */
706struct amdgpu_gem {
707 struct mutex mutex;
708 struct list_head objects;
709};
710
711int amdgpu_gem_init(struct amdgpu_device *adev);
712void amdgpu_gem_fini(struct amdgpu_device *adev);
713int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
714 int alignment, u32 initial_domain,
715 u64 flags, bool kernel,
716 struct drm_gem_object **obj);
717
718int amdgpu_mode_dumb_create(struct drm_file *file_priv,
719 struct drm_device *dev,
720 struct drm_mode_create_dumb *args);
721int amdgpu_mode_dumb_mmap(struct drm_file *filp,
722 struct drm_device *dev,
723 uint32_t handle, uint64_t *offset_p);
724
725/*
726 * Semaphores.
727 */
728struct amdgpu_semaphore {
729 struct amdgpu_sa_bo *sa_bo;
730 signed waiters;
731 uint64_t gpu_addr;
732};
733
734int amdgpu_semaphore_create(struct amdgpu_device *adev,
735 struct amdgpu_semaphore **semaphore);
736bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
737 struct amdgpu_semaphore *semaphore);
738bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
739 struct amdgpu_semaphore *semaphore);
740void amdgpu_semaphore_free(struct amdgpu_device *adev,
741 struct amdgpu_semaphore **semaphore,
742 struct amdgpu_fence *fence);
743
744/*
745 * Synchronization
746 */
747struct amdgpu_sync {
748 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
749 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
750 struct amdgpu_fence *last_vm_update;
751};
752
753void amdgpu_sync_create(struct amdgpu_sync *sync);
754void amdgpu_sync_fence(struct amdgpu_sync *sync,
755 struct amdgpu_fence *fence);
756int amdgpu_sync_resv(struct amdgpu_device *adev,
757 struct amdgpu_sync *sync,
758 struct reservation_object *resv,
759 void *owner);
760int amdgpu_sync_rings(struct amdgpu_sync *sync,
761 struct amdgpu_ring *ring);
762void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
763 struct amdgpu_fence *fence);
764
765/*
766 * GART structures, functions & helpers
767 */
768struct amdgpu_mc;
769
770#define AMDGPU_GPU_PAGE_SIZE 4096
771#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
772#define AMDGPU_GPU_PAGE_SHIFT 12
773#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
774
775struct amdgpu_gart {
776 dma_addr_t table_addr;
777 struct amdgpu_bo *robj;
778 void *ptr;
779 unsigned num_gpu_pages;
780 unsigned num_cpu_pages;
781 unsigned table_size;
782 struct page **pages;
783 dma_addr_t *pages_addr;
784 bool ready;
785 const struct amdgpu_gart_funcs *gart_funcs;
786};
787
788int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
789void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
790int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
791void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
792int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
793void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
794int amdgpu_gart_init(struct amdgpu_device *adev);
795void amdgpu_gart_fini(struct amdgpu_device *adev);
796void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
797 int pages);
798int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
799 int pages, struct page **pagelist,
800 dma_addr_t *dma_addr, uint32_t flags);
801
802/*
803 * GPU MC structures, functions & helpers
804 */
805struct amdgpu_mc {
806 resource_size_t aper_size;
807 resource_size_t aper_base;
808 resource_size_t agp_base;
809 /* for some chips with <= 32MB we need to lie
810 * about vram size near mc fb location */
811 u64 mc_vram_size;
812 u64 visible_vram_size;
813 u64 gtt_size;
814 u64 gtt_start;
815 u64 gtt_end;
816 u64 vram_start;
817 u64 vram_end;
818 unsigned vram_width;
819 u64 real_vram_size;
820 int vram_mtrr;
821 u64 gtt_base_align;
822 u64 mc_mask;
823 const struct firmware *fw; /* MC firmware */
824 uint32_t fw_version;
825 struct amdgpu_irq_src vm_fault;
826 bool is_gddr5;
827};
828
829/*
830 * GPU doorbell structures, functions & helpers
831 */
832typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
833{
834 AMDGPU_DOORBELL_KIQ = 0x000,
835 AMDGPU_DOORBELL_HIQ = 0x001,
836 AMDGPU_DOORBELL_DIQ = 0x002,
837 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
838 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
839 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
840 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
841 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
842 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
843 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
844 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
845 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
846 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
847 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
848 AMDGPU_DOORBELL_IH = 0x1E8,
849 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
850 AMDGPU_DOORBELL_INVALID = 0xFFFF
851} AMDGPU_DOORBELL_ASSIGNMENT;
852
853struct amdgpu_doorbell {
854 /* doorbell mmio */
855 resource_size_t base;
856 resource_size_t size;
857 u32 __iomem *ptr;
858 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
859};
860
861void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
862 phys_addr_t *aperture_base,
863 size_t *aperture_size,
864 size_t *start_offset);
865
866/*
867 * IRQS.
868 */
869
870struct amdgpu_flip_work {
871 struct work_struct flip_work;
872 struct work_struct unpin_work;
873 struct amdgpu_device *adev;
874 int crtc_id;
875 uint64_t base;
876 struct drm_pending_vblank_event *event;
877 struct amdgpu_bo *old_rbo;
878 struct fence *fence;
879};
880
881
882/*
883 * CP & rings.
884 */
885
886struct amdgpu_ib {
887 struct amdgpu_sa_bo *sa_bo;
888 uint32_t length_dw;
889 uint64_t gpu_addr;
890 uint32_t *ptr;
891 struct amdgpu_ring *ring;
892 struct amdgpu_fence *fence;
893 struct amdgpu_user_fence *user;
894 struct amdgpu_vm *vm;
895 bool is_const_ib;
896 bool flush_hdp_writefifo;
897 struct amdgpu_sync sync;
898 bool gds_needed;
899 uint32_t gds_base, gds_size;
900 uint32_t gws_base, gws_size;
901 uint32_t oa_base, oa_size;
902};
903
904enum amdgpu_ring_type {
905 AMDGPU_RING_TYPE_GFX,
906 AMDGPU_RING_TYPE_COMPUTE,
907 AMDGPU_RING_TYPE_SDMA,
908 AMDGPU_RING_TYPE_UVD,
909 AMDGPU_RING_TYPE_VCE
910};
911
912struct amdgpu_ring {
913 struct amdgpu_device *adev;
914 const struct amdgpu_ring_funcs *funcs;
915 struct amdgpu_fence_driver fence_drv;
916
917 struct mutex *ring_lock;
918 struct amdgpu_bo *ring_obj;
919 volatile uint32_t *ring;
920 unsigned rptr_offs;
921 u64 next_rptr_gpu_addr;
922 volatile u32 *next_rptr_cpu_addr;
923 unsigned wptr;
924 unsigned wptr_old;
925 unsigned ring_size;
926 unsigned ring_free_dw;
927 int count_dw;
928 atomic_t last_rptr;
929 atomic64_t last_activity;
930 uint64_t gpu_addr;
931 uint32_t align_mask;
932 uint32_t ptr_mask;
933 bool ready;
934 u32 nop;
935 u32 idx;
936 u64 last_semaphore_signal_addr;
937 u64 last_semaphore_wait_addr;
938 u32 me;
939 u32 pipe;
940 u32 queue;
941 struct amdgpu_bo *mqd_obj;
942 u32 doorbell_index;
943 bool use_doorbell;
944 unsigned wptr_offs;
945 unsigned next_rptr_offs;
946 unsigned fence_offs;
947 struct drm_file *current_filp;
72efa7eb 948 unsigned current_ctx;
97b2e202
AD		 949 bool need_ctx_switch;
950 enum amdgpu_ring_type type;
951 char name[16];
952};
953
954/*
955 * VM
956 */
957
958/* maximum number of VMIDs */
959#define AMDGPU_NUM_VM 16
960
961/* number of entries in page table */
962#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
963
964/* PTBs (Page Table Blocks) need to be aligned to 32K */
965#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
966#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
967#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
968
969#define AMDGPU_PTE_VALID (1 << 0)
970#define AMDGPU_PTE_SYSTEM (1 << 1)
971#define AMDGPU_PTE_SNOOPED (1 << 2)
972
973/* VI only */
974#define AMDGPU_PTE_EXECUTABLE (1 << 4)
975
976#define AMDGPU_PTE_READABLE (1 << 5)
977#define AMDGPU_PTE_WRITEABLE (1 << 6)
978
979/* PTE (Page Table Entry) fragment field for different page sizes */
980#define AMDGPU_PTE_FRAG_4KB (0 << 7)
981#define AMDGPU_PTE_FRAG_64KB (4 << 7)
982#define AMDGPU_LOG2_PAGES_PER_FRAG 4
983
984struct amdgpu_vm_pt {
985 struct amdgpu_bo *bo;
986 uint64_t addr;
987};
988
989struct amdgpu_vm_id {
990 unsigned id;
991 uint64_t pd_gpu_addr;
992 /* last flushed PD/PT update */
993 struct amdgpu_fence *flushed_updates;
994 /* last use of vmid */
995 struct amdgpu_fence *last_id_use;
996};
997
998struct amdgpu_vm {
999 struct mutex mutex;
1000
1001 struct rb_root va;
1002
1003 /* protecting invalidated and freed */
1004 spinlock_t status_lock;
1005
1006 /* BOs moved, but not yet updated in the PT */
1007 struct list_head invalidated;
1008
1009 /* BOs freed, but not yet updated in the PT */
1010 struct list_head freed;
1011
1012 /* contains the page directory */
1013 struct amdgpu_bo *page_directory;
1014 unsigned max_pde_used;
1015
1016 /* array of page tables, one for each page directory entry */
1017 struct amdgpu_vm_pt *page_tables;
1018
1019 /* for id and flush management per ring */
1020 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
1021};
1022
1023struct amdgpu_vm_manager {
1024 struct amdgpu_fence *active[AMDGPU_NUM_VM];
1025 uint32_t max_pfn;
1026 /* number of VMIDs */
1027 unsigned nvm;
1028 /* vram base address for page table entry */
1029 u64 vram_base_offset;
1030 /* is vm enabled? */
1031 bool enabled;
1032 /* for hw to save the PD addr on suspend/resume */
1033 uint32_t saved_table_addr[AMDGPU_NUM_VM];
1034 /* vm pte handling */
1035 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
1036 struct amdgpu_ring *vm_pte_funcs_ring;
1037};
1038
1039/*
1040 * context related structures
1041 */
1042
1043struct amdgpu_ctx_state {
1044 uint64_t flags;
1045 uint64_t hangs;
1046};
1047
1048struct amdgpu_ctx {
1049 /* call kref_get()before CS start and kref_put() after CS fence signaled */
1050 struct kref refcount;
1051 struct amdgpu_fpriv *fpriv;
1052 struct amdgpu_ctx_state state;
1053 uint32_t id;
1054};
1055
1056struct amdgpu_ctx_mgr {
1057 struct amdgpu_device *adev;
1058 struct idr ctx_handles;
1059 /* lock for IDR system */
0147ee0f 1060 struct mutex lock;
97b2e202
AD		 1061};
1062
1063/*
1064 * file private structure
1065 */
1066
1067struct amdgpu_fpriv {
1068 struct amdgpu_vm vm;
1069 struct mutex bo_list_lock;
1070 struct idr bo_list_handles;
1071 struct amdgpu_ctx_mgr ctx_mgr;
1072};
1073
1074/*
1075 * residency list
1076 */
1077
1078struct amdgpu_bo_list {
1079 struct mutex lock;
1080 struct amdgpu_bo *gds_obj;
1081 struct amdgpu_bo *gws_obj;
1082 struct amdgpu_bo *oa_obj;
1083 bool has_userptr;
1084 unsigned num_entries;
1085 struct amdgpu_bo_list_entry *array;
1086};
1087
1088struct amdgpu_bo_list *
1089amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1090void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1091void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1092
1093/*
1094 * GFX stuff
1095 */
1096#include "clearstate_defs.h"
1097
1098struct amdgpu_rlc {
1099 /* for power gating */
1100 struct amdgpu_bo *save_restore_obj;
1101 uint64_t save_restore_gpu_addr;
1102 volatile uint32_t *sr_ptr;
1103 const u32 *reg_list;
1104 u32 reg_list_size;
1105 /* for clear state */
1106 struct amdgpu_bo *clear_state_obj;
1107 uint64_t clear_state_gpu_addr;
1108 volatile uint32_t *cs_ptr;
1109 const struct cs_section_def *cs_data;
1110 u32 clear_state_size;
1111 /* for cp tables */
1112 struct amdgpu_bo *cp_table_obj;
1113 uint64_t cp_table_gpu_addr;
1114 volatile uint32_t *cp_table_ptr;
1115 u32 cp_table_size;
1116};
1117
1118struct amdgpu_mec {
1119 struct amdgpu_bo *hpd_eop_obj;
1120 u64 hpd_eop_gpu_addr;
1121 u32 num_pipe;
1122 u32 num_mec;
1123 u32 num_queue;
1124};
1125
1126/*
1127 * GPU scratch registers structures, functions & helpers
1128 */
1129struct amdgpu_scratch {
1130 unsigned num_reg;
1131 uint32_t reg_base;
1132 bool free[32];
1133 uint32_t reg[32];
1134};
1135
1136/*
1137 * GFX configurations
1138 */
1139struct amdgpu_gca_config {
1140 unsigned max_shader_engines;
1141 unsigned max_tile_pipes;
1142 unsigned max_cu_per_sh;
1143 unsigned max_sh_per_se;
1144 unsigned max_backends_per_se;
1145 unsigned max_texture_channel_caches;
1146 unsigned max_gprs;
1147 unsigned max_gs_threads;
1148 unsigned max_hw_contexts;
1149 unsigned sc_prim_fifo_size_frontend;
1150 unsigned sc_prim_fifo_size_backend;
1151 unsigned sc_hiz_tile_fifo_size;
1152 unsigned sc_earlyz_tile_fifo_size;
1153
1154 unsigned num_tile_pipes;
1155 unsigned backend_enable_mask;
1156 unsigned mem_max_burst_length_bytes;
1157 unsigned mem_row_size_in_kb;
1158 unsigned shader_engine_tile_size;
1159 unsigned num_gpus;
1160 unsigned multi_gpu_tile_size;
1161 unsigned mc_arb_ramcfg;
1162 unsigned gb_addr_config;
1163
1164 uint32_t tile_mode_array[32];
1165 uint32_t macrotile_mode_array[16];
1166};
1167
1168struct amdgpu_gfx {
1169 struct mutex gpu_clock_mutex;
1170 struct amdgpu_gca_config config;
1171 struct amdgpu_rlc rlc;
1172 struct amdgpu_mec mec;
1173 struct amdgpu_scratch scratch;
1174 const struct firmware *me_fw; /* ME firmware */
1175 uint32_t me_fw_version;
1176 const struct firmware *pfp_fw; /* PFP firmware */
1177 uint32_t pfp_fw_version;
1178 const struct firmware *ce_fw; /* CE firmware */
1179 uint32_t ce_fw_version;
1180 const struct firmware *rlc_fw; /* RLC firmware */
1181 uint32_t rlc_fw_version;
1182 const struct firmware *mec_fw; /* MEC firmware */
1183 uint32_t mec_fw_version;
1184 const struct firmware *mec2_fw; /* MEC2 firmware */
1185 uint32_t mec2_fw_version;
1186 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1187 unsigned num_gfx_rings;
1188 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1189 unsigned num_compute_rings;
1190 struct amdgpu_irq_src eop_irq;
1191 struct amdgpu_irq_src priv_reg_irq;
1192 struct amdgpu_irq_src priv_inst_irq;
1193 /* gfx status */
1194 uint32_t gfx_current_status;
1195 /* sync signal for const engine */
1196 unsigned ce_sync_offs;
1197};
1198
1199int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1200 unsigned size, struct amdgpu_ib *ib);
1201void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1202int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1203 struct amdgpu_ib *ib, void *owner);
1204int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1205void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1206int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1207/* Ring access between begin & end cannot sleep */
1208void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1209int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1210int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1211void amdgpu_ring_commit(struct amdgpu_ring *ring);
1212void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1213void amdgpu_ring_undo(struct amdgpu_ring *ring);
1214void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1215void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1216bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1217unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1218 uint32_t **data);
1219int amdgpu_ring_restore(struct amdgpu_ring *ring,
1220 unsigned size, uint32_t *data);
1221int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1222 unsigned ring_size, u32 nop, u32 align_mask,
1223 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1224 enum amdgpu_ring_type ring_type);
1225void amdgpu_ring_fini(struct amdgpu_ring *ring);
1226
1227/*
1228 * CS.
1229 */
1230struct amdgpu_cs_chunk {
1231 uint32_t chunk_id;
1232 uint32_t length_dw;
1233 uint32_t *kdata;
1234 void __user *user_ptr;
1235};
1236
1237struct amdgpu_cs_parser {
1238 struct amdgpu_device *adev;
1239 struct drm_file *filp;
1240 uint32_t ctx_id;
1241 struct amdgpu_bo_list *bo_list;
1242 /* chunks */
1243 unsigned nchunks;
1244 struct amdgpu_cs_chunk *chunks;
1245 /* relocations */
1246 struct amdgpu_bo_list_entry *vm_bos;
1247 struct amdgpu_bo_list_entry *ib_bos;
1248 struct list_head validated;
1249
1250 struct amdgpu_ib *ibs;
1251 uint32_t num_ibs;
1252
1253 struct ww_acquire_ctx ticket;
1254
1255 /* user fence */
1256 struct amdgpu_user_fence uf;
1257};
1258
1259static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1260{
1261 return p->ibs[ib_idx].ptr[idx];
1262}
1263
1264/*
1265 * Writeback
1266 */
1267#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1268
1269struct amdgpu_wb {
1270 struct amdgpu_bo *wb_obj;
1271 volatile uint32_t *wb;
1272 uint64_t gpu_addr;
1273 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1274 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1275};
1276
1277int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1278void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1279
1280/**
1281 * struct amdgpu_pm - power management datas
1282 * It keeps track of various data needed to take powermanagement decision.
1283 */
1284
1285enum amdgpu_pm_state_type {
1286 /* not used for dpm */
1287 POWER_STATE_TYPE_DEFAULT,
1288 POWER_STATE_TYPE_POWERSAVE,
1289 /* user selectable states */
1290 POWER_STATE_TYPE_BATTERY,
1291 POWER_STATE_TYPE_BALANCED,
1292 POWER_STATE_TYPE_PERFORMANCE,
1293 /* internal states */
1294 POWER_STATE_TYPE_INTERNAL_UVD,
1295 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1296 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1297 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1298 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1299 POWER_STATE_TYPE_INTERNAL_BOOT,
1300 POWER_STATE_TYPE_INTERNAL_THERMAL,
1301 POWER_STATE_TYPE_INTERNAL_ACPI,
1302 POWER_STATE_TYPE_INTERNAL_ULV,
1303 POWER_STATE_TYPE_INTERNAL_3DPERF,
1304};
1305
1306enum amdgpu_int_thermal_type {
1307 THERMAL_TYPE_NONE,
1308 THERMAL_TYPE_EXTERNAL,
1309 THERMAL_TYPE_EXTERNAL_GPIO,
1310 THERMAL_TYPE_RV6XX,
1311 THERMAL_TYPE_RV770,
1312 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1313 THERMAL_TYPE_EVERGREEN,
1314 THERMAL_TYPE_SUMO,
1315 THERMAL_TYPE_NI,
1316 THERMAL_TYPE_SI,
1317 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1318 THERMAL_TYPE_CI,
1319 THERMAL_TYPE_KV,
1320};
1321
1322enum amdgpu_dpm_auto_throttle_src {
1323 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1324 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1325};
1326
1327enum amdgpu_dpm_event_src {
1328 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1329 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1330 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1331 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1332 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1333};
1334
1335#define AMDGPU_MAX_VCE_LEVELS 6
1336
1337enum amdgpu_vce_level {
1338 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1339 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1340 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1341 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1342 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1343 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1344};
1345
1346struct amdgpu_ps {
1347 u32 caps; /* vbios flags */
1348 u32 class; /* vbios flags */
1349 u32 class2; /* vbios flags */
1350 /* UVD clocks */
1351 u32 vclk;
1352 u32 dclk;
1353 /* VCE clocks */
1354 u32 evclk;
1355 u32 ecclk;
1356 bool vce_active;
1357 enum amdgpu_vce_level vce_level;
1358 /* asic priv */
1359 void *ps_priv;
1360};
1361
1362struct amdgpu_dpm_thermal {
1363 /* thermal interrupt work */
1364 struct work_struct work;
1365 /* low temperature threshold */
1366 int min_temp;
1367 /* high temperature threshold */
1368 int max_temp;
1369 /* was last interrupt low to high or high to low */
1370 bool high_to_low;
1371 /* interrupt source */
1372 struct amdgpu_irq_src irq;
1373};
1374
1375enum amdgpu_clk_action
1376{
1377 AMDGPU_SCLK_UP = 1,
1378 AMDGPU_SCLK_DOWN
1379};
1380
1381struct amdgpu_blacklist_clocks
1382{
1383 u32 sclk;
1384 u32 mclk;
1385 enum amdgpu_clk_action action;
1386};
1387
1388struct amdgpu_clock_and_voltage_limits {
1389 u32 sclk;
1390 u32 mclk;
1391 u16 vddc;
1392 u16 vddci;
1393};
1394
1395struct amdgpu_clock_array {
1396 u32 count;
1397 u32 *values;
1398};
1399
1400struct amdgpu_clock_voltage_dependency_entry {
1401 u32 clk;
1402 u16 v;
1403};
1404
1405struct amdgpu_clock_voltage_dependency_table {
1406 u32 count;
1407 struct amdgpu_clock_voltage_dependency_entry *entries;
1408};
1409
1410union amdgpu_cac_leakage_entry {
1411 struct {
1412 u16 vddc;
1413 u32 leakage;
1414 };
1415 struct {
1416 u16 vddc1;
1417 u16 vddc2;
1418 u16 vddc3;
1419 };
1420};
1421
1422struct amdgpu_cac_leakage_table {
1423 u32 count;
1424 union amdgpu_cac_leakage_entry *entries;
1425};
1426
1427struct amdgpu_phase_shedding_limits_entry {
1428 u16 voltage;
1429 u32 sclk;
1430 u32 mclk;
1431};
1432
1433struct amdgpu_phase_shedding_limits_table {
1434 u32 count;
1435 struct amdgpu_phase_shedding_limits_entry *entries;
1436};
1437
1438struct amdgpu_uvd_clock_voltage_dependency_entry {
1439 u32 vclk;
1440 u32 dclk;
1441 u16 v;
1442};
1443
1444struct amdgpu_uvd_clock_voltage_dependency_table {
1445 u8 count;
1446 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1447};
1448
1449struct amdgpu_vce_clock_voltage_dependency_entry {
1450 u32 ecclk;
1451 u32 evclk;
1452 u16 v;
1453};
1454
1455struct amdgpu_vce_clock_voltage_dependency_table {
1456 u8 count;
1457 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1458};
1459
1460struct amdgpu_ppm_table {
1461 u8 ppm_design;
1462 u16 cpu_core_number;
1463 u32 platform_tdp;
1464 u32 small_ac_platform_tdp;
1465 u32 platform_tdc;
1466 u32 small_ac_platform_tdc;
1467 u32 apu_tdp;
1468 u32 dgpu_tdp;
1469 u32 dgpu_ulv_power;
1470 u32 tj_max;
1471};
1472
1473struct amdgpu_cac_tdp_table {
1474 u16 tdp;
1475 u16 configurable_tdp;
1476 u16 tdc;
1477 u16 battery_power_limit;
1478 u16 small_power_limit;
1479 u16 low_cac_leakage;
1480 u16 high_cac_leakage;
1481 u16 maximum_power_delivery_limit;
1482};
1483
1484struct amdgpu_dpm_dynamic_state {
1485 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1486 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1487 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1488 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1489 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1490 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1491 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1492 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1493 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1494 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1495 struct amdgpu_clock_array valid_sclk_values;
1496 struct amdgpu_clock_array valid_mclk_values;
1497 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1498 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1499 u32 mclk_sclk_ratio;
1500 u32 sclk_mclk_delta;
1501 u16 vddc_vddci_delta;
1502 u16 min_vddc_for_pcie_gen2;
1503 struct amdgpu_cac_leakage_table cac_leakage_table;
1504 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1505 struct amdgpu_ppm_table *ppm_table;
1506 struct amdgpu_cac_tdp_table *cac_tdp_table;
1507};
1508
1509struct amdgpu_dpm_fan {
1510 u16 t_min;
1511 u16 t_med;
1512 u16 t_high;
1513 u16 pwm_min;
1514 u16 pwm_med;
1515 u16 pwm_high;
1516 u8 t_hyst;
1517 u32 cycle_delay;
1518 u16 t_max;
1519 u8 control_mode;
1520 u16 default_max_fan_pwm;
1521 u16 default_fan_output_sensitivity;
1522 u16 fan_output_sensitivity;
1523 bool ucode_fan_control;
1524};
1525
1526enum amdgpu_pcie_gen {
1527 AMDGPU_PCIE_GEN1 = 0,
1528 AMDGPU_PCIE_GEN2 = 1,
1529 AMDGPU_PCIE_GEN3 = 2,
1530 AMDGPU_PCIE_GEN_INVALID = 0xffff
1531};
1532
1533enum amdgpu_dpm_forced_level {
1534 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1535 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1536 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1537};
1538
1539struct amdgpu_vce_state {
1540 /* vce clocks */
1541 u32 evclk;
1542 u32 ecclk;
1543 /* gpu clocks */
1544 u32 sclk;
1545 u32 mclk;
1546 u8 clk_idx;
1547 u8 pstate;
1548};
1549
1550struct amdgpu_dpm_funcs {
1551 int (*get_temperature)(struct amdgpu_device *adev);
1552 int (*pre_set_power_state)(struct amdgpu_device *adev);
1553 int (*set_power_state)(struct amdgpu_device *adev);
1554 void (*post_set_power_state)(struct amdgpu_device *adev);
1555 void (*display_configuration_changed)(struct amdgpu_device *adev);
1556 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1557 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1558 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1559 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1560 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1561 bool (*vblank_too_short)(struct amdgpu_device *adev);
1562 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1563 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1564 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1565 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1566 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1567 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1568};
1569
1570struct amdgpu_dpm {
1571 struct amdgpu_ps *ps;
1572 /* number of valid power states */
1573 int num_ps;
1574 /* current power state that is active */
1575 struct amdgpu_ps *current_ps;
1576 /* requested power state */
1577 struct amdgpu_ps *requested_ps;
1578 /* boot up power state */
1579 struct amdgpu_ps *boot_ps;
1580 /* default uvd power state */
1581 struct amdgpu_ps *uvd_ps;
1582 /* vce requirements */
1583 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1584 enum amdgpu_vce_level vce_level;
1585 enum amdgpu_pm_state_type state;
1586 enum amdgpu_pm_state_type user_state;
1587 u32 platform_caps;
1588 u32 voltage_response_time;
1589 u32 backbias_response_time;
1590 void *priv;
1591 u32 new_active_crtcs;
1592 int new_active_crtc_count;
1593 u32 current_active_crtcs;
1594 int current_active_crtc_count;
1595 struct amdgpu_dpm_dynamic_state dyn_state;
1596 struct amdgpu_dpm_fan fan;
1597 u32 tdp_limit;
1598 u32 near_tdp_limit;
1599 u32 near_tdp_limit_adjusted;
1600 u32 sq_ramping_threshold;
1601 u32 cac_leakage;
1602 u16 tdp_od_limit;
1603 u32 tdp_adjustment;
1604 u16 load_line_slope;
1605 bool power_control;
1606 bool ac_power;
1607 /* special states active */
1608 bool thermal_active;
1609 bool uvd_active;
1610 bool vce_active;
1611 /* thermal handling */
1612 struct amdgpu_dpm_thermal thermal;
1613 /* forced levels */
1614 enum amdgpu_dpm_forced_level forced_level;
1615};
1616
1617struct amdgpu_pm {
1618 struct mutex mutex;
1619 /* write locked while reprogramming mclk */
1620 struct rw_semaphore mclk_lock;
1621 u32 current_sclk;
1622 u32 current_mclk;
1623 u32 default_sclk;
1624 u32 default_mclk;
1625 struct amdgpu_i2c_chan *i2c_bus;
1626 /* internal thermal controller on rv6xx+ */
1627 enum amdgpu_int_thermal_type int_thermal_type;
1628 struct device *int_hwmon_dev;
1629 /* fan control parameters */
1630 bool no_fan;
1631 u8 fan_pulses_per_revolution;
1632 u8 fan_min_rpm;
1633 u8 fan_max_rpm;
1634 /* dpm */
1635 bool dpm_enabled;
1636 struct amdgpu_dpm dpm;
1637 const struct firmware *fw; /* SMC firmware */
1638 uint32_t fw_version;
1639 const struct amdgpu_dpm_funcs *funcs;
1640};
1641
1642/*
1643 * UVD
1644 */
1645#define AMDGPU_MAX_UVD_HANDLES 10
1646#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1647#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1648#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1649
1650struct amdgpu_uvd {
1651 struct amdgpu_bo *vcpu_bo;
1652 void *cpu_addr;
1653 uint64_t gpu_addr;
1654 void *saved_bo;
1655 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1656 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1657 struct delayed_work idle_work;
1658 const struct firmware *fw; /* UVD firmware */
1659 struct amdgpu_ring ring;
1660 struct amdgpu_irq_src irq;
1661 bool address_64_bit;
1662};
1663
1664/*
1665 * VCE
1666 */
1667#define AMDGPU_MAX_VCE_HANDLES 16
1668#define AMDGPU_VCE_STACK_SIZE (1024*1024)
1669#define AMDGPU_VCE_HEAP_SIZE (4*1024*1024)
1670#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1671
1672struct amdgpu_vce {
1673 struct amdgpu_bo *vcpu_bo;
1674 uint64_t gpu_addr;
1675 unsigned fw_version;
1676 unsigned fb_version;
1677 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1678 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1679 struct delayed_work idle_work;
1680 const struct firmware *fw; /* VCE firmware */
1681 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1682 struct amdgpu_irq_src irq;
1683};
1684
1685/*
1686 * SDMA
1687 */
1688struct amdgpu_sdma {
1689 /* SDMA firmware */
1690 const struct firmware *fw;
1691 uint32_t fw_version;
1692
1693 struct amdgpu_ring ring;
1694};
1695
1696/*
1697 * Firmware
1698 */
1699struct amdgpu_firmware {
1700 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1701 bool smu_load;
1702 struct amdgpu_bo *fw_buf;
1703 unsigned int fw_size;
1704};
1705
1706/*
1707 * Benchmarking
1708 */
1709void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1710
1711
1712/*
1713 * Testing
1714 */
1715void amdgpu_test_moves(struct amdgpu_device *adev);
1716void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1717 struct amdgpu_ring *cpA,
1718 struct amdgpu_ring *cpB);
1719void amdgpu_test_syncing(struct amdgpu_device *adev);
1720
1721/*
1722 * MMU Notifier
1723 */
1724#if defined(CONFIG_MMU_NOTIFIER)
1725int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1726void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1727#else
1728static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1729{
1730 return -ENODEV;
1731}
1732static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1733#endif
1734
1735/*
1736 * Debugfs
1737 */
1738struct amdgpu_debugfs {
1739 struct drm_info_list *files;
1740 unsigned num_files;
1741};
1742
1743int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1744 struct drm_info_list *files,
1745 unsigned nfiles);
1746int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1747
1748#if defined(CONFIG_DEBUG_FS)
1749int amdgpu_debugfs_init(struct drm_minor *minor);
1750void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1751#endif
1752
1753/*
1754 * amdgpu smumgr functions
1755 */
1756struct amdgpu_smumgr_funcs {
1757 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1758 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1759 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1760};
1761
1762/*
1763 * amdgpu smumgr
1764 */
1765struct amdgpu_smumgr {
1766 struct amdgpu_bo *toc_buf;
1767 struct amdgpu_bo *smu_buf;
1768 /* asic priv smu data */
1769 void *priv;
1770 spinlock_t smu_lock;
1771 /* smumgr functions */
1772 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1773 /* ucode loading complete flag */
1774 uint32_t fw_flags;
1775};
1776
1777/*
1778 * ASIC specific register table accessible by UMD
1779 */
1780struct amdgpu_allowed_register_entry {
1781 uint32_t reg_offset;
1782 bool untouched;
1783 bool grbm_indexed;
1784};
1785
1786struct amdgpu_cu_info {
1787 uint32_t number; /* total active CU number */
1788 uint32_t ao_cu_mask;
1789 uint32_t bitmap[4][4];
1790};
1791
1792
1793/*
1794 * ASIC specific functions.
1795 */
1796struct amdgpu_asic_funcs {
1797 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1798 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1799 u32 sh_num, u32 reg_offset, u32 *value);
1800 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1801 int (*reset)(struct amdgpu_device *adev);
1802 /* wait for mc_idle */
1803 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1804 /* get the reference clock */
1805 u32 (*get_xclk)(struct amdgpu_device *adev);
1806 /* get the gpu clock counter */
1807 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1808 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1809 /* MM block clocks */
1810 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1811 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1812};
1813
1814/*
1815 * IOCTL.
1816 */
1817int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1818 struct drm_file *filp);
1819int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1820 struct drm_file *filp);
1821
1822int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1823 struct drm_file *filp);
1824int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1825 struct drm_file *filp);
1826int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1827 struct drm_file *filp);
1828int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1829 struct drm_file *filp);
1830int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1831 struct drm_file *filp);
1832int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1833 struct drm_file *filp);
1834int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1835int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1836
1837int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1838 struct drm_file *filp);
1839
1840/* VRAM scratch page for HDP bug, default vram page */
1841struct amdgpu_vram_scratch {
1842 struct amdgpu_bo *robj;
1843 volatile uint32_t *ptr;
1844 u64 gpu_addr;
1845};
1846
1847/*
1848 * ACPI
1849 */
1850struct amdgpu_atif_notification_cfg {
1851 bool enabled;
1852 int command_code;
1853};
1854
1855struct amdgpu_atif_notifications {
1856 bool display_switch;
1857 bool expansion_mode_change;
1858 bool thermal_state;
1859 bool forced_power_state;
1860 bool system_power_state;
1861 bool display_conf_change;
1862 bool px_gfx_switch;
1863 bool brightness_change;
1864 bool dgpu_display_event;
1865};
1866
1867struct amdgpu_atif_functions {
1868 bool system_params;
1869 bool sbios_requests;
1870 bool select_active_disp;
1871 bool lid_state;
1872 bool get_tv_standard;
1873 bool set_tv_standard;
1874 bool get_panel_expansion_mode;
1875 bool set_panel_expansion_mode;
1876 bool temperature_change;
1877 bool graphics_device_types;
1878};
1879
1880struct amdgpu_atif {
1881 struct amdgpu_atif_notifications notifications;
1882 struct amdgpu_atif_functions functions;
1883 struct amdgpu_atif_notification_cfg notification_cfg;
1884 struct amdgpu_encoder *encoder_for_bl;
1885};
1886
1887struct amdgpu_atcs_functions {
1888 bool get_ext_state;
1889 bool pcie_perf_req;
1890 bool pcie_dev_rdy;
1891 bool pcie_bus_width;
1892};
1893
1894struct amdgpu_atcs {
1895 struct amdgpu_atcs_functions functions;
1896};
1897
1898int amdgpu_ctx_alloc(struct amdgpu_device *adev,struct amdgpu_fpriv *fpriv,
1899 uint32_t *id,uint32_t flags);
1900int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1901 uint32_t id);
1902int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1903 uint32_t id,struct amdgpu_ctx_state *state);
1904
1905void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
66b3cf2a
JZ		 1906struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1907int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
97b2e202
AD		 1908
1909extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1910 struct drm_file *filp);
1911
1912/*
1913 * Core structure, functions and helpers.
1914 */
1915typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1916typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1917
1918typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1919typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1920
1921struct amdgpu_device {
1922 struct device *dev;
1923 struct drm_device *ddev;
1924 struct pci_dev *pdev;
1925 struct rw_semaphore exclusive_lock;
1926
1927 /* ASIC */
1928 enum amdgpu_asic_type asic_type;
1929 uint32_t family;
1930 uint32_t rev_id;
1931 uint32_t external_rev_id;
1932 unsigned long flags;
1933 int usec_timeout;
1934 const struct amdgpu_asic_funcs *asic_funcs;
1935 bool shutdown;
1936 bool suspend;
1937 bool need_dma32;
1938 bool accel_working;
1939 bool needs_reset;
1940 struct work_struct reset_work;
1941 struct notifier_block acpi_nb;
1942 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1943 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1944 unsigned debugfs_count;
1945#if defined(CONFIG_DEBUG_FS)
1946 struct dentry *debugfs_regs;
1947#endif
1948 struct amdgpu_atif atif;
1949 struct amdgpu_atcs atcs;
1950 struct mutex srbm_mutex;
1951 /* GRBM index mutex. Protects concurrent access to GRBM index */
1952 struct mutex grbm_idx_mutex;
1953 struct dev_pm_domain vga_pm_domain;
1954 bool have_disp_power_ref;
1955
1956 /* BIOS */
1957 uint8_t *bios;
1958 bool is_atom_bios;
1959 uint16_t bios_header_start;
1960 struct amdgpu_bo *stollen_vga_memory;
1961 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1962
1963 /* Register/doorbell mmio */
1964 resource_size_t rmmio_base;
1965 resource_size_t rmmio_size;
1966 void __iomem *rmmio;
1967 /* protects concurrent MM_INDEX/DATA based register access */
1968 spinlock_t mmio_idx_lock;
1969 /* protects concurrent SMC based register access */
1970 spinlock_t smc_idx_lock;
1971 amdgpu_rreg_t smc_rreg;
1972 amdgpu_wreg_t smc_wreg;
1973 /* protects concurrent PCIE register access */
1974 spinlock_t pcie_idx_lock;
1975 amdgpu_rreg_t pcie_rreg;
1976 amdgpu_wreg_t pcie_wreg;
1977 /* protects concurrent UVD register access */
1978 spinlock_t uvd_ctx_idx_lock;
1979 amdgpu_rreg_t uvd_ctx_rreg;
1980 amdgpu_wreg_t uvd_ctx_wreg;
1981 /* protects concurrent DIDT register access */
1982 spinlock_t didt_idx_lock;
1983 amdgpu_rreg_t didt_rreg;
1984 amdgpu_wreg_t didt_wreg;
1985 /* protects concurrent ENDPOINT (audio) register access */
1986 spinlock_t audio_endpt_idx_lock;
1987 amdgpu_block_rreg_t audio_endpt_rreg;
1988 amdgpu_block_wreg_t audio_endpt_wreg;
1989 void __iomem *rio_mem;
1990 resource_size_t rio_mem_size;
1991 struct amdgpu_doorbell doorbell;
1992
1993 /* clock/pll info */
1994 struct amdgpu_clock clock;
1995
1996 /* MC */
1997 struct amdgpu_mc mc;
1998 struct amdgpu_gart gart;
1999 struct amdgpu_dummy_page dummy_page;
2000 struct amdgpu_vm_manager vm_manager;
2001
2002 /* memory management */
2003 struct amdgpu_mman mman;
2004 struct amdgpu_gem gem;
2005 struct amdgpu_vram_scratch vram_scratch;
2006 struct amdgpu_wb wb;
2007 atomic64_t vram_usage;
2008 atomic64_t vram_vis_usage;
2009 atomic64_t gtt_usage;
2010 atomic64_t num_bytes_moved;
2011
2012 /* display */
2013 struct amdgpu_mode_info mode_info;
2014 struct work_struct hotplug_work;
2015 struct amdgpu_irq_src crtc_irq;
2016 struct amdgpu_irq_src pageflip_irq;
2017 struct amdgpu_irq_src hpd_irq;
2018
2019 /* rings */
2020 wait_queue_head_t fence_queue;
2021 unsigned fence_context;
2022 struct mutex ring_lock;
2023 unsigned num_rings;
2024 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2025 bool ib_pool_ready;
2026 struct amdgpu_sa_manager ring_tmp_bo;
2027
2028 /* interrupts */
2029 struct amdgpu_irq irq;
2030
2031 /* dpm */
2032 struct amdgpu_pm pm;
2033 u32 cg_flags;
2034 u32 pg_flags;
2035
2036 /* amdgpu smumgr */
2037 struct amdgpu_smumgr smu;
2038
2039 /* gfx */
2040 struct amdgpu_gfx gfx;
2041
2042 /* sdma */
2043 struct amdgpu_sdma sdma[2];
2044 struct amdgpu_irq_src sdma_trap_irq;
2045 struct amdgpu_irq_src sdma_illegal_inst_irq;
2046
2047 /* uvd */
2048 bool has_uvd;
2049 struct amdgpu_uvd uvd;
2050
2051 /* vce */
2052 struct amdgpu_vce vce;
2053
2054 /* firmwares */
2055 struct amdgpu_firmware firmware;
2056
2057 /* GDS */
2058 struct amdgpu_gds gds;
2059
2060 const struct amdgpu_ip_block_version *ip_blocks;
2061 int num_ip_blocks;
2062 bool *ip_block_enabled;
2063 struct mutex mn_lock;
2064 DECLARE_HASHTABLE(mn_hash, 7);
2065
2066 /* tracking pinned memory */
2067 u64 vram_pin_size;
2068 u64 gart_pin_size;
2069};
2070
2071bool amdgpu_device_is_px(struct drm_device *dev);
2072int amdgpu_device_init(struct amdgpu_device *adev,
2073 struct drm_device *ddev,
2074 struct pci_dev *pdev,
2075 uint32_t flags);
2076void amdgpu_device_fini(struct amdgpu_device *adev);
2077int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2078
2079uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2080 bool always_indirect);
2081void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2082 bool always_indirect);
2083u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2084void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2085
2086u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2087void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2088
2089/*
2090 * Cast helper
2091 */
2092extern const struct fence_ops amdgpu_fence_ops;
2093static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2094{
2095 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2096
2097 if (__f->base.ops == &amdgpu_fence_ops)
2098 return __f;
2099
2100 return NULL;
2101}
2102
2103/*
2104 * Registers read & write functions.
2105 */
2106#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2107#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2108#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2109#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2110#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2111#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2112#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2113#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2114#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2115#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2116#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2117#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2118#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2119#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2120#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2121#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2122#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2123#define WREG32_P(reg, val, mask) \
2124 do { \
2125 uint32_t tmp_ = RREG32(reg); \
2126 tmp_ &= (mask); \
2127 tmp_ |= ((val) & ~(mask)); \
2128 WREG32(reg, tmp_); \
2129 } while (0)
2130#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2131#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2132#define WREG32_PLL_P(reg, val, mask) \
2133 do { \
2134 uint32_t tmp_ = RREG32_PLL(reg); \
2135 tmp_ &= (mask); \
2136 tmp_ |= ((val) & ~(mask)); \
2137 WREG32_PLL(reg, tmp_); \
2138 } while (0)
2139#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2140#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2141#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2142
2143#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2144#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2145
2146#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2147#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2148
2149#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2150 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2151 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2152
2153#define REG_GET_FIELD(value, reg, field) \
2154 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2155
2156/*
2157 * BIOS helpers.
2158 */
2159#define RBIOS8(i) (adev->bios[i])
2160#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2161#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2162
2163/*
2164 * RING helpers.
2165 */
2166static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2167{
2168 if (ring->count_dw <= 0)
2169 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2170 ring->ring[ring->wptr++] = v;
2171 ring->wptr &= ring->ptr_mask;
2172 ring->count_dw--;
2173 ring->ring_free_dw--;
2174}
2175
2176/*
2177 * ASICs macro.
2178 */
2179#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2180#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2181#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2182#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2183#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2184#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2185#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2186#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2187#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2188#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2189#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2190#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2191#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2192#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2193#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2194#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2195#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2196#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2197#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2198#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2199#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2200#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2201#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2202#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2203#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2204#define amdgpu_ring_emit_fence(r, addr, seq, write64bit) (r)->funcs->emit_fence((r), (addr), (seq), (write64bit))
2205#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2206#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2207#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2208#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2209#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2210#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2211#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2212#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2213#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2214#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2215#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2216#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2217#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2218#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2219#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2220#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2221#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2222#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2223#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2224#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2225#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2226#define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2227#define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2228#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2229#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2230#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2231#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2232#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2233#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2234#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2235#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2236#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2237#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2238#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2239#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2240#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2241#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2242#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2243#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2244#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2245
2246#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2247
2248/* Common functions */
2249int amdgpu_gpu_reset(struct amdgpu_device *adev);
2250void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2251bool amdgpu_card_posted(struct amdgpu_device *adev);
2252void amdgpu_update_display_priority(struct amdgpu_device *adev);
2253bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2254int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2255int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2256 u32 ip_instance, u32 ring,
2257 struct amdgpu_ring **out_ring);
2258void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2259bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2260int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2261 uint32_t flags);
2262bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2263bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2264uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2265 struct ttm_mem_reg *mem);
2266void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2267void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2268void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2269void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2270 const u32 *registers,
2271 const u32 array_size);
2272
2273bool amdgpu_device_is_px(struct drm_device *dev);
2274/* atpx handler */
2275#if defined(CONFIG_VGA_SWITCHEROO)
2276void amdgpu_register_atpx_handler(void);
2277void amdgpu_unregister_atpx_handler(void);
2278#else
2279static inline void amdgpu_register_atpx_handler(void) {}
2280static inline void amdgpu_unregister_atpx_handler(void) {}
2281#endif
2282
2283/*
2284 * KMS
2285 */
2286extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2287extern int amdgpu_max_kms_ioctl;
2288
2289int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2290int amdgpu_driver_unload_kms(struct drm_device *dev);
2291void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2292int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2293void amdgpu_driver_postclose_kms(struct drm_device *dev,
2294 struct drm_file *file_priv);
2295void amdgpu_driver_preclose_kms(struct drm_device *dev,
2296 struct drm_file *file_priv);
2297int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2298int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2299u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2300int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2301void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2302int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2303 int *max_error,
2304 struct timeval *vblank_time,
2305 unsigned flags);
2306long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2307 unsigned long arg);
2308
2309/*
2310 * vm
2311 */
2312int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2313void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2314struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2315 struct amdgpu_vm *vm,
2316 struct list_head *head);
2317struct amdgpu_fence *amdgpu_vm_grab_id(struct amdgpu_ring *ring,
2318 struct amdgpu_vm *vm);
2319void amdgpu_vm_flush(struct amdgpu_ring *ring,
2320 struct amdgpu_vm *vm,
2321 struct amdgpu_fence *updates);
2322void amdgpu_vm_fence(struct amdgpu_device *adev,
2323 struct amdgpu_vm *vm,
2324 struct amdgpu_fence *fence);
2325uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2326int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2327 struct amdgpu_vm *vm);
2328int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2329 struct amdgpu_vm *vm);
2330int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
2331 struct amdgpu_vm *vm);
2332int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2333 struct amdgpu_bo_va *bo_va,
2334 struct ttm_mem_reg *mem);
2335void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2336 struct amdgpu_bo *bo);
2337struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2338 struct amdgpu_bo *bo);
2339struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2340 struct amdgpu_vm *vm,
2341 struct amdgpu_bo *bo);
2342int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2343 struct amdgpu_bo_va *bo_va,
2344 uint64_t addr, uint64_t offset,
2345 uint64_t size, uint32_t flags);
2346int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2347 struct amdgpu_bo_va *bo_va,
2348 uint64_t addr);
2349void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2350 struct amdgpu_bo_va *bo_va);
2351
2352/*
2353 * functions used by amdgpu_encoder.c
2354 */
2355struct amdgpu_afmt_acr {
2356 u32 clock;
2357
2358 int n_32khz;
2359 int cts_32khz;
2360
2361 int n_44_1khz;
2362 int cts_44_1khz;
2363
2364 int n_48khz;
2365 int cts_48khz;
2366
2367};
2368
2369struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2370
2371/* amdgpu_acpi.c */
2372#if defined(CONFIG_ACPI)
2373int amdgpu_acpi_init(struct amdgpu_device *adev);
2374void amdgpu_acpi_fini(struct amdgpu_device *adev);
2375bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2376int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2377 u8 perf_req, bool advertise);
2378int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2379#else
2380static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2381static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2382#endif
2383
2384struct amdgpu_bo_va_mapping *
2385amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2386 uint64_t addr, struct amdgpu_bo **bo);
2387
2388#include "amdgpu_object.h"
2389
2390#endif
Linux 6.x block layer and io_uring tree(s)