[linux-2.6-block.git] / drivers / gpio / gpio-zx.c

/*
 * Copyright (C) 2015 Linaro Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define ZX_GPIO_DIR	0x00
#define ZX_GPIO_IVE	0x04
#define ZX_GPIO_IV	0x08
#define ZX_GPIO_IEP	0x0C
#define ZX_GPIO_IEN	0x10
#define ZX_GPIO_DI	0x14
#define ZX_GPIO_DO1	0x18
#define ZX_GPIO_DO0	0x1C
#define ZX_GPIO_DO	0x20

#define ZX_GPIO_IM	0x28
#define ZX_GPIO_IE	0x2C

#define ZX_GPIO_MIS	0x30
#define ZX_GPIO_IC	0x34

#define ZX_GPIO_NR	16

struct zx_gpio {
	spinlock_t		lock;

	void __iomem		*base;
	struct gpio_chip	gc;
};

static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct zx_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags;
	u16 gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
	gpiodir &= ~BIT(offset);
	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct zx_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags;
	u16 gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
	gpiodir |= BIT(offset);
	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);

	if (value)
		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
	else
		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int zx_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct zx_gpio *chip = gpiochip_get_data(gc);

	return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
}

static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct zx_gpio *chip = gpiochip_get_data(gc);

	if (value)
		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
	else
		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
}

static int zx_irq_type(struct irq_data *d, unsigned trigger)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct zx_gpio *chip = gpiochip_get_data(gc);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
	u16 bit = BIT(offset);

	if (offset < 0 || offset >= ZX_GPIO_NR)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);

	gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
	gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
	gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
	gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		gpiois |= bit;
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
	} else
		gpiois &= ~bit;

	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		gpioi_epos |= bit;
		gpioi_eneg |= bit;
	} else {
		if (trigger & IRQ_TYPE_EDGE_RISING) {
			gpioi_epos |= bit;
			gpioi_eneg &= ~bit;
		} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
			gpioi_eneg |= bit;
			gpioi_epos &= ~bit;
		}
	}

	writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
	writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
	writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
	writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static void zx_irq_handler(struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct zx_gpio *chip = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
	writew_relaxed(pending, chip->base + ZX_GPIO_IC);
	if (pending) {
		for_each_set_bit(offset, &pending, ZX_GPIO_NR)
			generic_handle_irq(irq_find_mapping(gc->irqdomain,
							    offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void zx_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct zx_gpio *chip = gpiochip_get_data(gc);
	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
	u16 gpioie;

	spin_lock(&chip->lock);
	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
	spin_unlock(&chip->lock);
}

static void zx_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct zx_gpio *chip = gpiochip_get_data(gc);
	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
	u16 gpioie;

	spin_lock(&chip->lock);
	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
	spin_unlock(&chip->lock);
}

static struct irq_chip zx_irqchip = {
	.name		= "zx-gpio",
	.irq_mask	= zx_irq_mask,
	.irq_unmask	= zx_irq_unmask,
	.irq_set_type	= zx_irq_type,
};

static int zx_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct zx_gpio *chip;
	struct resource *res;
	int irq, id, ret;

	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	chip->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(chip->base))
		return PTR_ERR(chip->base);

	spin_lock_init(&chip->lock);
	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
		chip->gc.request = gpiochip_generic_request;
		chip->gc.free = gpiochip_generic_free;
	}

	id = of_alias_get_id(dev->of_node, "gpio");
	chip->gc.direction_input = zx_direction_input;
	chip->gc.direction_output = zx_direction_output;
	chip->gc.get = zx_get_value;
	chip->gc.set = zx_set_value;
	chip->gc.base = ZX_GPIO_NR * id;
	chip->gc.ngpio = ZX_GPIO_NR;
	chip->gc.label = dev_name(dev);
	chip->gc.parent = dev;
	chip->gc.owner = THIS_MODULE;

	ret = gpiochip_add_data(&chip->gc, chip);
	if (ret)
		return ret;

	/*
	 * irq_chip support
	 */
	writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
	writew_relaxed(0, chip->base + ZX_GPIO_IE);
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "invalid IRQ\n");
		gpiochip_remove(&chip->gc);
		return -ENODEV;
	}

	ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
				   0, handle_simple_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "could not add irqchip\n");
		gpiochip_remove(&chip->gc);
		return ret;
	}
	gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
				     irq, zx_irq_handler);

	platform_set_drvdata(pdev, chip);
	dev_info(dev, "ZX GPIO chip registered\n");

	return 0;
}

static const struct of_device_id zx_gpio_match[] = {
	{
		.compatible = "zte,zx296702-gpio",
	},
	{ },
};
MODULE_DEVICE_TABLE(of, zx_gpio_match);

static struct platform_driver zx_gpio_driver = {
	.probe		= zx_gpio_probe,
	.driver = {
		.name	= "zx_gpio",
		.of_match_table = of_match_ptr(zx_gpio_match),
	},
};

module_platform_driver(zx_gpio_driver)

MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
MODULE_DESCRIPTION("ZTE ZX296702 GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
e7aa6d8c JN	1	/*
	2	* Copyright (C) 2015 Linaro Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8	#include <linux/bitops.h>
	9	#include <linux/device.h>
	10	#include <linux/errno.h>
	11	#include <linux/gpio/driver.h>
	12	#include <linux/irqchip/chained_irq.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
	15	#include <linux/pinctrl/consumer.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/pm.h>
	18	#include <linux/slab.h>
	19	#include <linux/spinlock.h>
	20
	21	#define ZX_GPIO_DIR 0x00
	22	#define ZX_GPIO_IVE 0x04
	23	#define ZX_GPIO_IV 0x08
	24	#define ZX_GPIO_IEP 0x0C
	25	#define ZX_GPIO_IEN 0x10
	26	#define ZX_GPIO_DI 0x14
	27	#define ZX_GPIO_DO1 0x18
	28	#define ZX_GPIO_DO0 0x1C
	29	#define ZX_GPIO_DO 0x20
	30
	31	#define ZX_GPIO_IM 0x28
	32	#define ZX_GPIO_IE 0x2C
	33
	34	#define ZX_GPIO_MIS 0x30
	35	#define ZX_GPIO_IC 0x34
	36
	37	#define ZX_GPIO_NR 16
	38
	39	struct zx_gpio {
	40	spinlock_t lock;
	41
	42	void __iomem *base;
	43	struct gpio_chip gc;
e7aa6d8c JN	44	};
e7aa6d8c JN	45
e7aa6d8c JN	46	static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
e7aa6d8c JN	47	{
17758b04	48	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	49	unsigned long flags;
	50	u16 gpiodir;
	51
	52	if (offset >= gc->ngpio)
	53	return -EINVAL;
	54
	55	spin_lock_irqsave(&chip->lock, flags);
	56	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
	57	gpiodir &= ~BIT(offset);
	58	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
	59	spin_unlock_irqrestore(&chip->lock, flags);
	60
	61	return 0;
	62	}
	63
	64	static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
	65	int value)
	66	{
17758b04	67	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	68	unsigned long flags;
	69	u16 gpiodir;
	70
	71	if (offset >= gc->ngpio)
	72	return -EINVAL;
	73
	74	spin_lock_irqsave(&chip->lock, flags);
	75	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
	76	gpiodir \|= BIT(offset);
	77	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
	78
	79	if (value)
	80	writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
	81	else
	82	writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
	83	spin_unlock_irqrestore(&chip->lock, flags);
	84
	85	return 0;
	86	}
	87
	88	static int zx_get_value(struct gpio_chip *gc, unsigned offset)
	89	{
17758b04	90	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	91
	92	return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
	93	}
	94
	95	static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
	96	{
17758b04	97	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	98
	99	if (value)
	100	writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
	101	else
	102	writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
	103	}
	104
	105	static int zx_irq_type(struct irq_data *d, unsigned trigger)
	106	{
	107	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
17758b04	108	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	109	int offset = irqd_to_hwirq(d);
	110	unsigned long flags;
	111	u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
	112	u16 bit = BIT(offset);
	113
	114	if (offset < 0 \|\| offset >= ZX_GPIO_NR)
	115	return -EINVAL;
	116
	117	spin_lock_irqsave(&chip->lock, flags);
	118
	119	gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
	120	gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
	121	gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
	122	gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
	123
	124	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
	125	gpiois \|= bit;
	126	if (trigger & IRQ_TYPE_LEVEL_HIGH)
	127	gpioiev \|= bit;
	128	else
	129	gpioiev &= ~bit;
	130	} else
	131	gpiois &= ~bit;
	132
	133	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
	134	gpioi_epos \|= bit;
	135	gpioi_eneg \|= bit;
	136	} else {
	137	if (trigger & IRQ_TYPE_EDGE_RISING) {
	138	gpioi_epos \|= bit;
	139	gpioi_eneg &= ~bit;
	140	} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
	141	gpioi_eneg \|= bit;
	142	gpioi_epos &= ~bit;
	143	}
	144	}
	145
	146	writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
	147	writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
	148	writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
	149	writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
	150	spin_unlock_irqrestore(&chip->lock, flags);
	151
	152	return 0;
	153	}
	154
bd0b9ac4	155	static void zx_irq_handler(struct irq_desc *desc)
e7aa6d8c JN	156	{
	157	unsigned long pending;
	158	int offset;
	159	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
17758b04	160	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	161	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	162
	163	chained_irq_enter(irqchip, desc);
	164
	165	pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
	166	writew_relaxed(pending, chip->base + ZX_GPIO_IC);
	167	if (pending) {
	168	for_each_set_bit(offset, &pending, ZX_GPIO_NR)
	169	generic_handle_irq(irq_find_mapping(gc->irqdomain,
	170	offset));
	171	}
	172
	173	chained_irq_exit(irqchip, desc);
	174	}
	175
	176	static void zx_irq_mask(struct irq_data *d)
	177	{
	178	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
17758b04	179	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	180	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
	181	u16 gpioie;
	182
	183	spin_lock(&chip->lock);
	184	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) \| mask;
	185	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
	186	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
	187	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
	188	spin_unlock(&chip->lock);
	189	}
	190
	191	static void zx_irq_unmask(struct irq_data *d)
	192	{
	193	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
17758b04	194	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	195	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
	196	u16 gpioie;
	197
	198	spin_lock(&chip->lock);
	199	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
	200	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
	201	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) \| mask;
	202	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
	203	spin_unlock(&chip->lock);
	204	}
	205
	206	static struct irq_chip zx_irqchip = {
	207	.name = "zx-gpio",
	208	.irq_mask = zx_irq_mask,
	209	.irq_unmask = zx_irq_unmask,
	210	.irq_set_type = zx_irq_type,
	211	};
	212
	213	static int zx_gpio_probe(struct platform_device *pdev)
	214	{
	215	struct device *dev = &pdev->dev;
	216	struct zx_gpio *chip;
	217	struct resource *res;
	218	int irq, id, ret;
	219
	220	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	221	if (!chip)
	222	return -ENOMEM;
	223
	224	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	225	chip->base = devm_ioremap_resource(dev, res);
	226	if (IS_ERR(chip->base))
	227	return PTR_ERR(chip->base);
	228
	229	spin_lock_init(&chip->lock);
da4002ee JG	230	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
	231	chip->gc.request = gpiochip_generic_request;
	232	chip->gc.free = gpiochip_generic_free;
	233	}
e7aa6d8c JN	234
e7aa6d8c JN	235	id = of_alias_get_id(dev->of_node, "gpio");
e7aa6d8c JN	236	chip->gc.direction_input = zx_direction_input;
	237	chip->gc.direction_output = zx_direction_output;
	238	chip->gc.get = zx_get_value;
	239	chip->gc.set = zx_set_value;
	240	chip->gc.base = ZX_GPIO_NR * id;
	241	chip->gc.ngpio = ZX_GPIO_NR;
	242	chip->gc.label = dev_name(dev);
58383c78	243	chip->gc.parent = dev;
e7aa6d8c JN	244	chip->gc.owner = THIS_MODULE;
e7aa6d8c JN	245
17758b04	246	ret = gpiochip_add_data(&chip->gc, chip);
e7aa6d8c JN	247	if (ret)
	248	return ret;
	249
	250	/*
	251	* irq_chip support
	252	*/
	253	writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
	254	writew_relaxed(0, chip->base + ZX_GPIO_IE);
	255	irq = platform_get_irq(pdev, 0);
	256	if (irq < 0) {
	257	dev_err(dev, "invalid IRQ\n");
	258	gpiochip_remove(&chip->gc);
	259	return -ENODEV;
	260	}
	261
	262	ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
	263	0, handle_simple_irq,
	264	IRQ_TYPE_NONE);
	265	if (ret) {
	266	dev_err(dev, "could not add irqchip\n");
	267	gpiochip_remove(&chip->gc);
	268	return ret;
	269	}
	270	gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
	271	irq, zx_irq_handler);
	272
	273	platform_set_drvdata(pdev, chip);
	274	dev_info(dev, "ZX GPIO chip registered\n");
	275
	276	return 0;
	277	}
	278
	279	static const struct of_device_id zx_gpio_match[] = {
	280	{
	281	.compatible = "zte,zx296702-gpio",
	282	},
	283	{ },
	284	};
	285	MODULE_DEVICE_TABLE(of, zx_gpio_match);
	286
	287	static struct platform_driver zx_gpio_driver = {
	288	.probe = zx_gpio_probe,
	289	.driver = {
	290	.name = "zx_gpio",
	291	.of_match_table = of_match_ptr(zx_gpio_match),
	292	},
	293	};
	294
	295	module_platform_driver(zx_gpio_driver)
	296
	297	MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
	298	MODULE_DESCRIPTION("ZTE ZX296702 GPIO driver");
	299	MODULE_LICENSE("GPL");