[linux-2.6-block.git] / drivers / gpio / gpio-xgene.c

/*
 * AppliedMicro X-Gene SoC GPIO Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Author: Feng Kan <fkan@apm.com>.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/types.h>
#include <linux/bitops.h>

#define GPIO_SET_DR_OFFSET	0x0C
#define GPIO_DATA_OFFSET	0x14
#define GPIO_BANK_STRIDE	0x0C

#define XGENE_GPIOS_PER_BANK	16
#define XGENE_MAX_GPIO_BANKS	3
#define XGENE_MAX_GPIOS		(XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)

#define GPIO_BIT_OFFSET(x)	(x % XGENE_GPIOS_PER_BANK)
#define GPIO_BANK_OFFSET(x)	((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)

struct xgene_gpio {
	struct gpio_chip	chip;
	void __iomem		*base;
	spinlock_t		lock;
#ifdef CONFIG_PM
	u32			set_dr_val[XGENE_MAX_GPIO_BANKS];
#endif
};

static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long bank_offset;
	u32 bit_offset;

	bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
	bit_offset = GPIO_BIT_OFFSET(offset);
	return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
}

static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long bank_offset;
	u32 setval, bit_offset;

	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;

	setval = ioread32(chip->base + bank_offset);
	if (val)
		setval |= BIT(bit_offset);
	else
		setval &= ~BIT(bit_offset);
	iowrite32(setval, chip->base + bank_offset);
}

static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&chip->lock, flags);
	__xgene_gpio_set(gc, offset, val);
	spin_unlock_irqrestore(&chip->lock, flags);
}

static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags, bank_offset;
	u32 dirval, bit_offset;

	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	bit_offset = GPIO_BIT_OFFSET(offset);

	spin_lock_irqsave(&chip->lock, flags);

	dirval = ioread32(chip->base + bank_offset);
	dirval |= BIT(bit_offset);
	iowrite32(dirval, chip->base + bank_offset);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int xgene_gpio_dir_out(struct gpio_chip *gc,
					unsigned int offset, int val)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags, bank_offset;
	u32 dirval, bit_offset;

	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	bit_offset = GPIO_BIT_OFFSET(offset);

	spin_lock_irqsave(&chip->lock, flags);

	dirval = ioread32(chip->base + bank_offset);
	dirval &= ~BIT(bit_offset);
	iowrite32(dirval, chip->base + bank_offset);
	__xgene_gpio_set(gc, offset, val);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

#ifdef CONFIG_PM
static int xgene_gpio_suspend(struct device *dev)
{
	struct xgene_gpio *gpio = dev_get_drvdata(dev);
	unsigned long bank_offset;
	unsigned int bank;

	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
		bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
		gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
	}
	return 0;
}

static int xgene_gpio_resume(struct device *dev)
{
	struct xgene_gpio *gpio = dev_get_drvdata(dev);
	unsigned long bank_offset;
	unsigned int bank;

	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
		bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
		iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
	}
	return 0;
}

static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
#define XGENE_GPIO_PM_OPS	(&xgene_gpio_pm)
#else
#define XGENE_GPIO_PM_OPS	NULL
#endif

static int xgene_gpio_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct xgene_gpio *gpio;
	int err = 0;

	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	if (!gpio) {
		err = -ENOMEM;
		goto err;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	gpio->base = devm_ioremap_nocache(&pdev->dev, res->start,
							resource_size(res));
	if (!gpio->base) {
		err = -ENOMEM;
		goto err;
	}

	gpio->chip.ngpio = XGENE_MAX_GPIOS;

	spin_lock_init(&gpio->lock);
	gpio->chip.parent = &pdev->dev;
	gpio->chip.direction_input = xgene_gpio_dir_in;
	gpio->chip.direction_output = xgene_gpio_dir_out;
	gpio->chip.get = xgene_gpio_get;
	gpio->chip.set = xgene_gpio_set;
	gpio->chip.label = dev_name(&pdev->dev);
	gpio->chip.base = -1;

	platform_set_drvdata(pdev, gpio);

	err = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
	if (err) {
		dev_err(&pdev->dev,
			"failed to register gpiochip.\n");
		goto err;
	}

	dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n");
	return 0;
err:
	dev_err(&pdev->dev, "X-Gene GPIO driver registration failed.\n");
	return err;
}

static const struct of_device_id xgene_gpio_of_match[] = {
	{ .compatible = "apm,xgene-gpio", },
	{},
};
MODULE_DEVICE_TABLE(of, xgene_gpio_of_match);

static struct platform_driver xgene_gpio_driver = {
	.driver = {
		.name = "xgene-gpio",
		.of_match_table = xgene_gpio_of_match,
		.pm     = XGENE_GPIO_PM_OPS,
	},
	.probe = xgene_gpio_probe,
};

module_platform_driver(xgene_gpio_driver);

MODULE_AUTHOR("Feng Kan <fkan@apm.com>");
MODULE_DESCRIPTION("APM X-Gene GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
29cbf458 FK	1	/*
	2	* AppliedMicro X-Gene SoC GPIO Driver
	3	*
	4	* Copyright (c) 2014, Applied Micro Circuits Corporation
	5	* Author: Feng Kan <fkan@apm.com>.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/module.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/io.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/gpio/driver.h>
	27	#include <linux/types.h>
	28	#include <linux/bitops.h>
	29
	30	#define GPIO_SET_DR_OFFSET 0x0C
	31	#define GPIO_DATA_OFFSET 0x14
	32	#define GPIO_BANK_STRIDE 0x0C
	33
	34	#define XGENE_GPIOS_PER_BANK 16
	35	#define XGENE_MAX_GPIO_BANKS 3
	36	#define XGENE_MAX_GPIOS (XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)
	37
	38	#define GPIO_BIT_OFFSET(x) (x % XGENE_GPIOS_PER_BANK)
	39	#define GPIO_BANK_OFFSET(x) ((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)
	40
29cbf458 FK	41	struct xgene_gpio {
	42	struct gpio_chip chip;
	43	void __iomem *base;
	44	spinlock_t lock;
	45	#ifdef CONFIG_PM
	46	u32 set_dr_val[XGENE_MAX_GPIO_BANKS];
	47	#endif
	48	};
	49
29cbf458 FK	50	static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
29cbf458 FK	51	{
ac9dc85e	52	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	53	unsigned long bank_offset;
	54	u32 bit_offset;
	55
	56	bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
	57	bit_offset = GPIO_BIT_OFFSET(offset);
	58	return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
	59	}
	60
	61	static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
	62	{
ac9dc85e	63	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	64	unsigned long bank_offset;
	65	u32 setval, bit_offset;
	66
	67	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	68	bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;
	69
	70	setval = ioread32(chip->base + bank_offset);
	71	if (val)
	72	setval \|= BIT(bit_offset);
	73	else
	74	setval &= ~BIT(bit_offset);
	75	iowrite32(setval, chip->base + bank_offset);
	76	}
	77
	78	static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
	79	{
ac9dc85e	80	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	81	unsigned long flags;
	82
	83	spin_lock_irqsave(&chip->lock, flags);
	84	__xgene_gpio_set(gc, offset, val);
	85	spin_unlock_irqrestore(&chip->lock, flags);
	86	}
	87
	88	static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
	89	{
ac9dc85e	90	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	91	unsigned long flags, bank_offset;
	92	u32 dirval, bit_offset;
	93
	94	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	95	bit_offset = GPIO_BIT_OFFSET(offset);
	96
	97	spin_lock_irqsave(&chip->lock, flags);
	98
	99	dirval = ioread32(chip->base + bank_offset);
	100	dirval \|= BIT(bit_offset);
	101	iowrite32(dirval, chip->base + bank_offset);
	102
	103	spin_unlock_irqrestore(&chip->lock, flags);
	104
	105	return 0;
	106	}
	107
	108	static int xgene_gpio_dir_out(struct gpio_chip *gc,
	109	unsigned int offset, int val)
	110	{
ac9dc85e	111	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	112	unsigned long flags, bank_offset;
	113	u32 dirval, bit_offset;
	114
	115	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	116	bit_offset = GPIO_BIT_OFFSET(offset);
	117
	118	spin_lock_irqsave(&chip->lock, flags);
	119
	120	dirval = ioread32(chip->base + bank_offset);
	121	dirval &= ~BIT(bit_offset);
	122	iowrite32(dirval, chip->base + bank_offset);
	123	__xgene_gpio_set(gc, offset, val);
	124
	125	spin_unlock_irqrestore(&chip->lock, flags);
	126
	127	return 0;
	128	}
	129
	130	#ifdef CONFIG_PM
	131	static int xgene_gpio_suspend(struct device *dev)
	132	{
	133	struct xgene_gpio *gpio = dev_get_drvdata(dev);
	134	unsigned long bank_offset;
	135	unsigned int bank;
	136
	137	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
	138	bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
	139	gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
	140	}
	141	return 0;
	142	}
	143
	144	static int xgene_gpio_resume(struct device *dev)
	145	{
	146	struct xgene_gpio *gpio = dev_get_drvdata(dev);
	147	unsigned long bank_offset;
	148	unsigned int bank;
	149
	150	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
	151	bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
	152	iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
	153	}
	154	return 0;
	155	}
	156
	157	static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
	158	#define XGENE_GPIO_PM_OPS (&xgene_gpio_pm)
	159	#else
	160	#define XGENE_GPIO_PM_OPS NULL
	161	#endif
	162
	163	static int xgene_gpio_probe(struct platform_device *pdev)
	164	{
	165	struct resource *res;
	166	struct xgene_gpio *gpio;
	167	int err = 0;
	168
	169	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	170	if (!gpio) {
	171	err = -ENOMEM;
	172	goto err;
	173	}
	174
	175	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
176	gpio->base = devm_ioremap_nocache(&pdev->dev, res->start,
177	resource_size(res));
4f51b913 WY	178	if (!gpio->base) {
4f51b913 WY	179	err = -ENOMEM;
29cbf458 FK	180	goto err;
	181	}
	182
	183	gpio->chip.ngpio = XGENE_MAX_GPIOS;
	184
1a19864e	185	spin_lock_init(&gpio->lock);
58383c78	186	gpio->chip.parent = &pdev->dev;
29cbf458 FK	187	gpio->chip.direction_input = xgene_gpio_dir_in;
	188	gpio->chip.direction_output = xgene_gpio_dir_out;
	189	gpio->chip.get = xgene_gpio_get;
	190	gpio->chip.set = xgene_gpio_set;
	191	gpio->chip.label = dev_name(&pdev->dev);
	192	gpio->chip.base = -1;
	193
	194	platform_set_drvdata(pdev, gpio);
	195
9d113c69	196	err = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
29cbf458 FK	197	if (err) {
	198	dev_err(&pdev->dev,
	199	"failed to register gpiochip.\n");
	200	goto err;
	201	}
	202
	203	dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n");
	204	return 0;
	205	err:
	206	dev_err(&pdev->dev, "X-Gene GPIO driver registration failed.\n");
	207	return err;
	208	}
	209
29cbf458 FK	210	static const struct of_device_id xgene_gpio_of_match[] = {
	211	{ .compatible = "apm,xgene-gpio", },
	212	{},
	213	};
	214	MODULE_DEVICE_TABLE(of, xgene_gpio_of_match);
29cbf458 FK	215
	216	static struct platform_driver xgene_gpio_driver = {
	217	.driver = {
	218	.name = "xgene-gpio",
29cbf458 FK	219	.of_match_table = xgene_gpio_of_match,
	220	.pm = XGENE_GPIO_PM_OPS,
	221	},
	222	.probe = xgene_gpio_probe,
29cbf458 FK	223	};
	224
	225	module_platform_driver(xgene_gpio_driver);
	226
	227	MODULE_AUTHOR("Feng Kan <fkan@apm.com>");
	228	MODULE_DESCRIPTION("APM X-Gene GPIO driver");
	229	MODULE_LICENSE("GPL");