[linux-2.6-block.git] / drivers / gpio / gpio-ws16c48.c

/*
 * GPIO driver for the WinSystems WS16C48
 * Copyright (C) 2016 William Breathitt Gray
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */
#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irqdesc.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>

#define WS16C48_EXTENT 16
#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)

static unsigned int base[MAX_NUM_WS16C48];
static unsigned int num_ws16c48;
module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");

static unsigned int irq[MAX_NUM_WS16C48];
module_param_hw_array(irq, uint, irq, NULL, 0);
MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");

/**
 * struct ws16c48_gpio - GPIO device private data structure
 * @chip:	instance of the gpio_chip
 * @io_state:	bit I/O state (whether bit is set to input or output)
 * @out_state:	output bits state
 * @lock:	synchronization lock to prevent I/O race conditions
 * @irq_mask:	I/O bits affected by interrupts
 * @flow_mask:	IRQ flow type mask for the respective I/O bits
 * @base:	base port address of the GPIO device
 */
struct ws16c48_gpio {
	struct gpio_chip chip;
	unsigned char io_state[6];
	unsigned char out_state[6];
	raw_spinlock_t lock;
	unsigned long irq_mask;
	unsigned long flow_mask;
	unsigned base;
};

static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);

	return !!(ws16c48gpio->io_state[port] & mask);
}

static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->io_state[port] |= mask;
	ws16c48gpio->out_state[port] &= ~mask;
	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return 0;
}

static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
	unsigned offset, int value)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->io_state[port] &= ~mask;
	if (value)
		ws16c48gpio->out_state[port] |= mask;
	else
		ws16c48gpio->out_state[port] &= ~mask;
	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return 0;
}

static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;
	unsigned port_state;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	/* ensure that GPIO is set for input */
	if (!(ws16c48gpio->io_state[port] & mask)) {
		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
		return -EINVAL;
	}

	port_state = inb(ws16c48gpio->base + port);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return !!(port_state & mask);
}

static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned int gpio_reg_size = 8;
	size_t i;
	const size_t num_ports = chip->ngpio / gpio_reg_size;
	unsigned int bits_offset;
	size_t word_index;
	unsigned int word_offset;
	unsigned long word_mask;
	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
	unsigned long port_state;

	/* clear bits array to a clean slate */
	bitmap_zero(bits, chip->ngpio);

	/* get bits are evaluated a gpio port register at a time */
	for (i = 0; i < num_ports; i++) {
		/* gpio offset in bits array */
		bits_offset = i * gpio_reg_size;

		/* word index for bits array */
		word_index = BIT_WORD(bits_offset);

		/* gpio offset within current word of bits array */
		word_offset = bits_offset % BITS_PER_LONG;

		/* mask of get bits for current gpio within current word */
		word_mask = mask[word_index] & (port_mask << word_offset);
		if (!word_mask) {
			/* no get bits in this port so skip to next one */
			continue;
		}

		/* read bits from current gpio port */
		port_state = inb(ws16c48gpio->base + i);

		/* store acquired bits at respective bits array offset */
		bits[word_index] |= (port_state << word_offset) & word_mask;
	}

	return 0;
}

static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	/* ensure that GPIO is set for output */
	if (ws16c48gpio->io_state[port] & mask) {
		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
		return;
	}

	if (value)
		ws16c48gpio->out_state[port] |= mask;
	else
		ws16c48gpio->out_state[port] &= ~mask;
	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	unsigned int i;
	const unsigned int gpio_reg_size = 8;
	unsigned int port;
	unsigned int iomask;
	unsigned int bitmask;
	unsigned long flags;

	/* set bits are evaluated a gpio register size at a time */
	for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
		/* no more set bits in this mask word; skip to the next word */
		if (!mask[BIT_WORD(i)]) {
			i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
			continue;
		}

		port = i / gpio_reg_size;

		/* mask out GPIO configured for input */
		iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port];
		bitmask = iomask & bits[BIT_WORD(i)];

		raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

		/* update output state data and set device gpio register */
		ws16c48gpio->out_state[port] &= ~iomask;
		ws16c48gpio->out_state[port] |= bitmask;
		outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);

		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

		/* prepare for next gpio register set */
		mask[BIT_WORD(i)] >>= gpio_reg_size;
		bits[BIT_WORD(i)] >>= gpio_reg_size;
	}
}

static void ws16c48_irq_ack(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;
	unsigned port_state;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	port_state = ws16c48gpio->irq_mask >> (8*port);

	outb(0x80, ws16c48gpio->base + 7);
	outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
	outb(port_state | mask, ws16c48gpio->base + 8 + port);
	outb(0xC0, ws16c48gpio->base + 7);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static void ws16c48_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned long mask = BIT(offset);
	const unsigned port = offset / 8;
	unsigned long flags;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->irq_mask &= ~mask;

	outb(0x80, ws16c48gpio->base + 7);
	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
	outb(0xC0, ws16c48gpio->base + 7);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static void ws16c48_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned long mask = BIT(offset);
	const unsigned port = offset / 8;
	unsigned long flags;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->irq_mask |= mask;

	outb(0x80, ws16c48gpio->base + 7);
	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
	outb(0xC0, ws16c48gpio->base + 7);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned long mask = BIT(offset);
	const unsigned port = offset / 8;
	unsigned long flags;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return -EINVAL;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	switch (flow_type) {
	case IRQ_TYPE_NONE:
		break;
	case IRQ_TYPE_EDGE_RISING:
		ws16c48gpio->flow_mask |= mask;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		ws16c48gpio->flow_mask &= ~mask;
		break;
	default:
		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
		return -EINVAL;
	}

	outb(0x40, ws16c48gpio->base + 7);
	outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
	outb(0xC0, ws16c48gpio->base + 7);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return 0;
}

static struct irq_chip ws16c48_irqchip = {
	.name = "ws16c48",
	.irq_ack = ws16c48_irq_ack,
	.irq_mask = ws16c48_irq_mask,
	.irq_unmask = ws16c48_irq_unmask,
	.irq_set_type = ws16c48_irq_set_type
};

static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
{
	struct ws16c48_gpio *const ws16c48gpio = dev_id;
	struct gpio_chip *const chip = &ws16c48gpio->chip;
	unsigned long int_pending;
	unsigned long port;
	unsigned long int_id;
	unsigned long gpio;

	int_pending = inb(ws16c48gpio->base + 6) & 0x7;
	if (!int_pending)
		return IRQ_NONE;

	/* loop until all pending interrupts are handled */
	do {
		for_each_set_bit(port, &int_pending, 3) {
			int_id = inb(ws16c48gpio->base + 8 + port);
			for_each_set_bit(gpio, &int_id, 8)
				generic_handle_irq(irq_find_mapping(
					chip->irq.domain, gpio + 8*port));
		}

		int_pending = inb(ws16c48gpio->base + 6) & 0x7;
	} while (int_pending);

	return IRQ_HANDLED;
}

#define WS16C48_NGPIO 48
static const char *ws16c48_names[WS16C48_NGPIO] = {
	"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
	"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
	"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
	"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
	"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
	"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
	"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
	"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
	"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
	"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
	"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
	"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
};

static int ws16c48_probe(struct device *dev, unsigned int id)
{
	struct ws16c48_gpio *ws16c48gpio;
	const char *const name = dev_name(dev);
	int err;

	ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
	if (!ws16c48gpio)
		return -ENOMEM;

	if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
			base[id], base[id] + WS16C48_EXTENT);
		return -EBUSY;
	}

	ws16c48gpio->chip.label = name;
	ws16c48gpio->chip.parent = dev;
	ws16c48gpio->chip.owner = THIS_MODULE;
	ws16c48gpio->chip.base = -1;
	ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
	ws16c48gpio->chip.names = ws16c48_names;
	ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
	ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
	ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
	ws16c48gpio->chip.get = ws16c48_gpio_get;
	ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
	ws16c48gpio->chip.set = ws16c48_gpio_set;
	ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
	ws16c48gpio->base = base[id];

	raw_spin_lock_init(&ws16c48gpio->lock);

	err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
	if (err) {
		dev_err(dev, "GPIO registering failed (%d)\n", err);
		return err;
	}

	/* Disable IRQ by default */
	outb(0x80, base[id] + 7);
	outb(0, base[id] + 8);
	outb(0, base[id] + 9);
	outb(0, base[id] + 10);
	outb(0xC0, base[id] + 7);

	err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
		handle_edge_irq, IRQ_TYPE_NONE);
	if (err) {
		dev_err(dev, "Could not add irqchip (%d)\n", err);
		return err;
	}

	err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
		name, ws16c48gpio);
	if (err) {
		dev_err(dev, "IRQ handler registering failed (%d)\n", err);
		return err;
	}

	return 0;
}

static struct isa_driver ws16c48_driver = {
	.probe = ws16c48_probe,
	.driver = {
		.name = "ws16c48"
	},
};

module_isa_driver(ws16c48_driver, num_ws16c48);

MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9c26df9b WBG	1	/*
	2	* GPIO driver for the WinSystems WS16C48
	3	* Copyright (C) 2016 William Breathitt Gray
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License, version 2, as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but
	10	* WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	12	* General Public License for more details.
	13	*/
a8ff510d	14	#include <linux/bitmap.h>
9c26df9b WBG	15	#include <linux/bitops.h>
	16	#include <linux/device.h>
	17	#include <linux/errno.h>
	18	#include <linux/gpio/driver.h>
	19	#include <linux/io.h>
	20	#include <linux/ioport.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/irqdesc.h>
cc736607	23	#include <linux/isa.h>
9c26df9b WBG	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/moduleparam.h>
9c26df9b WBG	27	#include <linux/spinlock.h>
9c26df9b WBG	28
cc736607 WBG	29	#define WS16C48_EXTENT 16
	30	#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
	31
	32	static unsigned int base[MAX_NUM_WS16C48];
	33	static unsigned int num_ws16c48;
d759f906	34	module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
cc736607 WBG	35	MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
	36
	37	static unsigned int irq[MAX_NUM_WS16C48];
d759f906	38	module_param_hw_array(irq, uint, irq, NULL, 0);
cc736607	39	MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
9c26df9b WBG	40
	41	/**
	42	* struct ws16c48_gpio - GPIO device private data structure
	43	* @chip: instance of the gpio_chip
	44	* @io_state: bit I/O state (whether bit is set to input or output)
	45	* @out_state: output bits state
	46	* @lock: synchronization lock to prevent I/O race conditions
	47	* @irq_mask: I/O bits affected by interrupts
	48	* @flow_mask: IRQ flow type mask for the respective I/O bits
	49	* @base: base port address of the GPIO device
9c26df9b WBG	50	*/
	51	struct ws16c48_gpio {
	52	struct gpio_chip chip;
	53	unsigned char io_state[6];
	54	unsigned char out_state[6];
a0a584f0	55	raw_spinlock_t lock;
9c26df9b WBG	56	unsigned long irq_mask;
	57	unsigned long flow_mask;
	58	unsigned base;
9c26df9b WBG	59	};
	60
	61	static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
	62	{
	63	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	64	const unsigned port = offset / 8;
	65	const unsigned mask = BIT(offset % 8);
	66
	67	return !!(ws16c48gpio->io_state[port] & mask);
	68	}
	69
	70	static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	71	{
	72	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	73	const unsigned port = offset / 8;
	74	const unsigned mask = BIT(offset % 8);
	75	unsigned long flags;
	76
a0a584f0	77	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	78
	79	ws16c48gpio->io_state[port] \|= mask;
	80	ws16c48gpio->out_state[port] &= ~mask;
	81	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
	82
a0a584f0	83	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	84
	85	return 0;
	86	}
	87
	88	static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
	89	unsigned offset, int value)
	90	{
	91	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	92	const unsigned port = offset / 8;
	93	const unsigned mask = BIT(offset % 8);
	94	unsigned long flags;
	95
a0a584f0	96	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	97
	98	ws16c48gpio->io_state[port] &= ~mask;
	99	if (value)
	100	ws16c48gpio->out_state[port] \|= mask;
	101	else
	102	ws16c48gpio->out_state[port] &= ~mask;
	103	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
	104
a0a584f0	105	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	106
	107	return 0;
	108	}
	109
	110	static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
	111	{
	112	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	113	const unsigned port = offset / 8;
	114	const unsigned mask = BIT(offset % 8);
	115	unsigned long flags;
	116	unsigned port_state;
	117
a0a584f0	118	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	119
	120	/* ensure that GPIO is set for input */
	121	if (!(ws16c48gpio->io_state[port] & mask)) {
a0a584f0	122	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	123	return -EINVAL;
	124	}
	125
	126	port_state = inb(ws16c48gpio->base + port);
	127
a0a584f0	128	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	129
	130	return !!(port_state & mask);
	131	}
	132
a8ff510d WBG	133	static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
	134	unsigned long mask, unsigned long bits)
	135	{
	136	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	137	const unsigned int gpio_reg_size = 8;
	138	size_t i;
	139	const size_t num_ports = chip->ngpio / gpio_reg_size;
	140	unsigned int bits_offset;
	141	size_t word_index;
	142	unsigned int word_offset;
	143	unsigned long word_mask;
	144	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
	145	unsigned long port_state;
	146
	147	/* clear bits array to a clean slate */
	148	bitmap_zero(bits, chip->ngpio);
	149
	150	/* get bits are evaluated a gpio port register at a time */
	151	for (i = 0; i < num_ports; i++) {
	152	/* gpio offset in bits array */
	153	bits_offset = i * gpio_reg_size;
	154
	155	/* word index for bits array */
	156	word_index = BIT_WORD(bits_offset);
	157
	158	/* gpio offset within current word of bits array */
	159	word_offset = bits_offset % BITS_PER_LONG;
	160
	161	/* mask of get bits for current gpio within current word */
	162	word_mask = mask[word_index] & (port_mask << word_offset);
	163	if (!word_mask) {
	164	/* no get bits in this port so skip to next one */
	165	continue;
	166	}
	167
	168	/* read bits from current gpio port */
	169	port_state = inb(ws16c48gpio->base + i);
	170
	171	/* store acquired bits at respective bits array offset */
7a702691	172	bits[word_index] \|= (port_state << word_offset) & word_mask;
a8ff510d WBG	173	}
	174
	175	return 0;
	176	}
	177
9c26df9b WBG	178	static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	179	{
	180	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	181	const unsigned port = offset / 8;
	182	const unsigned mask = BIT(offset % 8);
	183	unsigned long flags;
	184
a0a584f0	185	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	186
	187	/* ensure that GPIO is set for output */
	188	if (ws16c48gpio->io_state[port] & mask) {
a0a584f0	189	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	190	return;
	191	}
	192
	193	if (value)
	194	ws16c48gpio->out_state[port] \|= mask;
	195	else
	196	ws16c48gpio->out_state[port] &= ~mask;
	197	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
	198
a0a584f0	199	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	200	}
9c26df9b WBG	201
99c8ac95 WBG	202	static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
	203	unsigned long mask, unsigned long bits)
	204	{
	205	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	206	unsigned int i;
	207	const unsigned int gpio_reg_size = 8;
	208	unsigned int port;
	209	unsigned int iomask;
	210	unsigned int bitmask;
	211	unsigned long flags;
	212
	213	/* set bits are evaluated a gpio register size at a time */
	214	for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
	215	/* no more set bits in this mask word; skip to the next word */
	216	if (!mask[BIT_WORD(i)]) {
	217	i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
	218	continue;
	219	}
	220
	221	port = i / gpio_reg_size;
	222
	223	/* mask out GPIO configured for input */
	224	iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port];
	225	bitmask = iomask & bits[BIT_WORD(i)];
	226
a0a584f0	227	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
99c8ac95 WBG	228
	229	/* update output state data and set device gpio register */
	230	ws16c48gpio->out_state[port] &= ~iomask;
	231	ws16c48gpio->out_state[port] \|= bitmask;
	232	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
	233
a0a584f0	234	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
99c8ac95 WBG	235
	236	/* prepare for next gpio register set */
	237	mask[BIT_WORD(i)] >>= gpio_reg_size;
	238	bits[BIT_WORD(i)] >>= gpio_reg_size;
	239	}
	240	}
	241
9c26df9b WBG	242	static void ws16c48_irq_ack(struct irq_data *data)
	243	{
	244	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	245	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	246	const unsigned long offset = irqd_to_hwirq(data);
	247	const unsigned port = offset / 8;
	248	const unsigned mask = BIT(offset % 8);
	249	unsigned long flags;
	250	unsigned port_state;
	251
	252	/* only the first 3 ports support interrupts */
	253	if (port > 2)
	254	return;
	255
a0a584f0	256	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	257
	258	port_state = ws16c48gpio->irq_mask >> (8*port);
	259
	260	outb(0x80, ws16c48gpio->base + 7);
	261	outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
	262	outb(port_state \| mask, ws16c48gpio->base + 8 + port);
	263	outb(0xC0, ws16c48gpio->base + 7);
	264
a0a584f0	265	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	266	}
	267
	268	static void ws16c48_irq_mask(struct irq_data *data)
	269	{
	270	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	271	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	272	const unsigned long offset = irqd_to_hwirq(data);
	273	const unsigned long mask = BIT(offset);
	274	const unsigned port = offset / 8;
	275	unsigned long flags;
	276
	277	/* only the first 3 ports support interrupts */
	278	if (port > 2)
	279	return;
	280
a0a584f0	281	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	282
	283	ws16c48gpio->irq_mask &= ~mask;
	284
	285	outb(0x80, ws16c48gpio->base + 7);
	286	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
	287	outb(0xC0, ws16c48gpio->base + 7);
	288
a0a584f0	289	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	290	}
	291
	292	static void ws16c48_irq_unmask(struct irq_data *data)
	293	{
	294	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	295	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	296	const unsigned long offset = irqd_to_hwirq(data);
	297	const unsigned long mask = BIT(offset);
	298	const unsigned port = offset / 8;
	299	unsigned long flags;
	300
	301	/* only the first 3 ports support interrupts */
	302	if (port > 2)
	303	return;
	304
a0a584f0	305	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	306
	307	ws16c48gpio->irq_mask \|= mask;
	308
	309	outb(0x80, ws16c48gpio->base + 7);
	310	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
	311	outb(0xC0, ws16c48gpio->base + 7);
	312
a0a584f0	313	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	314	}
	315
	316	static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
	317	{
	318	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	319	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	320	const unsigned long offset = irqd_to_hwirq(data);
	321	const unsigned long mask = BIT(offset);
	322	const unsigned port = offset / 8;
	323	unsigned long flags;
	324
	325	/* only the first 3 ports support interrupts */
	326	if (port > 2)
	327	return -EINVAL;
	328
a0a584f0	329	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	330
	331	switch (flow_type) {
	332	case IRQ_TYPE_NONE:
	333	break;
	334	case IRQ_TYPE_EDGE_RISING:
	335	ws16c48gpio->flow_mask \|= mask;
	336	break;
	337	case IRQ_TYPE_EDGE_FALLING:
	338	ws16c48gpio->flow_mask &= ~mask;
	339	break;
	340	default:
a0a584f0	341	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	342	return -EINVAL;
	343	}
	344
	345	outb(0x40, ws16c48gpio->base + 7);
	346	outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
	347	outb(0xC0, ws16c48gpio->base + 7);
	348
a0a584f0	349	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	350
	351	return 0;
	352	}
	353
	354	static struct irq_chip ws16c48_irqchip = {
	355	.name = "ws16c48",
	356	.irq_ack = ws16c48_irq_ack,
	357	.irq_mask = ws16c48_irq_mask,
	358	.irq_unmask = ws16c48_irq_unmask,
	359	.irq_set_type = ws16c48_irq_set_type
	360	};
	361
	362	static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
	363	{
	364	struct ws16c48_gpio *const ws16c48gpio = dev_id;
	365	struct gpio_chip *const chip = &ws16c48gpio->chip;
	366	unsigned long int_pending;
	367	unsigned long port;
	368	unsigned long int_id;
	369	unsigned long gpio;
	370
	371	int_pending = inb(ws16c48gpio->base + 6) & 0x7;
	372	if (!int_pending)
	373	return IRQ_NONE;
	374
	375	/* loop until all pending interrupts are handled */
	376	do {
	377	for_each_set_bit(port, &int_pending, 3) {
	378	int_id = inb(ws16c48gpio->base + 8 + port);
	379	for_each_set_bit(gpio, &int_id, 8)
	380	generic_handle_irq(irq_find_mapping(
f0fbe7bc	381	chip->irq.domain, gpio + 8*port));
9c26df9b WBG	382	}
	383
	384	int_pending = inb(ws16c48gpio->base + 6) & 0x7;
	385	} while (int_pending);
	386
	387	return IRQ_HANDLED;
	388	}
	389
5238f60f WBG	390	#define WS16C48_NGPIO 48
	391	static const char *ws16c48_names[WS16C48_NGPIO] = {
	392	"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
	393	"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
	394	"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
	395	"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
	396	"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
	397	"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
	398	"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
	399	"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
	400	"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
	401	"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
	402	"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
	403	"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
	404	};
	405
cc736607	406	static int ws16c48_probe(struct device *dev, unsigned int id)
9c26df9b	407	{
9c26df9b	408	struct ws16c48_gpio *ws16c48gpio;
9c26df9b WBG	409	const char *const name = dev_name(dev);
9c26df9b WBG	410	int err;
9c26df9b WBG	411
	412	ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
	413	if (!ws16c48gpio)
	414	return -ENOMEM;
	415
cc736607	416	if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
148ad68b	417	dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
cc736607	418	base[id], base[id] + WS16C48_EXTENT);
148ad68b	419	return -EBUSY;
9c26df9b WBG	420	}
	421
	422	ws16c48gpio->chip.label = name;
	423	ws16c48gpio->chip.parent = dev;
	424	ws16c48gpio->chip.owner = THIS_MODULE;
	425	ws16c48gpio->chip.base = -1;
5238f60f WBG	426	ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
5238f60f WBG	427	ws16c48gpio->chip.names = ws16c48_names;
9c26df9b WBG	428	ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
	429	ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
	430	ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
	431	ws16c48gpio->chip.get = ws16c48_gpio_get;
a8ff510d	432	ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
9c26df9b	433	ws16c48gpio->chip.set = ws16c48_gpio_set;
99c8ac95	434	ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
cc736607	435	ws16c48gpio->base = base[id];
9c26df9b	436
a0a584f0	437	raw_spin_lock_init(&ws16c48gpio->lock);
9c26df9b	438
b4cad1bc	439	err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
9c26df9b WBG	440	if (err) {
9c26df9b WBG	441	dev_err(dev, "GPIO registering failed (%d)\n", err);
148ad68b	442	return err;
9c26df9b WBG	443	}
	444
	445	/* Disable IRQ by default */
cc736607 WBG	446	outb(0x80, base[id] + 7);
	447	outb(0, base[id] + 8);
	448	outb(0, base[id] + 9);
	449	outb(0, base[id] + 10);
	450	outb(0xC0, base[id] + 7);
9c26df9b WBG	451
	452	err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
	453	handle_edge_irq, IRQ_TYPE_NONE);
	454	if (err) {
	455	dev_err(dev, "Could not add irqchip (%d)\n", err);
b4cad1bc	456	return err;
9c26df9b WBG	457	}
9c26df9b WBG	458
b4cad1bc WBG	459	err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
b4cad1bc WBG	460	name, ws16c48gpio);
9c26df9b WBG	461	if (err) {
9c26df9b WBG	462	dev_err(dev, "IRQ handler registering failed (%d)\n", err);
b4cad1bc	463	return err;
9c26df9b WBG	464	}
9c26df9b WBG	465
9c26df9b WBG	466	return 0;
	467	}
	468
cc736607 WBG	469	static struct isa_driver ws16c48_driver = {
cc736607 WBG	470	.probe = ws16c48_probe,
9c26df9b WBG	471	.driver = {
	472	.name = "ws16c48"
	473	},
9c26df9b WBG	474	};
9c26df9b WBG	475
cc736607	476	module_isa_driver(ws16c48_driver, num_ws16c48);
9c26df9b WBG	477
	478	MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
	479	MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
22aeddb5	480	MODULE_LICENSE("GPL v2");