[linux-2.6-block.git] / drivers / gpio / gpio-tz1090.c

/*
 * Toumaz Xenif TZ1090 GPIO handling.
 *
 * Copyright (C) 2008-2013 Imagination Technologies Ltd.
 *
 *  Based on ARM PXA code and others.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/bitops.h>
#include <linux/export.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <asm/global_lock.h>

/* Register offsets from bank base address */
#define REG_GPIO_DIR		0x00
#define REG_GPIO_IRQ_PLRT	0x20
#define REG_GPIO_IRQ_TYPE	0x30
#define REG_GPIO_IRQ_EN		0x40
#define REG_GPIO_IRQ_STS	0x50
#define REG_GPIO_BIT_EN		0x60
#define REG_GPIO_DIN		0x70
#define REG_GPIO_DOUT		0x80

/* REG_GPIO_IRQ_PLRT */
#define REG_GPIO_IRQ_PLRT_LOW	0
#define REG_GPIO_IRQ_PLRT_HIGH	1

/* REG_GPIO_IRQ_TYPE */
#define REG_GPIO_IRQ_TYPE_LEVEL	0
#define REG_GPIO_IRQ_TYPE_EDGE	1

/**
 * struct tz1090_gpio_bank - GPIO bank private data
 * @chip:	Generic GPIO chip for GPIO bank
 * @domain:	IRQ domain for GPIO bank (may be NULL)
 * @reg:	Base of registers, offset for this GPIO bank
 * @irq:	IRQ number for GPIO bank
 * @label:	Debug GPIO bank label, used for storage of chip->label
 *
 * This is the main private data for a GPIO bank. It encapsulates a gpio_chip,
 * and the callbacks for the gpio_chip can access the private data with the
 * to_bank() macro below.
 */
struct tz1090_gpio_bank {
	struct gpio_chip chip;
	struct irq_domain *domain;
	void __iomem *reg;
	int irq;
	char label[16];
};

/**
 * struct tz1090_gpio - Overall GPIO device private data
 * @dev:	Device (from platform device)
 * @reg:	Base of GPIO registers
 *
 * Represents the overall GPIO device. This structure is actually only
 * temporary, and used during init.
 */
struct tz1090_gpio {
	struct device *dev;
	void __iomem *reg;
};

/**
 * struct tz1090_gpio_bank_info - Temporary registration info for GPIO bank
 * @priv:	Overall GPIO device private data
 * @node:	Device tree node specific to this GPIO bank
 * @index:	Index of bank in range 0-2
 */
struct tz1090_gpio_bank_info {
	struct tz1090_gpio *priv;
	struct device_node *node;
	unsigned int index;
};

/* Convenience register accessors */
static inline void tz1090_gpio_write(struct tz1090_gpio_bank *bank,
			      unsigned int reg_offs, u32 data)
{
	iowrite32(data, bank->reg + reg_offs);
}

static inline u32 tz1090_gpio_read(struct tz1090_gpio_bank *bank,
			    unsigned int reg_offs)
{
	return ioread32(bank->reg + reg_offs);
}

/* caller must hold LOCK2 */
static inline void _tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
					  unsigned int reg_offs,
					  unsigned int offset)
{
	u32 value;

	value = tz1090_gpio_read(bank, reg_offs);
	value &= ~BIT(offset);
	tz1090_gpio_write(bank, reg_offs, value);
}

static void tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
				  unsigned int reg_offs,
				  unsigned int offset)
{
	int lstat;

	__global_lock2(lstat);
	_tz1090_gpio_clear_bit(bank, reg_offs, offset);
	__global_unlock2(lstat);
}

/* caller must hold LOCK2 */
static inline void _tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
					unsigned int reg_offs,
					unsigned int offset)
{
	u32 value;

	value = tz1090_gpio_read(bank, reg_offs);
	value |= BIT(offset);
	tz1090_gpio_write(bank, reg_offs, value);
}

static void tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
				unsigned int reg_offs,
				unsigned int offset)
{
	int lstat;

	__global_lock2(lstat);
	_tz1090_gpio_set_bit(bank, reg_offs, offset);
	__global_unlock2(lstat);
}

/* caller must hold LOCK2 */
static inline void _tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
					unsigned int reg_offs,
					unsigned int offset,
					bool val)
{
	u32 value;

	value = tz1090_gpio_read(bank, reg_offs);
	value &= ~BIT(offset);
	if (val)
		value |= BIT(offset);
	tz1090_gpio_write(bank, reg_offs, value);
}

static void tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
				unsigned int reg_offs,
				unsigned int offset,
				bool val)
{
	int lstat;

	__global_lock2(lstat);
	_tz1090_gpio_mod_bit(bank, reg_offs, offset, val);
	__global_unlock2(lstat);
}

static inline int tz1090_gpio_read_bit(struct tz1090_gpio_bank *bank,
				       unsigned int reg_offs,
				       unsigned int offset)
{
	return tz1090_gpio_read(bank, reg_offs) & BIT(offset);
}

/* GPIO chip callbacks */

static int tz1090_gpio_direction_input(struct gpio_chip *chip,
				       unsigned int offset)
{
	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
	tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);

	return 0;
}

static int tz1090_gpio_direction_output(struct gpio_chip *chip,
					unsigned int offset, int output_value)
{
	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
	int lstat;

	__global_lock2(lstat);
	_tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
	_tz1090_gpio_clear_bit(bank, REG_GPIO_DIR, offset);
	__global_unlock2(lstat);

	return 0;
}

/*
 * Return GPIO level
 */
static int tz1090_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);

	return !!tz1090_gpio_read_bit(bank, REG_GPIO_DIN, offset);
}

/*
 * Set output GPIO level
 */
static void tz1090_gpio_set(struct gpio_chip *chip, unsigned int offset,
			    int output_value)
{
	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);

	tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
}

static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
	int ret;

	ret = pinctrl_request_gpio(chip->base + offset);
	if (ret)
		return ret;

	tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
	tz1090_gpio_set_bit(bank, REG_GPIO_BIT_EN, offset);

	return 0;
}

static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);

	pinctrl_free_gpio(chip->base + offset);

	tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset);
}

static int tz1090_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);

	if (!bank->domain)
		return -EINVAL;

	return irq_create_mapping(bank->domain, offset);
}

/* IRQ chip handlers */

/* Get TZ1090 GPIO chip from irq data provided to generic IRQ callbacks */
static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data)
{
	return (struct tz1090_gpio_bank *)data->domain->host_data;
}

static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank,
				     unsigned int offset, unsigned int polarity)
{
	tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity);
}

static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank,
				 unsigned int offset, unsigned int type)
{
	tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_TYPE, offset, type);
}

/* set polarity to trigger on next edge, whether rising or falling */
static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank,
				      unsigned int offset)
{
	unsigned int value_p, value_i;
	int lstat;

	/*
	 * Set the GPIO's interrupt polarity to the opposite of the current
	 * input value so that the next edge triggers an interrupt.
	 */
	__global_lock2(lstat);
	value_i = ~tz1090_gpio_read(bank, REG_GPIO_DIN);
	value_p = tz1090_gpio_read(bank, REG_GPIO_IRQ_PLRT);
	value_p &= ~BIT(offset);
	value_p |= value_i & BIT(offset);
	tz1090_gpio_write(bank, REG_GPIO_IRQ_PLRT, value_p);
	__global_unlock2(lstat);
}

static unsigned int gpio_startup_irq(struct irq_data *data)
{
	/*
	 * This warning indicates that the type of the irq hasn't been set
	 * before enabling the irq. This would normally be done by passing some
	 * trigger flags to request_irq().
	 */
	WARN(irqd_get_trigger_type(data) == IRQ_TYPE_NONE,
		"irq type not set before enabling gpio irq %d", data->irq);

	irq_gc_ack_clr_bit(data);
	irq_gc_mask_set_bit(data);
	return 0;
}

static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type)
{
	struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
	unsigned int type;
	unsigned int polarity;

	switch (flow_type) {
	case IRQ_TYPE_EDGE_BOTH:
		type = REG_GPIO_IRQ_TYPE_EDGE;
		polarity = REG_GPIO_IRQ_PLRT_LOW;
		break;
	case IRQ_TYPE_EDGE_RISING:
		type = REG_GPIO_IRQ_TYPE_EDGE;
		polarity = REG_GPIO_IRQ_PLRT_HIGH;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		type = REG_GPIO_IRQ_TYPE_EDGE;
		polarity = REG_GPIO_IRQ_PLRT_LOW;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		type = REG_GPIO_IRQ_TYPE_LEVEL;
		polarity = REG_GPIO_IRQ_PLRT_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		type = REG_GPIO_IRQ_TYPE_LEVEL;
		polarity = REG_GPIO_IRQ_PLRT_LOW;
		break;
	default:
		return -EINVAL;
	}

	tz1090_gpio_irq_type(bank, data->hwirq, type);
	irq_setup_alt_chip(data, flow_type);

	if (flow_type == IRQ_TYPE_EDGE_BOTH)
		tz1090_gpio_irq_next_edge(bank, data->hwirq);
	else
		tz1090_gpio_irq_polarity(bank, data->hwirq, polarity);

	return 0;
}

#ifdef CONFIG_SUSPEND
static int gpio_set_irq_wake(struct irq_data *data, unsigned int on)
{
	struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);

#ifdef CONFIG_PM_DEBUG
	pr_info("irq_wake irq%d state:%d\n", data->irq, on);
#endif

	/* wake on gpio block interrupt */
	return irq_set_irq_wake(bank->irq, on);
}
#else
#define gpio_set_irq_wake NULL
#endif

static void tz1090_gpio_irq_handler(struct irq_desc *desc)
{
	irq_hw_number_t hw;
	unsigned int irq_stat, irq_no;
	struct tz1090_gpio_bank *bank;
	struct irq_desc *child_desc;

	bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc);
	irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) &
		   tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) &
		   tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) &
		   0x3FFFFFFF; /* 30 bits only */

	for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) {
		if (!(irq_stat & 1))
			continue;

		irq_no = irq_linear_revmap(bank->domain, hw);
		child_desc = irq_to_desc(irq_no);

		/* Toggle edge for pin with both edges triggering enabled */
		if (irqd_get_trigger_type(&child_desc->irq_data)
				== IRQ_TYPE_EDGE_BOTH)
			tz1090_gpio_irq_next_edge(bank, hw);

		generic_handle_irq_desc(child_desc);
	}
}

static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
{
	struct device_node *np = info->node;
	struct device *dev = info->priv->dev;
	struct tz1090_gpio_bank *bank;
	struct irq_chip_generic *gc;
	int err;

	bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
	if (!bank) {
		dev_err(dev, "unable to allocate driver data\n");
		return -ENOMEM;
	}

	/* Offset the main registers to the first register in this bank */
	bank->reg = info->priv->reg + info->index * 4;

	/* Set up GPIO chip */
	snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u",
		 info->index);
	bank->chip.label		= bank->label;
	bank->chip.parent		= dev;
	bank->chip.direction_input	= tz1090_gpio_direction_input;
	bank->chip.direction_output	= tz1090_gpio_direction_output;
	bank->chip.get			= tz1090_gpio_get;
	bank->chip.set			= tz1090_gpio_set;
	bank->chip.free			= tz1090_gpio_free;
	bank->chip.request		= tz1090_gpio_request;
	bank->chip.to_irq		= tz1090_gpio_to_irq;
	bank->chip.of_node		= np;

	/* GPIO numbering from 0 */
	bank->chip.base			= info->index * 30;
	bank->chip.ngpio		= 30;

	/* Add the GPIO bank */
	gpiochip_add_data(&bank->chip, bank);

	/* Get the GPIO bank IRQ if provided */
	bank->irq = irq_of_parse_and_map(np, 0);

	/* The interrupt is optional (it may be used by another core on chip) */
	if (!bank->irq) {
		dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n",
			 info->index);
		return 0;
	}

	dev_info(dev, "Setting up IRQs for GPIO bank %u\n",
		 info->index);

	/*
	 * Initialise all interrupts to disabled so we don't get
	 * spurious ones on a dirty boot and hit the BUG_ON in the
	 * handler.
	 */
	tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0);

	/* Add a virtual IRQ for each GPIO */
	bank->domain = irq_domain_add_linear(np,
					     bank->chip.ngpio,
					     &irq_generic_chip_ops,
					     bank);

	/* Set up a generic irq chip with 2 chip types (level and edge) */
	err = irq_alloc_domain_generic_chips(bank->domain, bank->chip.ngpio, 2,
					     bank->label, handle_bad_irq, 0, 0,
					     IRQ_GC_INIT_NESTED_LOCK);
	if (err) {
		dev_info(dev,
			 "irq_alloc_domain_generic_chips failed for bank %u, IRQs disabled\n",
			 info->index);
		irq_domain_remove(bank->domain);
		return 0;
	}

	gc = irq_get_domain_generic_chip(bank->domain, 0);
	gc->reg_base	= bank->reg;

	/* level chip type */
	gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;
	gc->chip_types[0].handler		= handle_level_irq;
	gc->chip_types[0].regs.ack		= REG_GPIO_IRQ_STS;
	gc->chip_types[0].regs.mask		= REG_GPIO_IRQ_EN;
	gc->chip_types[0].chip.irq_startup	= gpio_startup_irq;
	gc->chip_types[0].chip.irq_ack		= irq_gc_ack_clr_bit;
	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;
	gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;
	gc->chip_types[0].chip.irq_set_type	= gpio_set_irq_type;
	gc->chip_types[0].chip.irq_set_wake	= gpio_set_irq_wake;
	gc->chip_types[0].chip.flags		= IRQCHIP_MASK_ON_SUSPEND;

	/* edge chip type */
	gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;
	gc->chip_types[1].handler		= handle_edge_irq;
	gc->chip_types[1].regs.ack		= REG_GPIO_IRQ_STS;
	gc->chip_types[1].regs.mask		= REG_GPIO_IRQ_EN;
	gc->chip_types[1].chip.irq_startup	= gpio_startup_irq;
	gc->chip_types[1].chip.irq_ack		= irq_gc_ack_clr_bit;
	gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;
	gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;
	gc->chip_types[1].chip.irq_set_type	= gpio_set_irq_type;
	gc->chip_types[1].chip.irq_set_wake	= gpio_set_irq_wake;
	gc->chip_types[1].chip.flags		= IRQCHIP_MASK_ON_SUSPEND;

	/* Setup chained handler for this GPIO bank */
	irq_set_chained_handler_and_data(bank->irq, tz1090_gpio_irq_handler,
					 bank);

	return 0;
}

static void tz1090_gpio_register_banks(struct tz1090_gpio *priv)
{
	struct device_node *np = priv->dev->of_node;
	struct device_node *node;

	for_each_available_child_of_node(np, node) {
		struct tz1090_gpio_bank_info info;
		u32 addr;
		int ret;

		ret = of_property_read_u32(node, "reg", &addr);
		if (ret) {
			dev_err(priv->dev, "invalid reg on %s\n",
				node->full_name);
			continue;
		}
		if (addr >= 3) {
			dev_err(priv->dev, "index %u in %s out of range\n",
				addr, node->full_name);
			continue;
		}

		info.index = addr;
		info.node = of_node_get(node);
		info.priv = priv;

		ret = tz1090_gpio_bank_probe(&info);
		if (ret) {
			dev_err(priv->dev, "failure registering %s\n",
				node->full_name);
			of_node_put(node);
			continue;
		}
	}
}

static int tz1090_gpio_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct resource *res_regs;
	struct tz1090_gpio priv;

	if (!np) {
		dev_err(&pdev->dev, "must be instantiated via devicetree\n");
		return -ENOENT;
	}

	res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res_regs) {
		dev_err(&pdev->dev, "cannot find registers resource\n");
		return -ENOENT;
	}

	priv.dev = &pdev->dev;

	/* Ioremap the registers */
	priv.reg = devm_ioremap(&pdev->dev, res_regs->start,
				resource_size(res_regs));
	if (!priv.reg) {
		dev_err(&pdev->dev, "unable to ioremap registers\n");
		return -ENOMEM;
	}

	/* Look for banks */
	tz1090_gpio_register_banks(&priv);

	return 0;
}

static struct of_device_id tz1090_gpio_of_match[] = {
	{ .compatible = "img,tz1090-gpio" },
	{ },
};

static struct platform_driver tz1090_gpio_driver = {
	.driver = {
		.name		= "tz1090-gpio",
		.of_match_table	= tz1090_gpio_of_match,
	},
	.probe		= tz1090_gpio_probe,
};

static int __init tz1090_gpio_init(void)
{
	return platform_driver_register(&tz1090_gpio_driver);
}
subsys_initcall(tz1090_gpio_init);
Commit	Line	Data
9caf1f22 JH	1	/*
	2	* Toumaz Xenif TZ1090 GPIO handling.
	3	*
	4	* Copyright (C) 2008-2013 Imagination Technologies Ltd.
	5	*
	6	* Based on ARM PXA code and others.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/bitops.h>
	14	#include <linux/export.h>
	15	#include <linux/gpio.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/io.h>
	18	#include <linux/irq.h>
	19	#include <linux/irqdomain.h>
	20	#include <linux/kernel.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/pinctrl/consumer.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/slab.h>
	25	#include <linux/syscore_ops.h>
	26	#include <asm/global_lock.h>
	27
	28	/* Register offsets from bank base address */
	29	#define REG_GPIO_DIR 0x00
	30	#define REG_GPIO_IRQ_PLRT 0x20
	31	#define REG_GPIO_IRQ_TYPE 0x30
	32	#define REG_GPIO_IRQ_EN 0x40
	33	#define REG_GPIO_IRQ_STS 0x50
	34	#define REG_GPIO_BIT_EN 0x60
	35	#define REG_GPIO_DIN 0x70
	36	#define REG_GPIO_DOUT 0x80
	37
	38	/* REG_GPIO_IRQ_PLRT */
	39	#define REG_GPIO_IRQ_PLRT_LOW 0
	40	#define REG_GPIO_IRQ_PLRT_HIGH 1
	41
	42	/* REG_GPIO_IRQ_TYPE */
	43	#define REG_GPIO_IRQ_TYPE_LEVEL 0
	44	#define REG_GPIO_IRQ_TYPE_EDGE 1
	45
	46	/**
	47	* struct tz1090_gpio_bank - GPIO bank private data
	48	* @chip: Generic GPIO chip for GPIO bank
	49	* @domain: IRQ domain for GPIO bank (may be NULL)
	50	* @reg: Base of registers, offset for this GPIO bank
	51	* @irq: IRQ number for GPIO bank
	52	* @label: Debug GPIO bank label, used for storage of chip->label
	53	*
	54	* This is the main private data for a GPIO bank. It encapsulates a gpio_chip,
	55	* and the callbacks for the gpio_chip can access the private data with the
	56	* to_bank() macro below.
	57	*/
	58	struct tz1090_gpio_bank {
	59	struct gpio_chip chip;
	60	struct irq_domain *domain;
	61	void __iomem *reg;
	62	int irq;
	63	char label[16];
	64	};
9caf1f22 JH	65
	66	/**
	67	* struct tz1090_gpio - Overall GPIO device private data
	68	* @dev: Device (from platform device)
	69	* @reg: Base of GPIO registers
	70	*
	71	* Represents the overall GPIO device. This structure is actually only
	72	* temporary, and used during init.
	73	*/
	74	struct tz1090_gpio {
	75	struct device *dev;
	76	void __iomem *reg;
	77	};
	78
	79	/**
	80	* struct tz1090_gpio_bank_info - Temporary registration info for GPIO bank
	81	* @priv: Overall GPIO device private data
	82	* @node: Device tree node specific to this GPIO bank
	83	* @index: Index of bank in range 0-2
	84	*/
	85	struct tz1090_gpio_bank_info {
	86	struct tz1090_gpio *priv;
	87	struct device_node *node;
	88	unsigned int index;
	89	};
	90
	91	/* Convenience register accessors */
	92	static inline void tz1090_gpio_write(struct tz1090_gpio_bank *bank,
	93	unsigned int reg_offs, u32 data)
	94	{
	95	iowrite32(data, bank->reg + reg_offs);
	96	}
	97
	98	static inline u32 tz1090_gpio_read(struct tz1090_gpio_bank *bank,
	99	unsigned int reg_offs)
	100	{
	101	return ioread32(bank->reg + reg_offs);
	102	}
	103
	104	/* caller must hold LOCK2 */
	105	static inline void _tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
	106	unsigned int reg_offs,
	107	unsigned int offset)
	108	{
	109	u32 value;
	110
	111	value = tz1090_gpio_read(bank, reg_offs);
	112	value &= ~BIT(offset);
	113	tz1090_gpio_write(bank, reg_offs, value);
	114	}
	115
	116	static void tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
	117	unsigned int reg_offs,
	118	unsigned int offset)
	119	{
	120	int lstat;
	121
	122	__global_lock2(lstat);
	123	_tz1090_gpio_clear_bit(bank, reg_offs, offset);
	124	__global_unlock2(lstat);
	125	}
	126
	127	/* caller must hold LOCK2 */
	128	static inline void _tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
129	unsigned int reg_offs,
130	unsigned int offset)
131	{
132	u32 value;
133
134	value = tz1090_gpio_read(bank, reg_offs);
135	value \|= BIT(offset);
136	tz1090_gpio_write(bank, reg_offs, value);
137	}
138
139	static void tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
140	unsigned int reg_offs,
141	unsigned int offset)
142	{
143	int lstat;
144
145	__global_lock2(lstat);
146	_tz1090_gpio_set_bit(bank, reg_offs, offset);
147	__global_unlock2(lstat);
148	}
149
150	/* caller must hold LOCK2 */
151	static inline void _tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
152	unsigned int reg_offs,
153	unsigned int offset,
154	bool val)
155	{
156	u32 value;
157
158	value = tz1090_gpio_read(bank, reg_offs);
159	value &= ~BIT(offset);
160	if (val)
161	value \|= BIT(offset);
162	tz1090_gpio_write(bank, reg_offs, value);
163	}
164
165	static void tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
166	unsigned int reg_offs,
167	unsigned int offset,
168	bool val)
169	{
170	int lstat;
171
172	__global_lock2(lstat);
173	_tz1090_gpio_mod_bit(bank, reg_offs, offset, val);
174	__global_unlock2(lstat);
175	}
176
177	static inline int tz1090_gpio_read_bit(struct tz1090_gpio_bank *bank,
178	unsigned int reg_offs,
179	unsigned int offset)
180	{
181	return tz1090_gpio_read(bank, reg_offs) & BIT(offset);
182	}
183
184	/* GPIO chip callbacks */
185
186	static int tz1090_gpio_direction_input(struct gpio_chip *chip,
187	unsigned int offset)
188	{
7020e7c5	189	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
9caf1f22 JH	190	tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
	191
	192	return 0;
	193	}
	194
	195	static int tz1090_gpio_direction_output(struct gpio_chip *chip,
	196	unsigned int offset, int output_value)
	197	{
7020e7c5	198	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
9caf1f22 JH	199	int lstat;
	200
	201	__global_lock2(lstat);
	202	_tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
	203	_tz1090_gpio_clear_bit(bank, REG_GPIO_DIR, offset);
	204	__global_unlock2(lstat);
	205
	206	return 0;
	207	}
	208
	209	/*
	210	* Return GPIO level
	211	*/
	212	static int tz1090_gpio_get(struct gpio_chip *chip, unsigned int offset)
	213	{
7020e7c5	214	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
9caf1f22	215
9fa90796	216	return !!tz1090_gpio_read_bit(bank, REG_GPIO_DIN, offset);
9caf1f22 JH	217	}
	218
	219	/*
	220	* Set output GPIO level
	221	*/
	222	static void tz1090_gpio_set(struct gpio_chip *chip, unsigned int offset,
	223	int output_value)
	224	{
7020e7c5	225	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
9caf1f22 JH	226
	227	tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
	228	}
	229
	230	static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset)
	231	{
7020e7c5	232	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
9caf1f22 JH	233	int ret;
	234
	235	ret = pinctrl_request_gpio(chip->base + offset);
	236	if (ret)
	237	return ret;
	238
	239	tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
	240	tz1090_gpio_set_bit(bank, REG_GPIO_BIT_EN, offset);
	241
	242	return 0;
	243	}
	244
	245	static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset)
	246	{
7020e7c5	247	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
9caf1f22 JH	248
	249	pinctrl_free_gpio(chip->base + offset);
	250
	251	tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset);
	252	}
	253
	254	static int tz1090_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
	255	{
7020e7c5	256	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
9caf1f22 JH	257
	258	if (!bank->domain)
	259	return -EINVAL;
	260
	261	return irq_create_mapping(bank->domain, offset);
	262	}
	263
	264	/* IRQ chip handlers */
	265
	266	/* Get TZ1090 GPIO chip from irq data provided to generic IRQ callbacks */
	267	static inline struct tz1090_gpio_bank irqd_to_gpio_bank(struct irq_data data)
	268	{
	269	return (struct tz1090_gpio_bank *)data->domain->host_data;
	270	}
	271
9caf1f22 JH	272	static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank,
	273	unsigned int offset, unsigned int polarity)
	274	{
	275	tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity);
	276	}
	277
9caf1f22 JH	278	static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank,
	279	unsigned int offset, unsigned int type)
	280	{
	281	tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_TYPE, offset, type);
	282	}
	283
	284	/* set polarity to trigger on next edge, whether rising or falling */
	285	static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank,
	286	unsigned int offset)
	287	{
	288	unsigned int value_p, value_i;
	289	int lstat;
	290
	291	/*
	292	* Set the GPIO's interrupt polarity to the opposite of the current
	293	* input value so that the next edge triggers an interrupt.
	294	*/
	295	__global_lock2(lstat);
	296	value_i = ~tz1090_gpio_read(bank, REG_GPIO_DIN);
	297	value_p = tz1090_gpio_read(bank, REG_GPIO_IRQ_PLRT);
	298	value_p &= ~BIT(offset);
	299	value_p \|= value_i & BIT(offset);
	300	tz1090_gpio_write(bank, REG_GPIO_IRQ_PLRT, value_p);
	301	__global_unlock2(lstat);
	302	}
	303
9caf1f22 JH	304	static unsigned int gpio_startup_irq(struct irq_data *data)
9caf1f22 JH	305	{
9caf1f22 JH	306	/*
	307	* This warning indicates that the type of the irq hasn't been set
	308	* before enabling the irq. This would normally be done by passing some
	309	* trigger flags to request_irq().
	310	*/
04777396	311	WARN(irqd_get_trigger_type(data) == IRQ_TYPE_NONE,
9caf1f22 JH	312	"irq type not set before enabling gpio irq %d", data->irq);
9caf1f22 JH	313
04777396 JH	314	irq_gc_ack_clr_bit(data);
04777396 JH	315	irq_gc_mask_set_bit(data);
9caf1f22 JH	316	return 0;
	317	}
	318
	319	static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type)
	320	{
	321	struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
	322	unsigned int type;
	323	unsigned int polarity;
	324
	325	switch (flow_type) {
	326	case IRQ_TYPE_EDGE_BOTH:
	327	type = REG_GPIO_IRQ_TYPE_EDGE;
	328	polarity = REG_GPIO_IRQ_PLRT_LOW;
	329	break;
	330	case IRQ_TYPE_EDGE_RISING:
	331	type = REG_GPIO_IRQ_TYPE_EDGE;
	332	polarity = REG_GPIO_IRQ_PLRT_HIGH;
	333	break;
	334	case IRQ_TYPE_EDGE_FALLING:
	335	type = REG_GPIO_IRQ_TYPE_EDGE;
	336	polarity = REG_GPIO_IRQ_PLRT_LOW;
	337	break;
	338	case IRQ_TYPE_LEVEL_HIGH:
	339	type = REG_GPIO_IRQ_TYPE_LEVEL;
	340	polarity = REG_GPIO_IRQ_PLRT_HIGH;
	341	break;
	342	case IRQ_TYPE_LEVEL_LOW:
	343	type = REG_GPIO_IRQ_TYPE_LEVEL;
	344	polarity = REG_GPIO_IRQ_PLRT_LOW;
	345	break;
	346	default:
	347	return -EINVAL;
	348	}
	349
	350	tz1090_gpio_irq_type(bank, data->hwirq, type);
04777396	351	irq_setup_alt_chip(data, flow_type);
9caf1f22 JH	352
	353	if (flow_type == IRQ_TYPE_EDGE_BOTH)
	354	tz1090_gpio_irq_next_edge(bank, data->hwirq);
	355	else
	356	tz1090_gpio_irq_polarity(bank, data->hwirq, polarity);
	357
	358	return 0;
	359	}
	360
	361	#ifdef CONFIG_SUSPEND
	362	static int gpio_set_irq_wake(struct irq_data *data, unsigned int on)
	363	{
	364	struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
	365
	366	#ifdef CONFIG_PM_DEBUG
	367	pr_info("irq_wake irq%d state:%d\n", data->irq, on);
	368	#endif
	369
	370	/* wake on gpio block interrupt */
	371	return irq_set_irq_wake(bank->irq, on);
	372	}
	373	#else
	374	#define gpio_set_irq_wake NULL
	375	#endif
	376
bd0b9ac4	377	static void tz1090_gpio_irq_handler(struct irq_desc *desc)
9caf1f22 JH	378	{
	379	irq_hw_number_t hw;
	380	unsigned int irq_stat, irq_no;
	381	struct tz1090_gpio_bank *bank;
	382	struct irq_desc *child_desc;
	383
	384	bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc);
	385	irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) &
	386	tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) &
	387	tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) &
	388	0x3FFFFFFF; /* 30 bits only */
	389
	390	for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) {
	391	if (!(irq_stat & 1))
	392	continue;
	393
	394	irq_no = irq_linear_revmap(bank->domain, hw);
	395	child_desc = irq_to_desc(irq_no);
	396
	397	/* Toggle edge for pin with both edges triggering enabled */
	398	if (irqd_get_trigger_type(&child_desc->irq_data)
	399	== IRQ_TYPE_EDGE_BOTH)
	400	tz1090_gpio_irq_next_edge(bank, hw);
	401
bd0b9ac4	402	generic_handle_irq_desc(child_desc);
9caf1f22 JH	403	}
	404	}
	405
9caf1f22 JH	406	static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
	407	{
	408	struct device_node *np = info->node;
	409	struct device *dev = info->priv->dev;
	410	struct tz1090_gpio_bank *bank;
04777396 JH	411	struct irq_chip_generic *gc;
04777396 JH	412	int err;
9caf1f22 JH	413
	414	bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
	415	if (!bank) {
	416	dev_err(dev, "unable to allocate driver data\n");
	417	return -ENOMEM;
	418	}
	419
	420	/* Offset the main registers to the first register in this bank */
	421	bank->reg = info->priv->reg + info->index * 4;
	422
	423	/* Set up GPIO chip */
	424	snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u",
	425	info->index);
	426	bank->chip.label = bank->label;
0d1bb2b3	427	bank->chip.parent = dev;
9caf1f22 JH	428	bank->chip.direction_input = tz1090_gpio_direction_input;
	429	bank->chip.direction_output = tz1090_gpio_direction_output;
	430	bank->chip.get = tz1090_gpio_get;
	431	bank->chip.set = tz1090_gpio_set;
	432	bank->chip.free = tz1090_gpio_free;
	433	bank->chip.request = tz1090_gpio_request;
	434	bank->chip.to_irq = tz1090_gpio_to_irq;
	435	bank->chip.of_node = np;
	436
	437	/* GPIO numbering from 0 */
	438	bank->chip.base = info->index * 30;
	439	bank->chip.ngpio = 30;
	440
	441	/* Add the GPIO bank */
7020e7c5	442	gpiochip_add_data(&bank->chip, bank);
9caf1f22 JH	443
	444	/* Get the GPIO bank IRQ if provided */
	445	bank->irq = irq_of_parse_and_map(np, 0);
	446
	447	/* The interrupt is optional (it may be used by another core on chip) */
842e528e	448	if (!bank->irq) {
9caf1f22 JH	449	dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n",
	450	info->index);
	451	return 0;
	452	}
	453
	454	dev_info(dev, "Setting up IRQs for GPIO bank %u\n",
	455	info->index);
	456
	457	/*
	458	* Initialise all interrupts to disabled so we don't get
	459	* spurious ones on a dirty boot and hit the BUG_ON in the
	460	* handler.
	461	*/
	462	tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0);
	463
	464	/* Add a virtual IRQ for each GPIO */
	465	bank->domain = irq_domain_add_linear(np,
	466	bank->chip.ngpio,
04777396	467	&irq_generic_chip_ops,
9caf1f22 JH	468	bank);
9caf1f22 JH	469
04777396 JH	470	/* Set up a generic irq chip with 2 chip types (level and edge) */
	471	err = irq_alloc_domain_generic_chips(bank->domain, bank->chip.ngpio, 2,
	472	bank->label, handle_bad_irq, 0, 0,
	473	IRQ_GC_INIT_NESTED_LOCK);
	474	if (err) {
	475	dev_info(dev,
	476	"irq_alloc_domain_generic_chips failed for bank %u, IRQs disabled\n",
	477	info->index);
	478	irq_domain_remove(bank->domain);
	479	return 0;
	480	}
	481
	482	gc = irq_get_domain_generic_chip(bank->domain, 0);
	483	gc->reg_base = bank->reg;
	484
	485	/* level chip type */
	486	gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	487	gc->chip_types[0].handler = handle_level_irq;
	488	gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS;
	489	gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN;
d3e14453 JH	490	gc->chip_types[0].chip.irq_startup = gpio_startup_irq;
	491	gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
	492	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
	493	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
	494	gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type;
	495	gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake;
	496	gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
04777396 JH	497
	498	/* edge chip type */
	499	gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	500	gc->chip_types[1].handler = handle_edge_irq;
	501	gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS;
	502	gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN;
d3e14453 JH	503	gc->chip_types[1].chip.irq_startup = gpio_startup_irq;
	504	gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit;
	505	gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
	506	gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
	507	gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type;
	508	gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake;
	509	gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
04777396	510
9caf1f22	511	/* Setup chained handler for this GPIO bank */
77c77e3f TG	512	irq_set_chained_handler_and_data(bank->irq, tz1090_gpio_irq_handler,
77c77e3f TG	513	bank);
9caf1f22 JH	514
	515	return 0;
	516	}
	517
	518	static void tz1090_gpio_register_banks(struct tz1090_gpio *priv)
	519	{
	520	struct device_node *np = priv->dev->of_node;
	521	struct device_node *node;
	522
	523	for_each_available_child_of_node(np, node) {
	524	struct tz1090_gpio_bank_info info;
	525	u32 addr;
	526	int ret;
	527
	528	ret = of_property_read_u32(node, "reg", &addr);
	529	if (ret) {
	530	dev_err(priv->dev, "invalid reg on %s\n",
	531	node->full_name);
	532	continue;
	533	}
	534	if (addr >= 3) {
	535	dev_err(priv->dev, "index %u in %s out of range\n",
	536	addr, node->full_name);
	537	continue;
	538	}
	539
	540	info.index = addr;
	541	info.node = of_node_get(node);
	542	info.priv = priv;
	543
	544	ret = tz1090_gpio_bank_probe(&info);
	545	if (ret) {
	546	dev_err(priv->dev, "failure registering %s\n",
	547	node->full_name);
	548	of_node_put(node);
	549	continue;
	550	}
	551	}
	552	}
	553
	554	static int tz1090_gpio_probe(struct platform_device *pdev)
	555	{
	556	struct device_node *np = pdev->dev.of_node;
	557	struct resource *res_regs;
	558	struct tz1090_gpio priv;
	559
	560	if (!np) {
	561	dev_err(&pdev->dev, "must be instantiated via devicetree\n");
	562	return -ENOENT;
	563	}
	564
	565	res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	566	if (!res_regs) {
	567	dev_err(&pdev->dev, "cannot find registers resource\n");
	568	return -ENOENT;
	569	}
	570
	571	priv.dev = &pdev->dev;
	572
	573	/* Ioremap the registers */
	574	priv.reg = devm_ioremap(&pdev->dev, res_regs->start,
08b89fa2	575	resource_size(res_regs));
9caf1f22 JH	576	if (!priv.reg) {
	577	dev_err(&pdev->dev, "unable to ioremap registers\n");
	578	return -ENOMEM;
	579	}
	580
	581	/* Look for banks */
	582	tz1090_gpio_register_banks(&priv);
	583
	584	return 0;
	585	}
	586
	587	static struct of_device_id tz1090_gpio_of_match[] = {
	588	{ .compatible = "img,tz1090-gpio" },
	589	{ },
	590	};
	591
	592	static struct platform_driver tz1090_gpio_driver = {
	593	.driver = {
	594	.name = "tz1090-gpio",
9caf1f22 JH	595	.of_match_table = tz1090_gpio_of_match,
	596	},
	597	.probe = tz1090_gpio_probe,
	598	};
	599
	600	static int __init tz1090_gpio_init(void)
	601	{
	602	return platform_driver_register(&tz1090_gpio_driver);
	603	}
	604	subsys_initcall(tz1090_gpio_init);