[linux-2.6-block.git] / drivers / gpio / gpio-timberdale.c

/*
 * Timberdale FPGA GPIO driver
 * Copyright (c) 2009 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Timberdale FPGA GPIO
 */

#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/timb_gpio.h>
#include <linux/interrupt.h>
#include <linux/slab.h>

#define DRIVER_NAME "timb-gpio"

#define TGPIOVAL	0x00
#define TGPIODIR	0x04
#define TGPIO_IER	0x08
#define TGPIO_ISR	0x0c
#define TGPIO_IPR	0x10
#define TGPIO_ICR	0x14
#define TGPIO_FLR	0x18
#define TGPIO_LVR	0x1c
#define TGPIO_VER	0x20
#define TGPIO_BFLR	0x24

struct timbgpio {
	void __iomem		*membase;
	spinlock_t		lock; /* mutual exclusion */
	struct gpio_chip	gpio;
	int			irq_base;
	unsigned long		last_ier;
};

static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	unsigned offset, bool enabled)
{
	struct timbgpio *tgpio = gpiochip_get_data(gpio);
	u32 reg;

	spin_lock(&tgpio->lock);
	reg = ioread32(tgpio->membase + offset);

	if (enabled)
		reg |= (1 << index);
	else
		reg &= ~(1 << index);

	iowrite32(reg, tgpio->membase + offset);
	spin_unlock(&tgpio->lock);

	return 0;
}

static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
}

static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct timbgpio *tgpio = gpiochip_get_data(gpio);
	u32 value;

	value = ioread32(tgpio->membase + TGPIOVAL);
	return (value & (1 << nr)) ? 1 : 0;
}

static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
						unsigned nr, int val)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
}

static void timbgpio_gpio_set(struct gpio_chip *gpio,
				unsigned nr, int val)
{
	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
}

static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct timbgpio *tgpio = gpiochip_get_data(gpio);

	if (tgpio->irq_base <= 0)
		return -EINVAL;

	return tgpio->irq_base + offset;
}

/*
 * GPIO IRQ
 */
static void timbgpio_irq_disable(struct irq_data *d)
{
	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tgpio->irq_base;
	unsigned long flags;

	spin_lock_irqsave(&tgpio->lock, flags);
	tgpio->last_ier &= ~(1UL << offset);
	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
	spin_unlock_irqrestore(&tgpio->lock, flags);
}

static void timbgpio_irq_enable(struct irq_data *d)
{
	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tgpio->irq_base;
	unsigned long flags;

	spin_lock_irqsave(&tgpio->lock, flags);
	tgpio->last_ier |= 1UL << offset;
	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
	spin_unlock_irqrestore(&tgpio->lock, flags);
}

static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
{
	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tgpio->irq_base;
	unsigned long flags;
	u32 lvr, flr, bflr = 0;
	u32 ver;
	int ret = 0;

	if (offset < 0 || offset > tgpio->gpio.ngpio)
		return -EINVAL;

	ver = ioread32(tgpio->membase + TGPIO_VER);

	spin_lock_irqsave(&tgpio->lock, flags);

	lvr = ioread32(tgpio->membase + TGPIO_LVR);
	flr = ioread32(tgpio->membase + TGPIO_FLR);
	if (ver > 2)
		bflr = ioread32(tgpio->membase + TGPIO_BFLR);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		bflr &= ~(1 << offset);
		flr &= ~(1 << offset);
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			lvr |= 1 << offset;
		else
			lvr &= ~(1 << offset);
	}

	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		if (ver < 3) {
			ret = -EINVAL;
			goto out;
		} else {
			flr |= 1 << offset;
			bflr |= 1 << offset;
		}
	} else {
		bflr &= ~(1 << offset);
		flr |= 1 << offset;
		if (trigger & IRQ_TYPE_EDGE_FALLING)
			lvr &= ~(1 << offset);
		else
			lvr |= 1 << offset;
	}

	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
	iowrite32(flr, tgpio->membase + TGPIO_FLR);
	if (ver > 2)
		iowrite32(bflr, tgpio->membase + TGPIO_BFLR);

	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);

out:
	spin_unlock_irqrestore(&tgpio->lock, flags);
	return ret;
}

static void timbgpio_irq(struct irq_desc *desc)
{
	struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
	struct irq_data *data = irq_desc_get_irq_data(desc);
	unsigned long ipr;
	int offset;

	data->chip->irq_ack(data);
	ipr = ioread32(tgpio->membase + TGPIO_IPR);
	iowrite32(ipr, tgpio->membase + TGPIO_ICR);

	/*
	 * Some versions of the hardware trash the IER register if more than
	 * one interrupt is received simultaneously.
	 */
	iowrite32(0, tgpio->membase + TGPIO_IER);

	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
		generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));

	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
}

static struct irq_chip timbgpio_irqchip = {
	.name		= "GPIO",
	.irq_enable	= timbgpio_irq_enable,
	.irq_disable	= timbgpio_irq_disable,
	.irq_set_type	= timbgpio_irq_type,
};

static int timbgpio_probe(struct platform_device *pdev)
{
	int err, i;
	struct device *dev = &pdev->dev;
	struct gpio_chip *gc;
	struct timbgpio *tgpio;
	struct resource *iomem;
	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	int irq = platform_get_irq(pdev, 0);

	if (!pdata || pdata->nr_pins > 32) {
		dev_err(dev, "Invalid platform data\n");
		return -EINVAL;
	}

	tgpio = devm_kzalloc(dev, sizeof(struct timbgpio), GFP_KERNEL);
	if (!tgpio) {
		dev_err(dev, "Memory alloc failed\n");
		return -EINVAL;
	}
	tgpio->irq_base = pdata->irq_base;

	spin_lock_init(&tgpio->lock);

	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tgpio->membase = devm_ioremap_resource(dev, iomem);
	if (IS_ERR(tgpio->membase))
		return PTR_ERR(tgpio->membase);

	gc = &tgpio->gpio;

	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->parent = &pdev->dev;
	gc->direction_input = timbgpio_gpio_direction_input;
	gc->get = timbgpio_gpio_get;
	gc->direction_output = timbgpio_gpio_direction_output;
	gc->set = timbgpio_gpio_set;
	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	gc->dbg_show = NULL;
	gc->base = pdata->gpio_base;
	gc->ngpio = pdata->nr_pins;
	gc->can_sleep = false;

	err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
	if (err)
		return err;

	platform_set_drvdata(pdev, tgpio);

	/* make sure to disable interrupts */
	iowrite32(0x0, tgpio->membase + TGPIO_IER);

	if (irq < 0 || tgpio->irq_base <= 0)
		return 0;

	for (i = 0; i < pdata->nr_pins; i++) {
		irq_set_chip_and_handler(tgpio->irq_base + i,
			&timbgpio_irqchip, handle_simple_irq);
		irq_set_chip_data(tgpio->irq_base + i, tgpio);
		irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
	}

	irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);

	return 0;
}

static int timbgpio_remove(struct platform_device *pdev)
{
	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct timbgpio *tgpio = platform_get_drvdata(pdev);
	int irq = platform_get_irq(pdev, 0);

	if (irq >= 0 && tgpio->irq_base > 0) {
		int i;
		for (i = 0; i < pdata->nr_pins; i++) {
			irq_set_chip(tgpio->irq_base + i, NULL);
			irq_set_chip_data(tgpio->irq_base + i, NULL);
		}

		irq_set_handler(irq, NULL);
		irq_set_handler_data(irq, NULL);
	}

	return 0;
}

static struct platform_driver timbgpio_platform_driver = {
	.driver = {
		.name	= DRIVER_NAME,
	},
	.probe		= timbgpio_probe,
	.remove		= timbgpio_remove,
};

/*--------------------------------------------------------------------------*/

module_platform_driver(timbgpio_platform_driver);

MODULE_DESCRIPTION("Timberdale GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mocean Laboratories");
MODULE_ALIAS("platform:"DRIVER_NAME);
Commit	Line	Data
35570ac6	1	/*
c103de24	2	* Timberdale FPGA GPIO driver
35570ac6 RR	3	* Copyright (c) 2009 Intel Corporation
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*/
	18
	19	/* Supports:
	20	* Timberdale FPGA GPIO
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/gpio.h>
	25	#include <linux/platform_device.h>
e3cb91ce	26	#include <linux/irq.h>
35570ac6 RR	27	#include <linux/io.h>
	28	#include <linux/timb_gpio.h>
	29	#include <linux/interrupt.h>
5a0e3ad6	30	#include <linux/slab.h>
35570ac6 RR	31
	32	#define DRIVER_NAME "timb-gpio"
	33
	34	#define TGPIOVAL 0x00
	35	#define TGPIODIR 0x04
	36	#define TGPIO_IER 0x08
	37	#define TGPIO_ISR 0x0c
	38	#define TGPIO_IPR 0x10
	39	#define TGPIO_ICR 0x14
	40	#define TGPIO_FLR 0x18
	41	#define TGPIO_LVR 0x1c
8c35c89a RR	42	#define TGPIO_VER 0x20
8c35c89a RR	43	#define TGPIO_BFLR 0x24
35570ac6 RR	44
	45	struct timbgpio {
	46	void __iomem *membase;
	47	spinlock_t lock; /* mutual exclusion */
	48	struct gpio_chip gpio;
	49	int irq_base;
76d800a5	50	unsigned long last_ier;
35570ac6 RR	51	};
	52
	53	static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	54	unsigned offset, bool enabled)
	55	{
92a41e2f	56	struct timbgpio *tgpio = gpiochip_get_data(gpio);
35570ac6 RR	57	u32 reg;
	58
	59	spin_lock(&tgpio->lock);
	60	reg = ioread32(tgpio->membase + offset);
	61
	62	if (enabled)
	63	reg \|= (1 << index);
	64	else
	65	reg &= ~(1 << index);
	66
	67	iowrite32(reg, tgpio->membase + offset);
	68	spin_unlock(&tgpio->lock);
	69
	70	return 0;
	71	}
	72
	73	static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	74	{
	75	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
	76	}
	77
	78	static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
	79	{
92a41e2f	80	struct timbgpio *tgpio = gpiochip_get_data(gpio);
35570ac6 RR	81	u32 value;
	82
	83	value = ioread32(tgpio->membase + TGPIOVAL);
	84	return (value & (1 << nr)) ? 1 : 0;
	85	}
	86
	87	static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
	88	unsigned nr, int val)
	89	{
	90	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
	91	}
	92
	93	static void timbgpio_gpio_set(struct gpio_chip *gpio,
	94	unsigned nr, int val)
	95	{
	96	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
	97	}
	98
	99	static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	100	{
92a41e2f	101	struct timbgpio *tgpio = gpiochip_get_data(gpio);
35570ac6 RR	102
	103	if (tgpio->irq_base <= 0)
	104	return -EINVAL;
	105
	106	return tgpio->irq_base + offset;
	107	}
	108
	109	/*
	110	* GPIO IRQ
	111	*/
a1f5f22a	112	static void timbgpio_irq_disable(struct irq_data *d)
35570ac6	113	{
a1f5f22a LB	114	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
a1f5f22a LB	115	int offset = d->irq - tgpio->irq_base;
76d800a5	116	unsigned long flags;
35570ac6	117
76d800a5	118	spin_lock_irqsave(&tgpio->lock, flags);
d79550a7	119	tgpio->last_ier &= ~(1UL << offset);
76d800a5 TH	120	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
76d800a5 TH	121	spin_unlock_irqrestore(&tgpio->lock, flags);
35570ac6 RR	122	}
35570ac6 RR	123
a1f5f22a	124	static void timbgpio_irq_enable(struct irq_data *d)
35570ac6	125	{
a1f5f22a LB	126	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
a1f5f22a LB	127	int offset = d->irq - tgpio->irq_base;
76d800a5	128	unsigned long flags;
35570ac6	129
76d800a5	130	spin_lock_irqsave(&tgpio->lock, flags);
d79550a7	131	tgpio->last_ier \|= 1UL << offset;
76d800a5 TH	132	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
76d800a5 TH	133	spin_unlock_irqrestore(&tgpio->lock, flags);
35570ac6 RR	134	}
35570ac6 RR	135
a1f5f22a	136	static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
35570ac6	137	{
a1f5f22a LB	138	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
a1f5f22a LB	139	int offset = d->irq - tgpio->irq_base;
35570ac6	140	unsigned long flags;
8c35c89a RR	141	u32 lvr, flr, bflr = 0;
8c35c89a RR	142	u32 ver;
2a481800	143	int ret = 0;
35570ac6 RR	144
	145	if (offset < 0 \|\| offset > tgpio->gpio.ngpio)
	146	return -EINVAL;
	147
8c35c89a RR	148	ver = ioread32(tgpio->membase + TGPIO_VER);
8c35c89a RR	149
35570ac6 RR	150	spin_lock_irqsave(&tgpio->lock, flags);
	151
	152	lvr = ioread32(tgpio->membase + TGPIO_LVR);
	153	flr = ioread32(tgpio->membase + TGPIO_FLR);
8c35c89a RR	154	if (ver > 2)
8c35c89a RR	155	bflr = ioread32(tgpio->membase + TGPIO_BFLR);
35570ac6 RR	156
35570ac6 RR	157	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
8c35c89a	158	bflr &= ~(1 << offset);
35570ac6 RR	159	flr &= ~(1 << offset);
	160	if (trigger & IRQ_TYPE_LEVEL_HIGH)
	161	lvr \|= 1 << offset;
	162	else
	163	lvr &= ~(1 << offset);
	164	}
	165
8c35c89a	166	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
2a481800 JL	167	if (ver < 3) {
	168	ret = -EINVAL;
	169	goto out;
8a29a409	170	} else {
8c35c89a RR	171	flr \|= 1 << offset;
	172	bflr \|= 1 << offset;
	173	}
	174	} else {
	175	bflr &= ~(1 << offset);
35570ac6	176	flr \|= 1 << offset;
35570ac6	177	if (trigger & IRQ_TYPE_EDGE_FALLING)
35570ac6	178	lvr &= ~(1 << offset);
8c35c89a RR	179	else
8c35c89a RR	180	lvr \|= 1 << offset;
35570ac6 RR	181	}
	182
	183	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
	184	iowrite32(flr, tgpio->membase + TGPIO_FLR);
8c35c89a RR	185	if (ver > 2)
	186	iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
	187
35570ac6	188	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
35570ac6	189
2a481800 JL	190	out:
	191	spin_unlock_irqrestore(&tgpio->lock, flags);
	192	return ret;
35570ac6 RR	193	}
35570ac6 RR	194
bd0b9ac4	195	static void timbgpio_irq(struct irq_desc *desc)
35570ac6	196	{
476f8b4c JL	197	struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
476f8b4c JL	198	struct irq_data *data = irq_desc_get_irq_data(desc);
35570ac6 RR	199	unsigned long ipr;
	200	int offset;
	201
476f8b4c	202	data->chip->irq_ack(data);
35570ac6 RR	203	ipr = ioread32(tgpio->membase + TGPIO_IPR);
	204	iowrite32(ipr, tgpio->membase + TGPIO_ICR);
	205
76d800a5 TH	206	/*
	207	* Some versions of the hardware trash the IER register if more than
	208	* one interrupt is received simultaneously.
	209	*/
	210	iowrite32(0, tgpio->membase + TGPIO_IER);
	211
984b3f57	212	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
35570ac6	213	generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
76d800a5 TH	214
76d800a5 TH	215	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
35570ac6 RR	216	}
	217
	218	static struct irq_chip timbgpio_irqchip = {
	219	.name = "GPIO",
a1f5f22a LB	220	.irq_enable = timbgpio_irq_enable,
	221	.irq_disable = timbgpio_irq_disable,
	222	.irq_set_type = timbgpio_irq_type,
35570ac6 RR	223	};
35570ac6 RR	224
3836309d	225	static int timbgpio_probe(struct platform_device *pdev)
35570ac6 RR	226	{
35570ac6 RR	227	int err, i;
0ed3398e	228	struct device *dev = &pdev->dev;
35570ac6 RR	229	struct gpio_chip *gc;
	230	struct timbgpio *tgpio;
	231	struct resource *iomem;
e56aee18	232	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
35570ac6 RR	233	int irq = platform_get_irq(pdev, 0);
	234
	235	if (!pdata \|\| pdata->nr_pins > 32) {
0ed3398e	236	dev_err(dev, "Invalid platform data\n");
0ed3398e	237	return -EINVAL;
35570ac6 RR	238	}
35570ac6 RR	239
0ed3398e	240	tgpio = devm_kzalloc(dev, sizeof(struct timbgpio), GFP_KERNEL);
35570ac6	241	if (!tgpio) {
0ed3398e	242	dev_err(dev, "Memory alloc failed\n");
0ed3398e	243	return -EINVAL;
35570ac6 RR	244	}
	245	tgpio->irq_base = pdata->irq_base;
	246
	247	spin_lock_init(&tgpio->lock);
	248
fa283db7 AKC	249	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	250	tgpio->membase = devm_ioremap_resource(dev, iomem);
	251	if (IS_ERR(tgpio->membase))
	252	return PTR_ERR(tgpio->membase);
35570ac6 RR	253
	254	gc = &tgpio->gpio;
	255
	256	gc->label = dev_name(&pdev->dev);
	257	gc->owner = THIS_MODULE;
58383c78	258	gc->parent = &pdev->dev;
35570ac6 RR	259	gc->direction_input = timbgpio_gpio_direction_input;
	260	gc->get = timbgpio_gpio_get;
	261	gc->direction_output = timbgpio_gpio_direction_output;
	262	gc->set = timbgpio_gpio_set;
	263	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	264	gc->dbg_show = NULL;
	265	gc->base = pdata->gpio_base;
	266	gc->ngpio = pdata->nr_pins;
9fb1f39e	267	gc->can_sleep = false;
35570ac6	268
43fad832	269	err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
35570ac6	270	if (err)
0ed3398e	271	return err;
35570ac6 RR	272
	273	platform_set_drvdata(pdev, tgpio);
	274
	275	/* make sure to disable interrupts */
	276	iowrite32(0x0, tgpio->membase + TGPIO_IER);
	277
	278	if (irq < 0 \|\| tgpio->irq_base <= 0)
	279	return 0;
	280
	281	for (i = 0; i < pdata->nr_pins; i++) {
e5428a68 LW	282	irq_set_chip_and_handler(tgpio->irq_base + i,
e5428a68 LW	283	&timbgpio_irqchip, handle_simple_irq);
b51804bc	284	irq_set_chip_data(tgpio->irq_base + i, tgpio);
23393d49	285	irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST \| IRQ_NOPROBE);
35570ac6 RR	286	}
35570ac6 RR	287
8a52211a	288	irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
35570ac6 RR	289
35570ac6 RR	290	return 0;
35570ac6 RR	291	}
35570ac6 RR	292
206210ce	293	static int timbgpio_remove(struct platform_device *pdev)
35570ac6	294	{
e56aee18	295	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
35570ac6	296	struct timbgpio *tgpio = platform_get_drvdata(pdev);
35570ac6 RR	297	int irq = platform_get_irq(pdev, 0);
	298
	299	if (irq >= 0 && tgpio->irq_base > 0) {
	300	int i;
3271d382	301	for (i = 0; i < pdata->nr_pins; i++) {
b51804bc TG	302	irq_set_chip(tgpio->irq_base + i, NULL);
b51804bc TG	303	irq_set_chip_data(tgpio->irq_base + i, NULL);
35570ac6 RR	304	}
35570ac6 RR	305
b51804bc TG	306	irq_set_handler(irq, NULL);
b51804bc TG	307	irq_set_handler_data(irq, NULL);
35570ac6 RR	308	}
35570ac6 RR	309
35570ac6 RR	310	return 0;
	311	}
	312
	313	static struct platform_driver timbgpio_platform_driver = {
	314	.driver = {
	315	.name = DRIVER_NAME,
35570ac6 RR	316	},
	317	.probe = timbgpio_probe,
	318	.remove = timbgpio_remove,
	319	};
	320
	321	/--------------------------------------------------------------------------/
	322
6f61415e	323	module_platform_driver(timbgpio_platform_driver);
35570ac6 RR	324
	325	MODULE_DESCRIPTION("Timberdale GPIO driver");
	326	MODULE_LICENSE("GPL v2");
	327	MODULE_AUTHOR("Mocean Laboratories");
	328	MODULE_ALIAS("platform:"DRIVER_NAME);
	329