[linux-2.6-block.git] / drivers / gpio / gpio-sx150x.c

/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 */
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/i2c/sx150x.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/of_device.h>

#define NO_UPDATE_PENDING	-1

/* The chip models of sx150x */
#define SX150X_123 0
#define SX150X_456 1
#define SX150X_789 2

struct sx150x_123_pri {
	u8 reg_pld_mode;
	u8 reg_pld_table0;
	u8 reg_pld_table1;
	u8 reg_pld_table2;
	u8 reg_pld_table3;
	u8 reg_pld_table4;
	u8 reg_advance;
};

struct sx150x_456_pri {
	u8 reg_pld_mode;
	u8 reg_pld_table0;
	u8 reg_pld_table1;
	u8 reg_pld_table2;
	u8 reg_pld_table3;
	u8 reg_pld_table4;
	u8 reg_advance;
};

struct sx150x_789_pri {
	u8 reg_drain;
	u8 reg_polarity;
	u8 reg_clock;
	u8 reg_misc;
	u8 reg_reset;
	u8 ngpios;
};

struct sx150x_device_data {
	u8 model;
	u8 reg_pullup;
	u8 reg_pulldn;
	u8 reg_dir;
	u8 reg_data;
	u8 reg_irq_mask;
	u8 reg_irq_src;
	u8 reg_sense;
	u8 ngpios;
	union {
		struct sx150x_123_pri x123;
		struct sx150x_456_pri x456;
		struct sx150x_789_pri x789;
	} pri;
};

struct sx150x_chip {
	struct gpio_chip                 gpio_chip;
	struct i2c_client               *client;
	const struct sx150x_device_data *dev_cfg;
	int                              irq_summary;
	int                              irq_base;
	int				 irq_update;
	u32                              irq_sense;
	u32				 irq_masked;
	u32				 dev_sense;
	u32				 dev_masked;
	struct irq_chip                  irq_chip;
	struct mutex                     lock;
};

static const struct sx150x_device_data sx150x_devices[] = {
	[0] = { /* sx1508q */
		.model = SX150X_789,
		.reg_pullup	= 0x03,
		.reg_pulldn	= 0x04,
		.reg_dir	= 0x07,
		.reg_data	= 0x08,
		.reg_irq_mask	= 0x09,
		.reg_irq_src	= 0x0c,
		.reg_sense	= 0x0b,
		.pri.x789 = {
			.reg_drain	= 0x05,
			.reg_polarity	= 0x06,
			.reg_clock	= 0x0f,
			.reg_misc	= 0x10,
			.reg_reset	= 0x7d,
		},
		.ngpios = 8,
	},
	[1] = { /* sx1509q */
		.model = SX150X_789,
		.reg_pullup	= 0x07,
		.reg_pulldn	= 0x09,
		.reg_dir	= 0x0f,
		.reg_data	= 0x11,
		.reg_irq_mask	= 0x13,
		.reg_irq_src	= 0x19,
		.reg_sense	= 0x17,
		.pri.x789 = {
			.reg_drain	= 0x0b,
			.reg_polarity	= 0x0d,
			.reg_clock	= 0x1e,
			.reg_misc	= 0x1f,
			.reg_reset	= 0x7d,
		},
		.ngpios	= 16
	},
	[2] = { /* sx1506q */
		.model = SX150X_456,
		.reg_pullup	= 0x05,
		.reg_pulldn	= 0x07,
		.reg_dir	= 0x03,
		.reg_data	= 0x01,
		.reg_irq_mask	= 0x09,
		.reg_irq_src	= 0x0f,
		.reg_sense	= 0x0d,
		.pri.x456 = {
			.reg_pld_mode	= 0x21,
			.reg_pld_table0	= 0x23,
			.reg_pld_table1	= 0x25,
			.reg_pld_table2	= 0x27,
			.reg_pld_table3	= 0x29,
			.reg_pld_table4	= 0x2b,
			.reg_advance	= 0xad,
		},
		.ngpios	= 16
	},
	[3] = { /* sx1502q */
		.model = SX150X_123,
		.reg_pullup	= 0x02,
		.reg_pulldn	= 0x03,
		.reg_dir	= 0x01,
		.reg_data	= 0x00,
		.reg_irq_mask	= 0x05,
		.reg_irq_src	= 0x08,
		.reg_sense	= 0x07,
		.pri.x123 = {
			.reg_pld_mode	= 0x10,
			.reg_pld_table0	= 0x11,
			.reg_pld_table1	= 0x12,
			.reg_pld_table2	= 0x13,
			.reg_pld_table3	= 0x14,
			.reg_pld_table4	= 0x15,
			.reg_advance	= 0xad,
		},
		.ngpios	= 8,
	},
};

static const struct i2c_device_id sx150x_id[] = {
	{"sx1508q", 0},
	{"sx1509q", 1},
	{"sx1506q", 2},
	{"sx1502q", 3},
	{}
};
MODULE_DEVICE_TABLE(i2c, sx150x_id);

static const struct of_device_id sx150x_of_match[] = {
	{ .compatible = "semtech,sx1508q" },
	{ .compatible = "semtech,sx1509q" },
	{ .compatible = "semtech,sx1506q" },
	{ .compatible = "semtech,sx1502q" },
	{},
};
MODULE_DEVICE_TABLE(of, sx150x_of_match);

static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val)
{
	s32 err = i2c_smbus_write_byte_data(client, reg, val);

	if (err < 0)
		dev_warn(&client->dev,
			"i2c write fail: can't write %02x to %02x: %d\n",
			val, reg, err);
	return err;
}

static s32 sx150x_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
{
	s32 err = i2c_smbus_read_byte_data(client, reg);

	if (err >= 0)
		*val = err;
	else
		dev_warn(&client->dev,
			"i2c read fail: can't read from %02x: %d\n",
			reg, err);
	return err;
}

static inline bool offset_is_oscio(struct sx150x_chip *chip, unsigned offset)
{
	return (chip->dev_cfg->ngpios == offset);
}

/*
 * These utility functions solve the common problem of locating and setting
 * configuration bits.  Configuration bits are grouped into registers
 * whose indexes increase downwards.  For example, with eight-bit registers,
 * sixteen gpios would have their config bits grouped in the following order:
 * REGISTER N-1 [ f e d c b a 9 8 ]
 *          N   [ 7 6 5 4 3 2 1 0 ]
 *
 * For multi-bit configurations, the pattern gets wider:
 * REGISTER N-3 [ f f e e d d c c ]
 *          N-2 [ b b a a 9 9 8 8 ]
 *          N-1 [ 7 7 6 6 5 5 4 4 ]
 *          N   [ 3 3 2 2 1 1 0 0 ]
 *
 * Given the address of the starting register 'N', the index of the gpio
 * whose configuration we seek to change, and the width in bits of that
 * configuration, these functions allow us to locate the correct
 * register and mask the correct bits.
 */
static inline void sx150x_find_cfg(u8 offset, u8 width,
				u8 *reg, u8 *mask, u8 *shift)
{
	*reg   -= offset * width / 8;
	*mask   = (1 << width) - 1;
	*shift  = (offset * width) % 8;
	*mask <<= *shift;
}

static s32 sx150x_write_cfg(struct sx150x_chip *chip,
			u8 offset, u8 width, u8 reg, u8 val)
{
	u8  mask;
	u8  data;
	u8  shift;
	s32 err;

	sx150x_find_cfg(offset, width, &reg, &mask, &shift);
	err = sx150x_i2c_read(chip->client, reg, &data);
	if (err < 0)
		return err;

	data &= ~mask;
	data |= (val << shift) & mask;
	return sx150x_i2c_write(chip->client, reg, data);
}

static int sx150x_get_io(struct sx150x_chip *chip, unsigned offset)
{
	u8  reg = chip->dev_cfg->reg_data;
	u8  mask;
	u8  data;
	u8  shift;
	s32 err;

	sx150x_find_cfg(offset, 1, &reg, &mask, &shift);
	err = sx150x_i2c_read(chip->client, reg, &data);
	if (err >= 0)
		err = (data & mask) != 0 ? 1 : 0;

	return err;
}

static void sx150x_set_oscio(struct sx150x_chip *chip, int val)
{
	sx150x_i2c_write(chip->client,
			chip->dev_cfg->pri.x789.reg_clock,
			(val ? 0x1f : 0x10));
}

static void sx150x_set_io(struct sx150x_chip *chip, unsigned offset, int val)
{
	sx150x_write_cfg(chip,
			offset,
			1,
			chip->dev_cfg->reg_data,
			(val ? 1 : 0));
}

static int sx150x_io_input(struct sx150x_chip *chip, unsigned offset)
{
	return sx150x_write_cfg(chip,
				offset,
				1,
				chip->dev_cfg->reg_dir,
				1);
}

static int sx150x_io_output(struct sx150x_chip *chip, unsigned offset, int val)
{
	int err;

	err = sx150x_write_cfg(chip,
			offset,
			1,
			chip->dev_cfg->reg_data,
			(val ? 1 : 0));
	if (err >= 0)
		err = sx150x_write_cfg(chip,
				offset,
				1,
				chip->dev_cfg->reg_dir,
				0);
	return err;
}

static int sx150x_gpio_get(struct gpio_chip *gc, unsigned offset)
{
	struct sx150x_chip *chip = gpiochip_get_data(gc);
	int status = -EINVAL;

	if (!offset_is_oscio(chip, offset)) {
		mutex_lock(&chip->lock);
		status = sx150x_get_io(chip, offset);
		mutex_unlock(&chip->lock);
	}

	return (status < 0) ? status : !!status;
}

static void sx150x_gpio_set(struct gpio_chip *gc, unsigned offset, int val)
{
	struct sx150x_chip *chip = gpiochip_get_data(gc);

	mutex_lock(&chip->lock);
	if (offset_is_oscio(chip, offset))
		sx150x_set_oscio(chip, val);
	else
		sx150x_set_io(chip, offset, val);
	mutex_unlock(&chip->lock);
}

static int sx150x_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct sx150x_chip *chip = gpiochip_get_data(gc);
	int status = -EINVAL;

	if (!offset_is_oscio(chip, offset)) {
		mutex_lock(&chip->lock);
		status = sx150x_io_input(chip, offset);
		mutex_unlock(&chip->lock);
	}
	return status;
}

static int sx150x_gpio_direction_output(struct gpio_chip *gc,
					unsigned offset,
					int val)
{
	struct sx150x_chip *chip = gpiochip_get_data(gc);
	int status = 0;

	if (!offset_is_oscio(chip, offset)) {
		mutex_lock(&chip->lock);
		status = sx150x_io_output(chip, offset, val);
		mutex_unlock(&chip->lock);
	}
	return status;
}

static void sx150x_irq_mask(struct irq_data *d)
{
	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	unsigned n = d->hwirq;

	chip->irq_masked |= (1 << n);
	chip->irq_update = n;
}

static void sx150x_irq_unmask(struct irq_data *d)
{
	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	unsigned n = d->hwirq;

	chip->irq_masked &= ~(1 << n);
	chip->irq_update = n;
}

static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	unsigned n, val = 0;

	if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
		return -EINVAL;

	n = d->hwirq;

	if (flow_type & IRQ_TYPE_EDGE_RISING)
		val |= 0x1;
	if (flow_type & IRQ_TYPE_EDGE_FALLING)
		val |= 0x2;

	chip->irq_sense &= ~(3UL << (n * 2));
	chip->irq_sense |= val << (n * 2);
	chip->irq_update = n;
	return 0;
}

static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
{
	struct sx150x_chip *chip = (struct sx150x_chip *)dev_id;
	unsigned nhandled = 0;
	unsigned sub_irq;
	unsigned n;
	s32 err;
	u8 val;
	int i;

	for (i = (chip->dev_cfg->ngpios / 8) - 1; i >= 0; --i) {
		err = sx150x_i2c_read(chip->client,
				      chip->dev_cfg->reg_irq_src - i,
				      &val);
		if (err < 0)
			continue;

		sx150x_i2c_write(chip->client,
				chip->dev_cfg->reg_irq_src - i,
				val);
		for (n = 0; n < 8; ++n) {
			if (val & (1 << n)) {
				sub_irq = irq_find_mapping(
					chip->gpio_chip.irqdomain,
					(i * 8) + n);
				handle_nested_irq(sub_irq);
				++nhandled;
			}
		}
	}

	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

static void sx150x_irq_bus_lock(struct irq_data *d)
{
	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));

	mutex_lock(&chip->lock);
}

static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
{
	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	unsigned n;

	if (chip->irq_update == NO_UPDATE_PENDING)
		goto out;

	n = chip->irq_update;
	chip->irq_update = NO_UPDATE_PENDING;

	/* Avoid updates if nothing changed */
	if (chip->dev_sense == chip->irq_sense &&
	    chip->dev_masked == chip->irq_masked)
		goto out;

	chip->dev_sense = chip->irq_sense;
	chip->dev_masked = chip->irq_masked;

	if (chip->irq_masked & (1 << n)) {
		sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
		sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
	} else {
		sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
		sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
				 chip->irq_sense >> (n * 2));
	}
out:
	mutex_unlock(&chip->lock);
}

static void sx150x_init_chip(struct sx150x_chip *chip,
			struct i2c_client *client,
			kernel_ulong_t driver_data,
			struct sx150x_platform_data *pdata)
{
	mutex_init(&chip->lock);

	chip->client                     = client;
	chip->dev_cfg                    = &sx150x_devices[driver_data];
	chip->gpio_chip.parent              = &client->dev;
	chip->gpio_chip.label            = client->name;
	chip->gpio_chip.direction_input  = sx150x_gpio_direction_input;
	chip->gpio_chip.direction_output = sx150x_gpio_direction_output;
	chip->gpio_chip.get              = sx150x_gpio_get;
	chip->gpio_chip.set              = sx150x_gpio_set;
	chip->gpio_chip.base             = pdata->gpio_base;
	chip->gpio_chip.can_sleep        = true;
	chip->gpio_chip.ngpio            = chip->dev_cfg->ngpios;
#ifdef CONFIG_OF_GPIO
	chip->gpio_chip.of_node          = client->dev.of_node;
	chip->gpio_chip.of_gpio_n_cells  = 2;
#endif
	if (pdata->oscio_is_gpo)
		++chip->gpio_chip.ngpio;

	chip->irq_chip.name                = client->name;
	chip->irq_chip.irq_mask            = sx150x_irq_mask;
	chip->irq_chip.irq_unmask          = sx150x_irq_unmask;
	chip->irq_chip.irq_set_type        = sx150x_irq_set_type;
	chip->irq_chip.irq_bus_lock        = sx150x_irq_bus_lock;
	chip->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
	chip->irq_summary                  = -1;
	chip->irq_base                     = -1;
	chip->irq_masked                   = ~0;
	chip->irq_sense                    = 0;
	chip->dev_masked                   = ~0;
	chip->dev_sense                    = 0;
	chip->irq_update		   = NO_UPDATE_PENDING;
}

static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
{
	int err = 0;
	unsigned n;

	for (n = 0; err >= 0 && n < (chip->dev_cfg->ngpios / 8); ++n)
		err = sx150x_i2c_write(chip->client, base - n, cfg >> (n * 8));
	return err;
}

static int sx150x_reset(struct sx150x_chip *chip)
{
	int err;

	err = i2c_smbus_write_byte_data(chip->client,
					chip->dev_cfg->pri.x789.reg_reset,
					0x12);
	if (err < 0)
		return err;

	err = i2c_smbus_write_byte_data(chip->client,
					chip->dev_cfg->pri.x789.reg_reset,
					0x34);
	return err;
}

static int sx150x_init_hw(struct sx150x_chip *chip,
			struct sx150x_platform_data *pdata)
{
	int err = 0;

	if (pdata->reset_during_probe) {
		err = sx150x_reset(chip);
		if (err < 0)
			return err;
	}

	if (chip->dev_cfg->model == SX150X_789)
		err = sx150x_i2c_write(chip->client,
				chip->dev_cfg->pri.x789.reg_misc,
				0x01);
	else if (chip->dev_cfg->model == SX150X_456)
		err = sx150x_i2c_write(chip->client,
				chip->dev_cfg->pri.x456.reg_advance,
				0x04);
	else
		err = sx150x_i2c_write(chip->client,
				chip->dev_cfg->pri.x123.reg_advance,
				0x00);
	if (err < 0)
		return err;

	err = sx150x_init_io(chip, chip->dev_cfg->reg_pullup,
			pdata->io_pullup_ena);
	if (err < 0)
		return err;

	err = sx150x_init_io(chip, chip->dev_cfg->reg_pulldn,
			pdata->io_pulldn_ena);
	if (err < 0)
		return err;

	if (chip->dev_cfg->model == SX150X_789) {
		err = sx150x_init_io(chip,
				chip->dev_cfg->pri.x789.reg_drain,
				pdata->io_open_drain_ena);
		if (err < 0)
			return err;

		err = sx150x_init_io(chip,
				chip->dev_cfg->pri.x789.reg_polarity,
				pdata->io_polarity);
		if (err < 0)
			return err;
	} else if (chip->dev_cfg->model == SX150X_456) {
		/* Set all pins to work in normal mode */
		err = sx150x_init_io(chip,
				chip->dev_cfg->pri.x456.reg_pld_mode,
				0);
		if (err < 0)
			return err;
	} else {
		/* Set all pins to work in normal mode */
		err = sx150x_init_io(chip,
				chip->dev_cfg->pri.x123.reg_pld_mode,
				0);
		if (err < 0)
			return err;
	}


	if (pdata->oscio_is_gpo)
		sx150x_set_oscio(chip, 0);

	return err;
}

static int sx150x_install_irq_chip(struct sx150x_chip *chip,
				int irq_summary,
				int irq_base)
{
	int err;

	chip->irq_summary = irq_summary;
	chip->irq_base    = irq_base;

	/* Add gpio chip to irq subsystem */
	err = gpiochip_irqchip_add(&chip->gpio_chip,
		&chip->irq_chip, chip->irq_base,
		handle_edge_irq, IRQ_TYPE_EDGE_BOTH);
	if (err) {
		dev_err(&chip->client->dev,
			"could not connect irqchip to gpiochip\n");
		return  err;
	}

	err = devm_request_threaded_irq(&chip->client->dev,
			irq_summary, NULL, sx150x_irq_thread_fn,
			IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_FALLING,
			chip->irq_chip.name, chip);
	if (err < 0) {
		chip->irq_summary = -1;
		chip->irq_base    = -1;
	}

	return err;
}

static int sx150x_probe(struct i2c_client *client,
				const struct i2c_device_id *id)
{
	static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
				     I2C_FUNC_SMBUS_WRITE_WORD_DATA;
	struct sx150x_platform_data *pdata;
	struct sx150x_chip *chip;
	int rc;

	pdata = dev_get_platdata(&client->dev);
	if (!pdata)
		return -EINVAL;

	if (!i2c_check_functionality(client->adapter, i2c_funcs))
		return -ENOSYS;

	chip = devm_kzalloc(&client->dev,
		sizeof(struct sx150x_chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	sx150x_init_chip(chip, client, id->driver_data, pdata);
	rc = sx150x_init_hw(chip, pdata);
	if (rc < 0)
		return rc;

	rc = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
	if (rc)
		return rc;

	if (pdata->irq_summary >= 0) {
		rc = sx150x_install_irq_chip(chip,
					pdata->irq_summary,
					pdata->irq_base);
		if (rc < 0)
			return rc;
	}

	i2c_set_clientdata(client, chip);

	return 0;
}

static struct i2c_driver sx150x_driver = {
	.driver = {
		.name = "sx150x",
		.of_match_table = of_match_ptr(sx150x_of_match),
	},
	.probe    = sx150x_probe,
	.id_table = sx150x_id,
};

static int __init sx150x_init(void)
{
	return i2c_add_driver(&sx150x_driver);
}
subsys_initcall(sx150x_init);

static void __exit sx150x_exit(void)
{
	return i2c_del_driver(&sx150x_driver);
}
module_exit(sx150x_exit);

MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
MODULE_DESCRIPTION("Driver for Semtech SX150X I2C GPIO Expanders");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
c34f16b7 GB	1	/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	15	* 02110-1301, USA.
	16	*/
	17	#include <linux/gpio.h>
	18	#include <linux/i2c.h>
	19	#include <linux/init.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/irq.h>
	22	#include <linux/module.h>
	23	#include <linux/mutex.h>
	24	#include <linux/slab.h>
c34f16b7	25	#include <linux/i2c/sx150x.h>
04d2264c WC	26	#include <linux/of.h>
	27	#include <linux/of_address.h>
	28	#include <linux/of_irq.h>
	29	#include <linux/of_gpio.h>
	30	#include <linux/of_device.h>
c34f16b7	31
0ff56cd8 TG	32	#define NO_UPDATE_PENDING -1
0ff56cd8 TG	33
ae9ca493	34	/* The chip models of sx150x */
50e8df09 PR	35	#define SX150X_123 0
	36	#define SX150X_456 1
	37	#define SX150X_789 2
	38
	39	struct sx150x_123_pri {
	40	u8 reg_pld_mode;
	41	u8 reg_pld_table0;
	42	u8 reg_pld_table1;
	43	u8 reg_pld_table2;
	44	u8 reg_pld_table3;
	45	u8 reg_pld_table4;
	46	u8 reg_advance;
	47	};
ae9ca493 WC	48
	49	struct sx150x_456_pri {
	50	u8 reg_pld_mode;
	51	u8 reg_pld_table0;
	52	u8 reg_pld_table1;
	53	u8 reg_pld_table2;
	54	u8 reg_pld_table3;
	55	u8 reg_pld_table4;
	56	u8 reg_advance;
	57	};
	58
	59	struct sx150x_789_pri {
	60	u8 reg_drain;
	61	u8 reg_polarity;
	62	u8 reg_clock;
	63	u8 reg_misc;
	64	u8 reg_reset;
	65	u8 ngpios;
	66	};
	67
c34f16b7	68	struct sx150x_device_data {
ae9ca493	69	u8 model;
c34f16b7 GB	70	u8 reg_pullup;
c34f16b7 GB	71	u8 reg_pulldn;
c34f16b7 GB	72	u8 reg_dir;
	73	u8 reg_data;
	74	u8 reg_irq_mask;
	75	u8 reg_irq_src;
	76	u8 reg_sense;
c34f16b7	77	u8 ngpios;
ae9ca493	78	union {
50e8df09	79	struct sx150x_123_pri x123;
ae9ca493 WC	80	struct sx150x_456_pri x456;
	81	struct sx150x_789_pri x789;
	82	} pri;
c34f16b7 GB	83	};
	84
	85	struct sx150x_chip {
	86	struct gpio_chip gpio_chip;
	87	struct i2c_client *client;
	88	const struct sx150x_device_data *dev_cfg;
	89	int irq_summary;
	90	int irq_base;
0ff56cd8	91	int irq_update;
c34f16b7	92	u32 irq_sense;
0ff56cd8 TG	93	u32 irq_masked;
	94	u32 dev_sense;
	95	u32 dev_masked;
c34f16b7 GB	96	struct irq_chip irq_chip;
	97	struct mutex lock;
	98	};
	99
	100	static const struct sx150x_device_data sx150x_devices[] = {
	101	[0] = { /* sx1508q */
ae9ca493 WC	102	.model = SX150X_789,
	103	.reg_pullup = 0x03,
	104	.reg_pulldn = 0x04,
	105	.reg_dir = 0x07,
	106	.reg_data = 0x08,
	107	.reg_irq_mask = 0x09,
	108	.reg_irq_src = 0x0c,
	109	.reg_sense = 0x0b,
	110	.pri.x789 = {
	111	.reg_drain = 0x05,
	112	.reg_polarity = 0x06,
	113	.reg_clock = 0x0f,
	114	.reg_misc = 0x10,
	115	.reg_reset = 0x7d,
	116	},
	117	.ngpios = 8,
c34f16b7 GB	118	},
c34f16b7 GB	119	[1] = { /* sx1509q */
ae9ca493 WC	120	.model = SX150X_789,
	121	.reg_pullup = 0x07,
	122	.reg_pulldn = 0x09,
	123	.reg_dir = 0x0f,
	124	.reg_data = 0x11,
	125	.reg_irq_mask = 0x13,
	126	.reg_irq_src = 0x19,
	127	.reg_sense = 0x17,
	128	.pri.x789 = {
	129	.reg_drain = 0x0b,
	130	.reg_polarity = 0x0d,
	131	.reg_clock = 0x1e,
	132	.reg_misc = 0x1f,
	133	.reg_reset = 0x7d,
	134	},
	135	.ngpios = 16
	136	},
	137	[2] = { /* sx1506q */
	138	.model = SX150X_456,
	139	.reg_pullup = 0x05,
	140	.reg_pulldn = 0x07,
	141	.reg_dir = 0x03,
	142	.reg_data = 0x01,
	143	.reg_irq_mask = 0x09,
	144	.reg_irq_src = 0x0f,
	145	.reg_sense = 0x0d,
	146	.pri.x456 = {
	147	.reg_pld_mode = 0x21,
	148	.reg_pld_table0 = 0x23,
	149	.reg_pld_table1 = 0x25,
	150	.reg_pld_table2 = 0x27,
	151	.reg_pld_table3 = 0x29,
	152	.reg_pld_table4 = 0x2b,
	153	.reg_advance = 0xad,
	154	},
	155	.ngpios = 16
c34f16b7	156	},
50e8df09 PR	157	[3] = { /* sx1502q */
	158	.model = SX150X_123,
	159	.reg_pullup = 0x02,
	160	.reg_pulldn = 0x03,
	161	.reg_dir = 0x01,
	162	.reg_data = 0x00,
	163	.reg_irq_mask = 0x05,
	164	.reg_irq_src = 0x08,
	165	.reg_sense = 0x07,
	166	.pri.x123 = {
	167	.reg_pld_mode = 0x10,
	168	.reg_pld_table0 = 0x11,
	169	.reg_pld_table1 = 0x12,
	170	.reg_pld_table2 = 0x13,
	171	.reg_pld_table3 = 0x14,
	172	.reg_pld_table4 = 0x15,
	173	.reg_advance = 0xad,
	174	},
	175	.ngpios = 8,
	176	},
c34f16b7 GB	177	};
	178
	179	static const struct i2c_device_id sx150x_id[] = {
	180	{"sx1508q", 0},
	181	{"sx1509q", 1},
ae9ca493	182	{"sx1506q", 2},
50e8df09	183	{"sx1502q", 3},
c34f16b7 GB	184	{}
	185	};
	186	MODULE_DEVICE_TABLE(i2c, sx150x_id);
	187
16858cc5	188	static const struct of_device_id sx150x_of_match[] = {
04d2264c WC	189	{ .compatible = "semtech,sx1508q" },
	190	{ .compatible = "semtech,sx1509q" },
	191	{ .compatible = "semtech,sx1506q" },
50e8df09	192	{ .compatible = "semtech,sx1502q" },
04d2264c WC	193	{},
04d2264c WC	194	};
16858cc5	195	MODULE_DEVICE_TABLE(of, sx150x_of_match);
04d2264c	196
c34f16b7 GB	197	static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val)
	198	{
	199	s32 err = i2c_smbus_write_byte_data(client, reg, val);
	200
	201	if (err < 0)
	202	dev_warn(&client->dev,
	203	"i2c write fail: can't write %02x to %02x: %d\n",
	204	val, reg, err);
	205	return err;
	206	}
	207
	208	static s32 sx150x_i2c_read(struct i2c_client client, u8 reg, u8 val)
	209	{
	210	s32 err = i2c_smbus_read_byte_data(client, reg);
	211
	212	if (err >= 0)
	213	*val = err;
	214	else
	215	dev_warn(&client->dev,
	216	"i2c read fail: can't read from %02x: %d\n",
	217	reg, err);
	218	return err;
	219	}
	220
	221	static inline bool offset_is_oscio(struct sx150x_chip *chip, unsigned offset)
	222	{
	223	return (chip->dev_cfg->ngpios == offset);
	224	}
	225
	226	/*
	227	* These utility functions solve the common problem of locating and setting
	228	* configuration bits. Configuration bits are grouped into registers
	229	* whose indexes increase downwards. For example, with eight-bit registers,
	230	* sixteen gpios would have their config bits grouped in the following order:
	231	* REGISTER N-1 [ f e d c b a 9 8 ]
	232	* N [ 7 6 5 4 3 2 1 0 ]
	233	*
	234	* For multi-bit configurations, the pattern gets wider:
	235	* REGISTER N-3 [ f f e e d d c c ]
	236	* N-2 [ b b a a 9 9 8 8 ]
	237	* N-1 [ 7 7 6 6 5 5 4 4 ]
	238	* N [ 3 3 2 2 1 1 0 0 ]
	239	*
	240	* Given the address of the starting register 'N', the index of the gpio
	241	* whose configuration we seek to change, and the width in bits of that
	242	* configuration, these functions allow us to locate the correct
	243	* register and mask the correct bits.
	244	*/
	245	static inline void sx150x_find_cfg(u8 offset, u8 width,
	246	u8 reg, u8 mask, u8 *shift)
	247	{
	248	reg -= offset width / 8;
	249	*mask = (1 << width) - 1;
	250	shift = (offset width) % 8;
	251	mask <<= shift;
	252	}
	253
	254	static s32 sx150x_write_cfg(struct sx150x_chip *chip,
	255	u8 offset, u8 width, u8 reg, u8 val)
	256	{
	257	u8 mask;
	258	u8 data;
	259	u8 shift;
	260	s32 err;
261
262	sx150x_find_cfg(offset, width, &reg, &mask, &shift);
263	err = sx150x_i2c_read(chip->client, reg, &data);
264	if (err < 0)
265	return err;
266
267	data &= ~mask;
268	data \|= (val << shift) & mask;
269	return sx150x_i2c_write(chip->client, reg, data);
270	}
271
272	static int sx150x_get_io(struct sx150x_chip *chip, unsigned offset)
273	{
274	u8 reg = chip->dev_cfg->reg_data;
275	u8 mask;
276	u8 data;
277	u8 shift;
278	s32 err;
279
280	sx150x_find_cfg(offset, 1, &reg, &mask, &shift);
281	err = sx150x_i2c_read(chip->client, reg, &data);
282	if (err >= 0)
283	err = (data & mask) != 0 ? 1 : 0;
284
285	return err;
286	}
287
288	static void sx150x_set_oscio(struct sx150x_chip *chip, int val)
289	{
290	sx150x_i2c_write(chip->client,
ae9ca493	291	chip->dev_cfg->pri.x789.reg_clock,
c34f16b7 GB	292	(val ? 0x1f : 0x10));
	293	}
	294
	295	static void sx150x_set_io(struct sx150x_chip *chip, unsigned offset, int val)
	296	{
	297	sx150x_write_cfg(chip,
	298	offset,
	299	1,
	300	chip->dev_cfg->reg_data,
	301	(val ? 1 : 0));
	302	}
	303
	304	static int sx150x_io_input(struct sx150x_chip *chip, unsigned offset)
	305	{
	306	return sx150x_write_cfg(chip,
	307	offset,
	308	1,
	309	chip->dev_cfg->reg_dir,
	310	1);
	311	}
	312
	313	static int sx150x_io_output(struct sx150x_chip *chip, unsigned offset, int val)
	314	{
	315	int err;
	316
	317	err = sx150x_write_cfg(chip,
	318	offset,
	319	1,
	320	chip->dev_cfg->reg_data,
	321	(val ? 1 : 0));
	322	if (err >= 0)
	323	err = sx150x_write_cfg(chip,
	324	offset,
	325	1,
	326	chip->dev_cfg->reg_dir,
	327	0);
	328	return err;
	329	}
	330
	331	static int sx150x_gpio_get(struct gpio_chip *gc, unsigned offset)
	332	{
5b90b8c2	333	struct sx150x_chip *chip = gpiochip_get_data(gc);
c34f16b7 GB	334	int status = -EINVAL;
c34f16b7 GB	335
c34f16b7 GB	336	if (!offset_is_oscio(chip, offset)) {
	337	mutex_lock(&chip->lock);
	338	status = sx150x_get_io(chip, offset);
	339	mutex_unlock(&chip->lock);
	340	}
	341
f2e13d2f	342	return (status < 0) ? status : !!status;
c34f16b7 GB	343	}
	344
	345	static void sx150x_gpio_set(struct gpio_chip *gc, unsigned offset, int val)
	346	{
5b90b8c2	347	struct sx150x_chip *chip = gpiochip_get_data(gc);
c34f16b7 GB	348
	349	mutex_lock(&chip->lock);
	350	if (offset_is_oscio(chip, offset))
	351	sx150x_set_oscio(chip, val);
	352	else
	353	sx150x_set_io(chip, offset, val);
	354	mutex_unlock(&chip->lock);
	355	}
	356
	357	static int sx150x_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
	358	{
5b90b8c2	359	struct sx150x_chip *chip = gpiochip_get_data(gc);
c34f16b7 GB	360	int status = -EINVAL;
c34f16b7 GB	361
c34f16b7 GB	362	if (!offset_is_oscio(chip, offset)) {
	363	mutex_lock(&chip->lock);
	364	status = sx150x_io_input(chip, offset);
	365	mutex_unlock(&chip->lock);
	366	}
	367	return status;
	368	}
	369
	370	static int sx150x_gpio_direction_output(struct gpio_chip *gc,
	371	unsigned offset,
	372	int val)
	373	{
5b90b8c2	374	struct sx150x_chip *chip = gpiochip_get_data(gc);
c34f16b7 GB	375	int status = 0;
c34f16b7 GB	376
c34f16b7 GB	377	if (!offset_is_oscio(chip, offset)) {
	378	mutex_lock(&chip->lock);
	379	status = sx150x_io_output(chip, offset, val);
	380	mutex_unlock(&chip->lock);
	381	}
	382	return status;
	383	}
	384
673860c1	385	static void sx150x_irq_mask(struct irq_data *d)
c34f16b7	386	{
5b90b8c2	387	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
093e9435	388	unsigned n = d->hwirq;
c34f16b7	389
0ff56cd8 TG	390	chip->irq_masked \|= (1 << n);
0ff56cd8 TG	391	chip->irq_update = n;
c34f16b7 GB	392	}
c34f16b7 GB	393
673860c1	394	static void sx150x_irq_unmask(struct irq_data *d)
c34f16b7	395	{
5b90b8c2	396	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
093e9435	397	unsigned n = d->hwirq;
c34f16b7	398
0ff56cd8 TG	399	chip->irq_masked &= ~(1 << n);
0ff56cd8 TG	400	chip->irq_update = n;
c34f16b7 GB	401	}
c34f16b7 GB	402
673860c1	403	static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
c34f16b7	404	{
5b90b8c2	405	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
c34f16b7 GB	406	unsigned n, val = 0;
	407
	408	if (flow_type & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW))
	409	return -EINVAL;
	410
093e9435	411	n = d->hwirq;
c34f16b7 GB	412
	413	if (flow_type & IRQ_TYPE_EDGE_RISING)
	414	val \|= 0x1;
	415	if (flow_type & IRQ_TYPE_EDGE_FALLING)
	416	val \|= 0x2;
	417
	418	chip->irq_sense &= ~(3UL << (n * 2));
	419	chip->irq_sense \|= val << (n * 2);
0ff56cd8	420	chip->irq_update = n;
c34f16b7 GB	421	return 0;
	422	}
	423
	424	static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
	425	{
	426	struct sx150x_chip chip = (struct sx150x_chip )dev_id;
	427	unsigned nhandled = 0;
	428	unsigned sub_irq;
	429	unsigned n;
	430	s32 err;
	431	u8 val;
	432	int i;
	433
	434	for (i = (chip->dev_cfg->ngpios / 8) - 1; i >= 0; --i) {
	435	err = sx150x_i2c_read(chip->client,
	436	chip->dev_cfg->reg_irq_src - i,
	437	&val);
	438	if (err < 0)
	439	continue;
	440
	441	sx150x_i2c_write(chip->client,
	442	chip->dev_cfg->reg_irq_src - i,
	443	val);
	444	for (n = 0; n < 8; ++n) {
	445	if (val & (1 << n)) {
093e9435 WC	446	sub_irq = irq_find_mapping(
	447	chip->gpio_chip.irqdomain,
	448	(i * 8) + n);
c34f16b7 GB	449	handle_nested_irq(sub_irq);
	450	++nhandled;
	451	}
	452	}
	453	}
	454
	455	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
	456	}
	457
673860c1	458	static void sx150x_irq_bus_lock(struct irq_data *d)
c34f16b7	459	{
5b90b8c2	460	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
c34f16b7 GB	461
	462	mutex_lock(&chip->lock);
	463	}
	464
673860c1	465	static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
c34f16b7	466	{
5b90b8c2	467	struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
c34f16b7 GB	468	unsigned n;
c34f16b7 GB	469
0ff56cd8 TG	470	if (chip->irq_update == NO_UPDATE_PENDING)
	471	goto out;
	472
	473	n = chip->irq_update;
	474	chip->irq_update = NO_UPDATE_PENDING;
c34f16b7	475
0ff56cd8 TG	476	/* Avoid updates if nothing changed */
0ff56cd8 TG	477	if (chip->dev_sense == chip->irq_sense &&
aab0b129	478	chip->dev_masked == chip->irq_masked)
0ff56cd8 TG	479	goto out;
	480
	481	chip->dev_sense = chip->irq_sense;
	482	chip->dev_masked = chip->irq_masked;
	483
	484	if (chip->irq_masked & (1 << n)) {
	485	sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
	486	sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
	487	} else {
	488	sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
	489	sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
	490	chip->irq_sense >> (n * 2));
	491	}
	492	out:
c34f16b7 GB	493	mutex_unlock(&chip->lock);
	494	}
	495
	496	static void sx150x_init_chip(struct sx150x_chip *chip,
	497	struct i2c_client *client,
	498	kernel_ulong_t driver_data,
	499	struct sx150x_platform_data *pdata)
	500	{
	501	mutex_init(&chip->lock);
	502
	503	chip->client = client;
	504	chip->dev_cfg = &sx150x_devices[driver_data];
58383c78	505	chip->gpio_chip.parent = &client->dev;
c34f16b7 GB	506	chip->gpio_chip.label = client->name;
	507	chip->gpio_chip.direction_input = sx150x_gpio_direction_input;
	508	chip->gpio_chip.direction_output = sx150x_gpio_direction_output;
	509	chip->gpio_chip.get = sx150x_gpio_get;
	510	chip->gpio_chip.set = sx150x_gpio_set;
c34f16b7	511	chip->gpio_chip.base = pdata->gpio_base;
9fb1f39e	512	chip->gpio_chip.can_sleep = true;
c34f16b7	513	chip->gpio_chip.ngpio = chip->dev_cfg->ngpios;
16858cc5	514	#ifdef CONFIG_OF_GPIO
04d2264c WC	515	chip->gpio_chip.of_node = client->dev.of_node;
04d2264c WC	516	chip->gpio_chip.of_gpio_n_cells = 2;
16858cc5	517	#endif
c34f16b7 GB	518	if (pdata->oscio_is_gpo)
	519	++chip->gpio_chip.ngpio;
	520
673860c1 LB	521	chip->irq_chip.name = client->name;
	522	chip->irq_chip.irq_mask = sx150x_irq_mask;
	523	chip->irq_chip.irq_unmask = sx150x_irq_unmask;
	524	chip->irq_chip.irq_set_type = sx150x_irq_set_type;
	525	chip->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
	526	chip->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
	527	chip->irq_summary = -1;
	528	chip->irq_base = -1;
0ff56cd8	529	chip->irq_masked = ~0;
673860c1	530	chip->irq_sense = 0;
0ff56cd8 TG	531	chip->dev_masked = ~0;
	532	chip->dev_sense = 0;
	533	chip->irq_update = NO_UPDATE_PENDING;
c34f16b7 GB	534	}
	535
	536	static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
	537	{
	538	int err = 0;
	539	unsigned n;
	540
	541	for (n = 0; err >= 0 && n < (chip->dev_cfg->ngpios / 8); ++n)
	542	err = sx150x_i2c_write(chip->client, base - n, cfg >> (n * 8));
	543	return err;
	544	}
	545
5affb607	546	static int sx150x_reset(struct sx150x_chip *chip)
c34f16b7	547	{
5affb607	548	int err;
c34f16b7	549
5affb607	550	err = i2c_smbus_write_byte_data(chip->client,
ae9ca493	551	chip->dev_cfg->pri.x789.reg_reset,
5affb607	552	0x12);
c34f16b7 GB	553	if (err < 0)
	554	return err;
	555
5affb607	556	err = i2c_smbus_write_byte_data(chip->client,
ae9ca493	557	chip->dev_cfg->pri.x789.reg_reset,
5affb607 GB	558	0x34);
	559	return err;
	560	}
	561
	562	static int sx150x_init_hw(struct sx150x_chip *chip,
	563	struct sx150x_platform_data *pdata)
	564	{
	565	int err = 0;
	566
	567	if (pdata->reset_during_probe) {
	568	err = sx150x_reset(chip);
	569	if (err < 0)
	570	return err;
	571	}
	572
ae9ca493 WC	573	if (chip->dev_cfg->model == SX150X_789)
	574	err = sx150x_i2c_write(chip->client,
	575	chip->dev_cfg->pri.x789.reg_misc,
	576	0x01);
50e8df09	577	else if (chip->dev_cfg->model == SX150X_456)
ae9ca493 WC	578	err = sx150x_i2c_write(chip->client,
	579	chip->dev_cfg->pri.x456.reg_advance,
	580	0x04);
50e8df09 PR	581	else
	582	err = sx150x_i2c_write(chip->client,
	583	chip->dev_cfg->pri.x123.reg_advance,
	584	0x00);
c34f16b7 GB	585	if (err < 0)
	586	return err;
	587
	588	err = sx150x_init_io(chip, chip->dev_cfg->reg_pullup,
	589	pdata->io_pullup_ena);
	590	if (err < 0)
	591	return err;
	592
	593	err = sx150x_init_io(chip, chip->dev_cfg->reg_pulldn,
	594	pdata->io_pulldn_ena);
	595	if (err < 0)
	596	return err;
	597
ae9ca493 WC	598	if (chip->dev_cfg->model == SX150X_789) {
	599	err = sx150x_init_io(chip,
	600	chip->dev_cfg->pri.x789.reg_drain,
	601	pdata->io_open_drain_ena);
	602	if (err < 0)
	603	return err;
	604
	605	err = sx150x_init_io(chip,
	606	chip->dev_cfg->pri.x789.reg_polarity,
	607	pdata->io_polarity);
	608	if (err < 0)
	609	return err;
50e8df09	610	} else if (chip->dev_cfg->model == SX150X_456) {
ae9ca493 WC	611	/* Set all pins to work in normal mode */
	612	err = sx150x_init_io(chip,
	613	chip->dev_cfg->pri.x456.reg_pld_mode,
	614	0);
	615	if (err < 0)
	616	return err;
50e8df09 PR	617	} else {
	618	/* Set all pins to work in normal mode */
	619	err = sx150x_init_io(chip,
	620	chip->dev_cfg->pri.x123.reg_pld_mode,
	621	0);
	622	if (err < 0)
	623	return err;
ae9ca493	624	}
c34f16b7	625
c34f16b7 GB	626
	627	if (pdata->oscio_is_gpo)
	628	sx150x_set_oscio(chip, 0);
	629
	630	return err;
	631	}
	632
	633	static int sx150x_install_irq_chip(struct sx150x_chip *chip,
	634	int irq_summary,
	635	int irq_base)
	636	{
	637	int err;
c34f16b7 GB	638
	639	chip->irq_summary = irq_summary;
	640	chip->irq_base = irq_base;
	641
093e9435 WC	642	/* Add gpio chip to irq subsystem */
	643	err = gpiochip_irqchip_add(&chip->gpio_chip,
	644	&chip->irq_chip, chip->irq_base,
	645	handle_edge_irq, IRQ_TYPE_EDGE_BOTH);
	646	if (err) {
	647	dev_err(&chip->client->dev,
	648	"could not connect irqchip to gpiochip\n");
	649	return err;
c34f16b7 GB	650	}
c34f16b7 GB	651
644c8df2	652	err = devm_request_threaded_irq(&chip->client->dev,
093e9435 WC	653	irq_summary, NULL, sx150x_irq_thread_fn,
	654	IRQF_ONESHOT \| IRQF_SHARED \| IRQF_TRIGGER_FALLING,
	655	chip->irq_chip.name, chip);
c34f16b7 GB	656	if (err < 0) {
	657	chip->irq_summary = -1;
	658	chip->irq_base = -1;
	659	}
	660
	661	return err;
	662	}
	663
3836309d	664	static int sx150x_probe(struct i2c_client *client,
c34f16b7 GB	665	const struct i2c_device_id *id)
	666	{
	667	static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA \|
	668	I2C_FUNC_SMBUS_WRITE_WORD_DATA;
	669	struct sx150x_platform_data *pdata;
	670	struct sx150x_chip *chip;
	671	int rc;
	672
e56aee18	673	pdata = dev_get_platdata(&client->dev);
c34f16b7 GB	674	if (!pdata)
	675	return -EINVAL;
	676
	677	if (!i2c_check_functionality(client->adapter, i2c_funcs))
	678	return -ENOSYS;
	679
644c8df2 NB	680	chip = devm_kzalloc(&client->dev,
644c8df2 NB	681	sizeof(struct sx150x_chip), GFP_KERNEL);
c34f16b7 GB	682	if (!chip)
	683	return -ENOMEM;
	684
	685	sx150x_init_chip(chip, client, id->driver_data, pdata);
	686	rc = sx150x_init_hw(chip, pdata);
	687	if (rc < 0)
644c8df2	688	return rc;
c34f16b7	689
c7c8a8fc	690	rc = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
644c8df2 NB	691	if (rc)
644c8df2 NB	692	return rc;
c34f16b7 GB	693
	694	if (pdata->irq_summary >= 0) {
	695	rc = sx150x_install_irq_chip(chip,
	696	pdata->irq_summary,
	697	pdata->irq_base);
	698	if (rc < 0)
c7c8a8fc	699	return rc;
c34f16b7 GB	700	}
	701
	702	i2c_set_clientdata(client, chip);
	703
c34f16b7 GB	704	return 0;
	705	}
	706
	707	static struct i2c_driver sx150x_driver = {
	708	.driver = {
	709	.name = "sx150x",
16858cc5	710	.of_match_table = of_match_ptr(sx150x_of_match),
c34f16b7 GB	711	},
c34f16b7 GB	712	.probe = sx150x_probe,
c34f16b7 GB	713	.id_table = sx150x_id,
	714	};
	715
	716	static int __init sx150x_init(void)
	717	{
	718	return i2c_add_driver(&sx150x_driver);
	719	}
	720	subsys_initcall(sx150x_init);
	721
	722	static void __exit sx150x_exit(void)
	723	{
	724	return i2c_del_driver(&sx150x_driver);
	725	}
	726	module_exit(sx150x_exit);
	727
	728	MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
	729	MODULE_DESCRIPTION("Driver for Semtech SX150X I2C GPIO Expanders");
	730	MODULE_LICENSE("GPL v2");