[linux-2.6-block.git] / drivers / gpio / gpio-rcar.c

/*
 * Renesas R-Car GPIO Support
 *
 *  Copyright (C) 2013 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/slab.h>

struct gpio_rcar_priv {
	void __iomem *base;
	spinlock_t lock;
	struct gpio_rcar_config config;
	struct platform_device *pdev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
};

#define IOINTSEL 0x00
#define INOUTSEL 0x04
#define OUTDT 0x08
#define INDT 0x0c
#define INTDT 0x10
#define INTCLR 0x14
#define INTMSK 0x18
#define MSKCLR 0x1c
#define POSNEG 0x20
#define EDGLEVEL 0x24
#define FILONOFF 0x28
#define BOTHEDGE 0x4c

#define RCAR_MAX_GPIO_PER_BANK		32

static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
{
	return ioread32(p->base + offs);
}

static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
				   u32 value)
{
	iowrite32(value, p->base + offs);
}

static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
				 int bit, bool value)
{
	u32 tmp = gpio_rcar_read(p, offs);

	if (value)
		tmp |= BIT(bit);
	else
		tmp &= ~BIT(bit);

	gpio_rcar_write(p, offs, tmp);
}

static void gpio_rcar_irq_disable(struct irq_data *d)
{
	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);

	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_irq_enable(struct irq_data *d)
{
	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);

	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
						  unsigned int hwirq,
						  bool active_high_rising_edge,
						  bool level_trigger,
						  bool both)
{
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting Edge-Sensitive Interrupt Input Mode" and
	 * "Setting Level-Sensitive Interrupt Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive or negative logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);

	/* Configure edge or level trigger in EDGLEVEL */
	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);

	/* Select one edge or both edges in BOTHEDGE */
	if (p->config.has_both_edge_trigger)
		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);

	/* Select "Interrupt Input Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);

	/* Write INTCLR in case of edge trigger */
	if (!level_trigger)
		gpio_rcar_write(p, INTCLR, BIT(hwirq));

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
	unsigned int hwirq = irqd_to_hwirq(d);

	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
						      false);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
						      false);
		break;
	case IRQ_TYPE_EDGE_RISING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_BOTH:
		if (!p->config.has_both_edge_trigger)
			return -EINVAL;
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      true);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
{
	struct gpio_rcar_priv *p = dev_id;
	u32 pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = gpio_rcar_read(p, INTDT) &
			  gpio_rcar_read(p, INTMSK))) {
		offset = __ffs(pending);
		gpio_rcar_write(p, INTCLR, BIT(offset));
		generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
{
	return container_of(chip, struct gpio_rcar_priv, gpio_chip);
}

static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
						       unsigned int gpio,
						       bool output)
{
	struct gpio_rcar_priv *p = gpio_to_priv(chip);
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting General Output Mode" and
	 * "Setting General Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, gpio, false);

	/* Select "General Input/Output Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);

	/* Select Input Mode or Output Mode in INOUTSEL */
	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(chip->base + offset);
}

static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(chip->base + offset);

	/* Set the GPIO as an input to ensure that the next GPIO request won't
	 * drive the GPIO pin as an output.
	 */
	gpio_rcar_config_general_input_output_mode(chip, offset, false);
}

static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
{
	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	return 0;
}

static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
{
	u32 bit = BIT(offset);

	/* testing on r8a7790 shows that INDT does not show correct pin state
	 * when configured as output, so use OUTDT in case of output pins */
	if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
		return !!(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
	else
		return !!(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
}

static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_rcar_priv *p = gpio_to_priv(chip);
	unsigned long flags;

	spin_lock_irqsave(&p->lock, flags);
	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	gpio_rcar_set(chip, offset, value);
	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	return 0;
}

static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
}

static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int irq,
				 irq_hw_number_t hwirq)
{
	struct gpio_rcar_priv *p = h->host_data;

	dev_dbg(&p->pdev->dev, "map hw irq = %d, irq = %d\n", (int)hwirq, irq);

	irq_set_chip_data(irq, h->host_data);
	irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
	set_irq_flags(irq, IRQF_VALID); /* kill me now */
	return 0;
}

static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
	.map	= gpio_rcar_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

struct gpio_rcar_info {
	bool has_both_edge_trigger;
};

static const struct of_device_id gpio_rcar_of_table[] = {
	{
		.compatible = "renesas,gpio-r8a7790",
		.data = (void *)&(const struct gpio_rcar_info) {
			.has_both_edge_trigger = true,
		},
	}, {
		.compatible = "renesas,gpio-r8a7791",
		.data = (void *)&(const struct gpio_rcar_info) {
			.has_both_edge_trigger = true,
		},
	}, {
		.compatible = "renesas,gpio-rcar",
		.data = (void *)&(const struct gpio_rcar_info) {
			.has_both_edge_trigger = false,
		},
	}, {
		/* Terminator */
	},
};

MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);

static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
{
	struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
	struct device_node *np = p->pdev->dev.of_node;
	struct of_phandle_args args;
	int ret;

	if (pdata) {
		p->config = *pdata;
	} else if (IS_ENABLED(CONFIG_OF) && np) {
		const struct of_device_id *match;
		const struct gpio_rcar_info *info;

		match = of_match_node(gpio_rcar_of_table, np);
		if (!match)
			return -EINVAL;

		info = match->data;

		ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
						       &args);
		p->config.number_of_pins = ret == 0 ? args.args[2]
					 : RCAR_MAX_GPIO_PER_BANK;
		p->config.gpio_base = -1;
		p->config.has_both_edge_trigger = info->has_both_edge_trigger;
	}

	if (p->config.number_of_pins == 0 ||
	    p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
		dev_warn(&p->pdev->dev,
			 "Invalid number of gpio lines %u, using %u\n",
			 p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
		p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
	}

	return 0;
}

static int gpio_rcar_probe(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p;
	struct resource *io, *irq;
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	struct device *dev = &pdev->dev;
	const char *name = dev_name(dev);
	int ret;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p) {
		ret = -ENOMEM;
		goto err0;
	}

	p->pdev = pdev;
	spin_lock_init(&p->lock);

	/* Get device configuration from DT node or platform data. */
	ret = gpio_rcar_parse_pdata(p);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, p);

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);

	if (!io || !irq) {
		dev_err(dev, "missing IRQ or IOMEM\n");
		ret = -EINVAL;
		goto err0;
	}

	p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
	if (!p->base) {
		dev_err(dev, "failed to remap I/O memory\n");
		ret = -ENXIO;
		goto err0;
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->request = gpio_rcar_request;
	gpio_chip->free = gpio_rcar_free;
	gpio_chip->direction_input = gpio_rcar_direction_input;
	gpio_chip->get = gpio_rcar_get;
	gpio_chip->direction_output = gpio_rcar_direction_output;
	gpio_chip->set = gpio_rcar_set;
	gpio_chip->to_irq = gpio_rcar_to_irq;
	gpio_chip->label = name;
	gpio_chip->dev = dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = p->config.gpio_base;
	gpio_chip->ngpio = p->config.number_of_pins;

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->irq_mask = gpio_rcar_irq_disable;
	irq_chip->irq_unmask = gpio_rcar_irq_enable;
	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED
			 | IRQCHIP_MASK_ON_SUSPEND;

	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
					      p->config.number_of_pins,
					      p->config.irq_base,
					      &gpio_rcar_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(dev, "cannot initialize irq domain\n");
		goto err0;
	}

	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
			     IRQF_SHARED, name, p)) {
		dev_err(dev, "failed to request IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	ret = gpiochip_add(gpio_chip);
	if (ret) {
		dev_err(dev, "failed to add GPIO controller\n");
		goto err1;
	}

	dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);

	/* warn in case of mismatch if irq base is specified */
	if (p->config.irq_base) {
		ret = irq_find_mapping(p->irq_domain, 0);
		if (p->config.irq_base != ret)
			dev_warn(dev, "irq base mismatch (%u/%u)\n",
				 p->config.irq_base, ret);
	}

	if (p->config.pctl_name) {
		ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
					     gpio_chip->base, gpio_chip->ngpio);
		if (ret < 0)
			dev_warn(dev, "failed to add pin range\n");
	}

	return 0;

err1:
	irq_domain_remove(p->irq_domain);
err0:
	pm_runtime_put(dev);
	pm_runtime_disable(dev);
	return ret;
}

static int gpio_rcar_remove(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);

	gpiochip_remove(&p->gpio_chip);

	irq_domain_remove(p->irq_domain);
	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	return 0;
}

static struct platform_driver gpio_rcar_device_driver = {
	.probe		= gpio_rcar_probe,
	.remove		= gpio_rcar_remove,
	.driver		= {
		.name	= "gpio_rcar",
		.of_match_table = of_match_ptr(gpio_rcar_of_table),
	}
};

module_platform_driver(gpio_rcar_device_driver);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
119f5e44 MD	1	/*
	2	* Renesas R-Car GPIO Support
	3	*
	4	* Copyright (C) 2013 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/err.h>
	17	#include <linux/gpio.h>
	18	#include <linux/init.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/io.h>
	21	#include <linux/ioport.h>
	22	#include <linux/irq.h>
	23	#include <linux/irqdomain.h>
	24	#include <linux/module.h>
bd0bf468	25	#include <linux/of.h>
dc3465a9	26	#include <linux/pinctrl/consumer.h>
119f5e44 MD	27	#include <linux/platform_data/gpio-rcar.h>
119f5e44 MD	28	#include <linux/platform_device.h>
df0c6c80	29	#include <linux/pm_runtime.h>
119f5e44 MD	30	#include <linux/spinlock.h>
	31	#include <linux/slab.h>
	32
	33	struct gpio_rcar_priv {
	34	void __iomem *base;
	35	spinlock_t lock;
	36	struct gpio_rcar_config config;
	37	struct platform_device *pdev;
	38	struct gpio_chip gpio_chip;
	39	struct irq_chip irq_chip;
	40	struct irq_domain *irq_domain;
	41	};
	42
	43	#define IOINTSEL 0x00
	44	#define INOUTSEL 0x04
	45	#define OUTDT 0x08
	46	#define INDT 0x0c
	47	#define INTDT 0x10
	48	#define INTCLR 0x14
	49	#define INTMSK 0x18
	50	#define MSKCLR 0x1c
	51	#define POSNEG 0x20
	52	#define EDGLEVEL 0x24
	53	#define FILONOFF 0x28
7e1092b5	54	#define BOTHEDGE 0x4c
119f5e44	55
159f8a02 LP	56	#define RCAR_MAX_GPIO_PER_BANK 32
159f8a02 LP	57
119f5e44 MD	58	static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
	59	{
	60	return ioread32(p->base + offs);
	61	}
	62
	63	static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
	64	u32 value)
	65	{
	66	iowrite32(value, p->base + offs);
	67	}
	68
	69	static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
	70	int bit, bool value)
	71	{
	72	u32 tmp = gpio_rcar_read(p, offs);
	73
	74	if (value)
	75	tmp \|= BIT(bit);
	76	else
	77	tmp &= ~BIT(bit);
	78
	79	gpio_rcar_write(p, offs, tmp);
	80	}
	81
	82	static void gpio_rcar_irq_disable(struct irq_data *d)
	83	{
	84	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
	85
	86	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
	87	}
	88
	89	static void gpio_rcar_irq_enable(struct irq_data *d)
	90	{
	91	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
	92
	93	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
	94	}
	95
	96	static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
	97	unsigned int hwirq,
	98	bool active_high_rising_edge,
7e1092b5 SH	99	bool level_trigger,
7e1092b5 SH	100	bool both)
119f5e44 MD	101	{
	102	unsigned long flags;
	103
	104	/* follow steps in the GPIO documentation for
	105	* "Setting Edge-Sensitive Interrupt Input Mode" and
	106	* "Setting Level-Sensitive Interrupt Input Mode"
	107	*/
	108
	109	spin_lock_irqsave(&p->lock, flags);
	110
	111	/* Configure postive or negative logic in POSNEG */
	112	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
	113
	114	/* Configure edge or level trigger in EDGLEVEL */
	115	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
	116
7e1092b5 SH	117	/* Select one edge or both edges in BOTHEDGE */
	118	if (p->config.has_both_edge_trigger)
	119	gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
	120
119f5e44 MD	121	/* Select "Interrupt Input Mode" in IOINTSEL */
	122	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
	123
	124	/* Write INTCLR in case of edge trigger */
	125	if (!level_trigger)
	126	gpio_rcar_write(p, INTCLR, BIT(hwirq));
	127
	128	spin_unlock_irqrestore(&p->lock, flags);
	129	}
	130
	131	static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
	132	{
	133	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
	134	unsigned int hwirq = irqd_to_hwirq(d);
	135
	136	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
	137
	138	switch (type & IRQ_TYPE_SENSE_MASK) {
	139	case IRQ_TYPE_LEVEL_HIGH:
7e1092b5 SH	140	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
7e1092b5 SH	141	false);
119f5e44 MD	142	break;
119f5e44 MD	143	case IRQ_TYPE_LEVEL_LOW:
7e1092b5 SH	144	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
7e1092b5 SH	145	false);
119f5e44 MD	146	break;
119f5e44 MD	147	case IRQ_TYPE_EDGE_RISING:
7e1092b5 SH	148	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
7e1092b5 SH	149	false);
119f5e44 MD	150	break;
119f5e44 MD	151	case IRQ_TYPE_EDGE_FALLING:
7e1092b5 SH	152	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
	153	false);
	154	break;
	155	case IRQ_TYPE_EDGE_BOTH:
	156	if (!p->config.has_both_edge_trigger)
	157	return -EINVAL;
	158	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
	159	true);
119f5e44 MD	160	break;
	161	default:
	162	return -EINVAL;
	163	}
	164	return 0;
	165	}
	166
	167	static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
	168	{
	169	struct gpio_rcar_priv *p = dev_id;
	170	u32 pending;
	171	unsigned int offset, irqs_handled = 0;
	172
8808b64d VB	173	while ((pending = gpio_rcar_read(p, INTDT) &
8808b64d VB	174	gpio_rcar_read(p, INTMSK))) {
119f5e44 MD	175	offset = __ffs(pending);
	176	gpio_rcar_write(p, INTCLR, BIT(offset));
	177	generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
	178	irqs_handled++;
	179	}
	180
	181	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	182	}
	183
	184	static inline struct gpio_rcar_priv gpio_to_priv(struct gpio_chip chip)
	185	{
	186	return container_of(chip, struct gpio_rcar_priv, gpio_chip);
	187	}
	188
	189	static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
	190	unsigned int gpio,
	191	bool output)
	192	{
	193	struct gpio_rcar_priv *p = gpio_to_priv(chip);
	194	unsigned long flags;
	195
	196	/* follow steps in the GPIO documentation for
	197	* "Setting General Output Mode" and
	198	* "Setting General Input Mode"
	199	*/
	200
	201	spin_lock_irqsave(&p->lock, flags);
	202
	203	/* Configure postive logic in POSNEG */
	204	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
	205
	206	/* Select "General Input/Output Mode" in IOINTSEL */
	207	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
	208
	209	/* Select Input Mode or Output Mode in INOUTSEL */
	210	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
	211
	212	spin_unlock_irqrestore(&p->lock, flags);
	213	}
	214
dc3465a9 LP	215	static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
	216	{
	217	return pinctrl_request_gpio(chip->base + offset);
	218	}
	219
	220	static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
	221	{
	222	pinctrl_free_gpio(chip->base + offset);
	223
	224	/* Set the GPIO as an input to ensure that the next GPIO request won't
	225	* drive the GPIO pin as an output.
	226	*/
	227	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	228	}
	229
119f5e44 MD	230	static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
	231	{
	232	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	233	return 0;
	234	}
	235
	236	static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
	237	{
ae9550f6 MD	238	u32 bit = BIT(offset);
	239
	240	/* testing on r8a7790 shows that INDT does not show correct pin state
	241	* when configured as output, so use OUTDT in case of output pins */
	242	if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
7cb5409b	243	return !!(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
ae9550f6	244	else
7cb5409b	245	return !!(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
119f5e44 MD	246	}
	247
	248	static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
	249	{
	250	struct gpio_rcar_priv *p = gpio_to_priv(chip);
	251	unsigned long flags;
	252
	253	spin_lock_irqsave(&p->lock, flags);
	254	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	255	spin_unlock_irqrestore(&p->lock, flags);
	256	}
	257
	258	static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
	259	int value)
	260	{
	261	/* write GPIO value to output before selecting output mode of pin */
	262	gpio_rcar_set(chip, offset, value);
	263	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	264	return 0;
	265	}
	266
	267	static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
	268	{
	269	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
	270	}
	271
c0d6c1ad LW	272	static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int irq,
c0d6c1ad LW	273	irq_hw_number_t hwirq)
119f5e44 MD	274	{
	275	struct gpio_rcar_priv *p = h->host_data;
	276
c0d6c1ad	277	dev_dbg(&p->pdev->dev, "map hw irq = %d, irq = %d\n", (int)hwirq, irq);
119f5e44	278
c0d6c1ad LW	279	irq_set_chip_data(irq, h->host_data);
	280	irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
	281	set_irq_flags(irq, IRQF_VALID); /* kill me now */
119f5e44 MD	282	return 0;
	283	}
	284
	285	static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
	286	.map = gpio_rcar_irq_domain_map,
fe132649	287	.xlate = irq_domain_xlate_twocell,
119f5e44 MD	288	};
119f5e44 MD	289
850dfe17 LP	290	struct gpio_rcar_info {
	291	bool has_both_edge_trigger;
	292	};
	293
	294	static const struct of_device_id gpio_rcar_of_table[] = {
	295	{
	296	.compatible = "renesas,gpio-r8a7790",
	297	.data = (void *)&(const struct gpio_rcar_info) {
	298	.has_both_edge_trigger = true,
	299	},
	300	}, {
	301	.compatible = "renesas,gpio-r8a7791",
	302	.data = (void *)&(const struct gpio_rcar_info) {
	303	.has_both_edge_trigger = true,
	304	},
	305	}, {
	306	.compatible = "renesas,gpio-rcar",
	307	.data = (void *)&(const struct gpio_rcar_info) {
	308	.has_both_edge_trigger = false,
	309	},
	310	}, {
	311	/* Terminator */
	312	},
	313	};
	314
	315	MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
	316
	317	static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
159f8a02	318	{
e56aee18	319	struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
159f8a02 LP	320	struct device_node *np = p->pdev->dev.of_node;
	321	struct of_phandle_args args;
	322	int ret;
159f8a02	323
e305062e	324	if (pdata) {
159f8a02	325	p->config = *pdata;
e305062e	326	} else if (IS_ENABLED(CONFIG_OF) && np) {
850dfe17 LP	327	const struct of_device_id *match;
	328	const struct gpio_rcar_info *info;
	329
	330	match = of_match_node(gpio_rcar_of_table, np);
	331	if (!match)
	332	return -EINVAL;
	333
	334	info = match->data;
	335
01eb2d18 LP	336	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
	337	&args);
	338	p->config.number_of_pins = ret == 0 ? args.args[2]
159f8a02 LP	339	: RCAR_MAX_GPIO_PER_BANK;
159f8a02 LP	340	p->config.gpio_base = -1;
850dfe17	341	p->config.has_both_edge_trigger = info->has_both_edge_trigger;
159f8a02	342	}
159f8a02 LP	343
	344	if (p->config.number_of_pins == 0 \|\|
	345	p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
	346	dev_warn(&p->pdev->dev,
	347	"Invalid number of gpio lines %u, using %u\n",
	348	p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
	349	p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
	350	}
850dfe17 LP	351
850dfe17 LP	352	return 0;
159f8a02 LP	353	}
159f8a02 LP	354
119f5e44 MD	355	static int gpio_rcar_probe(struct platform_device *pdev)
119f5e44 MD	356	{
119f5e44 MD	357	struct gpio_rcar_priv *p;
	358	struct resource io, irq;
	359	struct gpio_chip *gpio_chip;
	360	struct irq_chip *irq_chip;
b22978fc GU	361	struct device *dev = &pdev->dev;
b22978fc GU	362	const char *name = dev_name(dev);
119f5e44 MD	363	int ret;
119f5e44 MD	364
b22978fc	365	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
119f5e44	366	if (!p) {
119f5e44 MD	367	ret = -ENOMEM;
	368	goto err0;
	369	}
	370
119f5e44	371	p->pdev = pdev;
119f5e44 MD	372	spin_lock_init(&p->lock);
119f5e44 MD	373
159f8a02	374	/* Get device configuration from DT node or platform data. */
850dfe17 LP	375	ret = gpio_rcar_parse_pdata(p);
	376	if (ret < 0)
	377	return ret;
159f8a02 LP	378
	379	platform_set_drvdata(pdev, p);
	380
df0c6c80 GU	381	pm_runtime_enable(dev);
	382	pm_runtime_get_sync(dev);
	383
119f5e44 MD	384	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	385	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	386
	387	if (!io \|\| !irq) {
b22978fc	388	dev_err(dev, "missing IRQ or IOMEM\n");
119f5e44 MD	389	ret = -EINVAL;
	390	goto err0;
	391	}
	392
b22978fc	393	p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
119f5e44	394	if (!p->base) {
b22978fc	395	dev_err(dev, "failed to remap I/O memory\n");
119f5e44 MD	396	ret = -ENXIO;
	397	goto err0;
	398	}
	399
	400	gpio_chip = &p->gpio_chip;
dc3465a9 LP	401	gpio_chip->request = gpio_rcar_request;
dc3465a9 LP	402	gpio_chip->free = gpio_rcar_free;
119f5e44 MD	403	gpio_chip->direction_input = gpio_rcar_direction_input;
	404	gpio_chip->get = gpio_rcar_get;
	405	gpio_chip->direction_output = gpio_rcar_direction_output;
	406	gpio_chip->set = gpio_rcar_set;
	407	gpio_chip->to_irq = gpio_rcar_to_irq;
	408	gpio_chip->label = name;
b22978fc	409	gpio_chip->dev = dev;
119f5e44 MD	410	gpio_chip->owner = THIS_MODULE;
	411	gpio_chip->base = p->config.gpio_base;
	412	gpio_chip->ngpio = p->config.number_of_pins;
	413
	414	irq_chip = &p->irq_chip;
	415	irq_chip->name = name;
	416	irq_chip->irq_mask = gpio_rcar_irq_disable;
	417	irq_chip->irq_unmask = gpio_rcar_irq_enable;
119f5e44	418	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
40396112 MD	419	irq_chip->flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_SET_TYPE_MASKED
40396112 MD	420	\| IRQCHIP_MASK_ON_SUSPEND;
119f5e44 MD	421
	422	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
	423	p->config.number_of_pins,
	424	p->config.irq_base,
	425	&gpio_rcar_irq_domain_ops, p);
	426	if (!p->irq_domain) {
	427	ret = -ENXIO;
b22978fc	428	dev_err(dev, "cannot initialize irq domain\n");
0c8aab8e	429	goto err0;
119f5e44 MD	430	}
119f5e44 MD	431
b22978fc GU	432	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
	433	IRQF_SHARED, name, p)) {
	434	dev_err(dev, "failed to request IRQ\n");
119f5e44 MD	435	ret = -ENOENT;
	436	goto err1;
	437	}
	438
	439	ret = gpiochip_add(gpio_chip);
	440	if (ret) {
b22978fc	441	dev_err(dev, "failed to add GPIO controller\n");
119f5e44 MD	442	goto err1;
	443	}
	444
b22978fc	445	dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);
119f5e44 MD	446
	447	/* warn in case of mismatch if irq base is specified */
	448	if (p->config.irq_base) {
	449	ret = irq_find_mapping(p->irq_domain, 0);
	450	if (p->config.irq_base != ret)
b22978fc	451	dev_warn(dev, "irq base mismatch (%u/%u)\n",
119f5e44 MD	452	p->config.irq_base, ret);
	453	}
	454
159f8a02 LP	455	if (p->config.pctl_name) {
	456	ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
	457	gpio_chip->base, gpio_chip->ngpio);
	458	if (ret < 0)
b22978fc	459	dev_warn(dev, "failed to add pin range\n");
159f8a02	460	}
dc3465a9	461
119f5e44 MD	462	return 0;
	463
	464	err1:
	465	irq_domain_remove(p->irq_domain);
	466	err0:
df0c6c80 GU	467	pm_runtime_put(dev);
df0c6c80 GU	468	pm_runtime_disable(dev);
119f5e44 MD	469	return ret;
	470	}
	471
	472	static int gpio_rcar_remove(struct platform_device *pdev)
	473	{
	474	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
119f5e44	475
9f5132ae	476	gpiochip_remove(&p->gpio_chip);
119f5e44 MD	477
119f5e44 MD	478	irq_domain_remove(p->irq_domain);
df0c6c80 GU	479	pm_runtime_put(&pdev->dev);
df0c6c80 GU	480	pm_runtime_disable(&pdev->dev);
119f5e44 MD	481	return 0;
	482	}
	483
	484	static struct platform_driver gpio_rcar_device_driver = {
	485	.probe = gpio_rcar_probe,
	486	.remove = gpio_rcar_remove,
	487	.driver = {
	488	.name = "gpio_rcar",
159f8a02	489	.of_match_table = of_match_ptr(gpio_rcar_of_table),
119f5e44 MD	490	}
	491	};
	492
	493	module_platform_driver(gpio_rcar_device_driver);
	494
	495	MODULE_AUTHOR("Magnus Damm");
	496	MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
	497	MODULE_LICENSE("GPL v2");