[linux-2.6-block.git] / drivers / gpio / gpio-rcar.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Renesas R-Car GPIO Support
 *
 *  Copyright (C) 2014 Renesas Electronics Corporation
 *  Copyright (C) 2013 Magnus Damm
 */

#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/slab.h>

struct gpio_rcar_bank_info {
	u32 iointsel;
	u32 inoutsel;
	u32 outdt;
	u32 posneg;
	u32 edglevel;
	u32 bothedge;
	u32 intmsk;
};

struct gpio_rcar_priv {
	void __iomem *base;
	spinlock_t lock;
	struct device *dev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	unsigned int irq_parent;
	atomic_t wakeup_path;
	bool has_both_edge_trigger;
	struct gpio_rcar_bank_info bank_info;
};

#define IOINTSEL 0x00	/* General IO/Interrupt Switching Register */
#define INOUTSEL 0x04	/* General Input/Output Switching Register */
#define OUTDT 0x08	/* General Output Register */
#define INDT 0x0c	/* General Input Register */
#define INTDT 0x10	/* Interrupt Display Register */
#define INTCLR 0x14	/* Interrupt Clear Register */
#define INTMSK 0x18	/* Interrupt Mask Register */
#define MSKCLR 0x1c	/* Interrupt Mask Clear Register */
#define POSNEG 0x20	/* Positive/Negative Logic Select Register */
#define EDGLEVEL 0x24	/* Edge/level Select Register */
#define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
#define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */

#define RCAR_MAX_GPIO_PER_BANK		32

static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
{
	return ioread32(p->base + offs);
}

static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
				   u32 value)
{
	iowrite32(value, p->base + offs);
}

static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
				 int bit, bool value)
{
	u32 tmp = gpio_rcar_read(p, offs);

	if (value)
		tmp |= BIT(bit);
	else
		tmp &= ~BIT(bit);

	gpio_rcar_write(p, offs, tmp);
}

static void gpio_rcar_irq_disable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_irq_enable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
						  unsigned int hwirq,
						  bool active_high_rising_edge,
						  bool level_trigger,
						  bool both)
{
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting Edge-Sensitive Interrupt Input Mode" and
	 * "Setting Level-Sensitive Interrupt Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive or negative logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);

	/* Configure edge or level trigger in EDGLEVEL */
	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);

	/* Select one edge or both edges in BOTHEDGE */
	if (p->has_both_edge_trigger)
		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);

	/* Select "Interrupt Input Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);

	/* Write INTCLR in case of edge trigger */
	if (!level_trigger)
		gpio_rcar_write(p, INTCLR, BIT(hwirq));

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	unsigned int hwirq = irqd_to_hwirq(d);

	dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
						      false);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
						      false);
		break;
	case IRQ_TYPE_EDGE_RISING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_BOTH:
		if (!p->has_both_edge_trigger)
			return -EINVAL;
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      true);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	int error;

	if (p->irq_parent) {
		error = irq_set_irq_wake(p->irq_parent, on);
		if (error) {
			dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
				p->irq_parent);
			p->irq_parent = 0;
		}
	}

	if (on)
		atomic_inc(&p->wakeup_path);
	else
		atomic_dec(&p->wakeup_path);

	return 0;
}

static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
{
	struct gpio_rcar_priv *p = dev_id;
	u32 pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = gpio_rcar_read(p, INTDT) &
			  gpio_rcar_read(p, INTMSK))) {
		offset = __ffs(pending);
		gpio_rcar_write(p, INTCLR, BIT(offset));
		generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
						    offset));
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
						       unsigned int gpio,
						       bool output)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting General Output Mode" and
	 * "Setting General Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, gpio, false);

	/* Select "General Input/Output Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);

	/* Select Input Mode or Output Mode in INOUTSEL */
	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	int error;

	error = pm_runtime_get_sync(p->dev);
	if (error < 0)
		return error;

	error = pinctrl_gpio_request(chip->base + offset);
	if (error)
		pm_runtime_put(p->dev);

	return error;
}

static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);

	pinctrl_gpio_free(chip->base + offset);

	/*
	 * Set the GPIO as an input to ensure that the next GPIO request won't
	 * drive the GPIO pin as an output.
	 */
	gpio_rcar_config_general_input_output_mode(chip, offset, false);

	pm_runtime_put(p->dev);
}

static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);

	return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
}

static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
{
	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	return 0;
}

static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
{
	u32 bit = BIT(offset);

	/* testing on r8a7790 shows that INDT does not show correct pin state
	 * when configured as output, so use OUTDT in case of output pins */
	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
		return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
	else
		return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
}

static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&p->lock, flags);
	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	spin_unlock_irqrestore(&p->lock, flags);
}

static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
				   unsigned long *bits)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;
	u32 val, bankmask;

	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
	if (chip->valid_mask)
		bankmask &= chip->valid_mask[0];

	if (!bankmask)
		return;

	spin_lock_irqsave(&p->lock, flags);
	val = gpio_rcar_read(p, OUTDT);
	val &= ~bankmask;
	val |= (bankmask & bits[0]);
	gpio_rcar_write(p, OUTDT, val);
	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	gpio_rcar_set(chip, offset, value);
	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	return 0;
}

struct gpio_rcar_info {
	bool has_both_edge_trigger;
};

static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
	.has_both_edge_trigger = false,
};

static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
	.has_both_edge_trigger = true,
};

static const struct of_device_id gpio_rcar_of_table[] = {
	{
		.compatible = "renesas,gpio-r8a7743",
		/* RZ/G1 GPIO is identical to R-Car Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7790",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7791",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7792",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7793",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7794",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7795",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7796",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,rcar-gen1-gpio",
		.data = &gpio_rcar_info_gen1,
	}, {
		.compatible = "renesas,rcar-gen2-gpio",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,rcar-gen3-gpio",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-rcar",
		.data = &gpio_rcar_info_gen1,
	}, {
		/* Terminator */
	},
};

MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);

static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
{
	struct device_node *np = p->dev->of_node;
	const struct gpio_rcar_info *info;
	struct of_phandle_args args;
	int ret;

	info = of_device_get_match_data(p->dev);

	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
	p->has_both_edge_trigger = info->has_both_edge_trigger;

	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
		dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
			 *npins, RCAR_MAX_GPIO_PER_BANK);
		*npins = RCAR_MAX_GPIO_PER_BANK;
	}

	return 0;
}

static int gpio_rcar_probe(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p;
	struct resource *io, *irq;
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	struct device *dev = &pdev->dev;
	const char *name = dev_name(dev);
	unsigned int npins;
	int ret;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p)
		return -ENOMEM;

	p->dev = dev;
	spin_lock_init(&p->lock);

	/* Get device configuration from DT node */
	ret = gpio_rcar_parse_dt(p, &npins);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, p);

	pm_runtime_enable(dev);

	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!irq) {
		dev_err(dev, "missing IRQ\n");
		ret = -EINVAL;
		goto err0;
	}

	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	p->base = devm_ioremap_resource(dev, io);
	if (IS_ERR(p->base)) {
		ret = PTR_ERR(p->base);
		goto err0;
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->request = gpio_rcar_request;
	gpio_chip->free = gpio_rcar_free;
	gpio_chip->get_direction = gpio_rcar_get_direction;
	gpio_chip->direction_input = gpio_rcar_direction_input;
	gpio_chip->get = gpio_rcar_get;
	gpio_chip->direction_output = gpio_rcar_direction_output;
	gpio_chip->set = gpio_rcar_set;
	gpio_chip->set_multiple = gpio_rcar_set_multiple;
	gpio_chip->label = name;
	gpio_chip->parent = dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = -1;
	gpio_chip->ngpio = npins;

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->parent_device = dev;
	irq_chip->irq_mask = gpio_rcar_irq_disable;
	irq_chip->irq_unmask = gpio_rcar_irq_enable;
	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
	irq_chip->flags	= IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;

	ret = gpiochip_add_data(gpio_chip, p);
	if (ret) {
		dev_err(dev, "failed to add GPIO controller\n");
		goto err0;
	}

	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "cannot add irqchip\n");
		goto err1;
	}

	p->irq_parent = irq->start;
	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
			     IRQF_SHARED, name, p)) {
		dev_err(dev, "failed to request IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	dev_info(dev, "driving %d GPIOs\n", npins);

	return 0;

err1:
	gpiochip_remove(gpio_chip);
err0:
	pm_runtime_disable(dev);
	return ret;
}

static int gpio_rcar_remove(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);

	gpiochip_remove(&p->gpio_chip);

	pm_runtime_disable(&pdev->dev);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int gpio_rcar_suspend(struct device *dev)
{
	struct gpio_rcar_priv *p = dev_get_drvdata(dev);

	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
	if (p->has_both_edge_trigger)
		p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);

	if (atomic_read(&p->wakeup_path))
		device_set_wakeup_path(dev);

	return 0;
}

static int gpio_rcar_resume(struct device *dev)
{
	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	unsigned int offset;
	u32 mask;

	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
		if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
			continue;

		mask = BIT(offset);
		/* I/O pin */
		if (!(p->bank_info.iointsel & mask)) {
			if (p->bank_info.inoutsel & mask)
				gpio_rcar_direction_output(
					&p->gpio_chip, offset,
					!!(p->bank_info.outdt & mask));
			else
				gpio_rcar_direction_input(&p->gpio_chip,
							  offset);
		} else {
			/* Interrupt pin */
			gpio_rcar_config_interrupt_input_mode(
				p,
				offset,
				!(p->bank_info.posneg & mask),
				!(p->bank_info.edglevel & mask),
				!!(p->bank_info.bothedge & mask));

			if (p->bank_info.intmsk & mask)
				gpio_rcar_write(p, MSKCLR, mask);
		}
	}

	return 0;
}
#endif /* CONFIG_PM_SLEEP*/

static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);

static struct platform_driver gpio_rcar_device_driver = {
	.probe		= gpio_rcar_probe,
	.remove		= gpio_rcar_remove,
	.driver		= {
		.name	= "gpio_rcar",
		.pm     = &gpio_rcar_pm_ops,
		.of_match_table = of_match_ptr(gpio_rcar_of_table),
	}
};

module_platform_driver(gpio_rcar_device_driver);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
8b37eb74	1	// SPDX-License-Identifier: GPL-2.0
119f5e44 MD	2	/*
	3	* Renesas R-Car GPIO Support
	4	*
1fd2b49d	5	* Copyright (C) 2014 Renesas Electronics Corporation
119f5e44	6	* Copyright (C) 2013 Magnus Damm
119f5e44 MD	7	*/
	8
	9	#include <linux/err.h>
4b1d8007	10	#include <linux/gpio/driver.h>
119f5e44 MD	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/io.h>
	14	#include <linux/ioport.h>
	15	#include <linux/irq.h>
119f5e44	16	#include <linux/module.h>
bd0bf468	17	#include <linux/of.h>
f9f2a6fe	18	#include <linux/of_device.h>
dc3465a9	19	#include <linux/pinctrl/consumer.h>
119f5e44	20	#include <linux/platform_device.h>
df0c6c80	21	#include <linux/pm_runtime.h>
119f5e44 MD	22	#include <linux/spinlock.h>
	23	#include <linux/slab.h>
	24
51750fb1 HD	25	struct gpio_rcar_bank_info {
	26	u32 iointsel;
	27	u32 inoutsel;
	28	u32 outdt;
	29	u32 posneg;
	30	u32 edglevel;
	31	u32 bothedge;
	32	u32 intmsk;
	33	};
	34
119f5e44 MD	35	struct gpio_rcar_priv {
	36	void __iomem *base;
	37	spinlock_t lock;
a53f7953	38	struct device *dev;
119f5e44 MD	39	struct gpio_chip gpio_chip;
119f5e44 MD	40	struct irq_chip irq_chip;
8b092be9	41	unsigned int irq_parent;
9ac79ba9	42	atomic_t wakeup_path;
8b092be9	43	bool has_both_edge_trigger;
51750fb1	44	struct gpio_rcar_bank_info bank_info;
119f5e44 MD	45	};
119f5e44 MD	46
3dc1e685 GU	47	#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
	48	#define INOUTSEL 0x04 /* General Input/Output Switching Register */
	49	#define OUTDT 0x08 /* General Output Register */
	50	#define INDT 0x0c /* General Input Register */
	51	#define INTDT 0x10 /* Interrupt Display Register */
	52	#define INTCLR 0x14 /* Interrupt Clear Register */
	53	#define INTMSK 0x18 /* Interrupt Mask Register */
	54	#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
	55	#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
	56	#define EDGLEVEL 0x24 /* Edge/level Select Register */
	57	#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
	58	#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
119f5e44	59
159f8a02 LP	60	#define RCAR_MAX_GPIO_PER_BANK 32
159f8a02 LP	61
119f5e44 MD	62	static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
	63	{
	64	return ioread32(p->base + offs);
	65	}
	66
	67	static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
	68	u32 value)
	69	{
	70	iowrite32(value, p->base + offs);
	71	}
	72
	73	static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
	74	int bit, bool value)
	75	{
	76	u32 tmp = gpio_rcar_read(p, offs);
	77
	78	if (value)
	79	tmp \|= BIT(bit);
	80	else
	81	tmp &= ~BIT(bit);
	82
	83	gpio_rcar_write(p, offs, tmp);
	84	}
	85
	86	static void gpio_rcar_irq_disable(struct irq_data *d)
	87	{
c7f3c5d3	88	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	89	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	90
	91	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
	92	}
	93
	94	static void gpio_rcar_irq_enable(struct irq_data *d)
	95	{
c7f3c5d3	96	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	97	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	98
	99	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
	100	}
	101
	102	static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
	103	unsigned int hwirq,
	104	bool active_high_rising_edge,
7e1092b5 SH	105	bool level_trigger,
7e1092b5 SH	106	bool both)
119f5e44 MD	107	{
	108	unsigned long flags;
	109
	110	/* follow steps in the GPIO documentation for
	111	* "Setting Edge-Sensitive Interrupt Input Mode" and
	112	* "Setting Level-Sensitive Interrupt Input Mode"
	113	*/
	114
	115	spin_lock_irqsave(&p->lock, flags);
	116
	117	/* Configure postive or negative logic in POSNEG */
	118	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
	119
	120	/* Configure edge or level trigger in EDGLEVEL */
	121	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
	122
7e1092b5	123	/* Select one edge or both edges in BOTHEDGE */
8b092be9	124	if (p->has_both_edge_trigger)
7e1092b5 SH	125	gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
7e1092b5 SH	126
119f5e44 MD	127	/* Select "Interrupt Input Mode" in IOINTSEL */
	128	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
	129
	130	/* Write INTCLR in case of edge trigger */
	131	if (!level_trigger)
	132	gpio_rcar_write(p, INTCLR, BIT(hwirq));
	133
	134	spin_unlock_irqrestore(&p->lock, flags);
	135	}
	136
	137	static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
	138	{
c7f3c5d3	139	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	140	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	141	unsigned int hwirq = irqd_to_hwirq(d);
119f5e44 MD	142
a53f7953	143	dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
119f5e44 MD	144
	145	switch (type & IRQ_TYPE_SENSE_MASK) {
	146	case IRQ_TYPE_LEVEL_HIGH:
7e1092b5 SH	147	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
7e1092b5 SH	148	false);
119f5e44 MD	149	break;
119f5e44 MD	150	case IRQ_TYPE_LEVEL_LOW:
7e1092b5 SH	151	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
7e1092b5 SH	152	false);
119f5e44 MD	153	break;
119f5e44 MD	154	case IRQ_TYPE_EDGE_RISING:
7e1092b5 SH	155	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
7e1092b5 SH	156	false);
119f5e44 MD	157	break;
119f5e44 MD	158	case IRQ_TYPE_EDGE_FALLING:
7e1092b5 SH	159	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
	160	false);
	161	break;
	162	case IRQ_TYPE_EDGE_BOTH:
8b092be9	163	if (!p->has_both_edge_trigger)
7e1092b5 SH	164	return -EINVAL;
	165	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
	166	true);
119f5e44 MD	167	break;
	168	default:
	169	return -EINVAL;
	170	}
	171	return 0;
	172	}
	173
ab82fa7d GU	174	static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
	175	{
	176	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	177	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
501ef0f9 GU	178	int error;
	179
	180	if (p->irq_parent) {
	181	error = irq_set_irq_wake(p->irq_parent, on);
	182	if (error) {
a53f7953	183	dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
501ef0f9 GU	184	p->irq_parent);
	185	p->irq_parent = 0;
	186	}
	187	}
ab82fa7d	188
ab82fa7d	189	if (on)
9ac79ba9	190	atomic_inc(&p->wakeup_path);
ab82fa7d	191	else
9ac79ba9	192	atomic_dec(&p->wakeup_path);
ab82fa7d GU	193
	194	return 0;
	195	}
	196
119f5e44 MD	197	static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
	198	{
	199	struct gpio_rcar_priv *p = dev_id;
	200	u32 pending;
	201	unsigned int offset, irqs_handled = 0;
	202
8808b64d VB	203	while ((pending = gpio_rcar_read(p, INTDT) &
8808b64d VB	204	gpio_rcar_read(p, INTMSK))) {
119f5e44 MD	205	offset = __ffs(pending);
119f5e44 MD	206	gpio_rcar_write(p, INTCLR, BIT(offset));
f0fbe7bc	207	generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
c7f3c5d3	208	offset));
119f5e44 MD	209	irqs_handled++;
	210	}
	211
	212	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	213	}
	214
119f5e44 MD	215	static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
	216	unsigned int gpio,
	217	bool output)
	218	{
c7b6f457	219	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	220	unsigned long flags;
	221
	222	/* follow steps in the GPIO documentation for
	223	* "Setting General Output Mode" and
	224	* "Setting General Input Mode"
	225	*/
	226
	227	spin_lock_irqsave(&p->lock, flags);
	228
	229	/* Configure postive logic in POSNEG */
	230	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
	231
	232	/* Select "General Input/Output Mode" in IOINTSEL */
	233	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
	234
	235	/* Select Input Mode or Output Mode in INOUTSEL */
	236	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
	237
	238	spin_unlock_irqrestore(&p->lock, flags);
	239	}
	240
dc3465a9 LP	241	static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
dc3465a9 LP	242	{
2d65472b GU	243	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	244	int error;
	245
a53f7953	246	error = pm_runtime_get_sync(p->dev);
2d65472b GU	247	if (error < 0)
	248	return error;
	249
a9a1d2a7	250	error = pinctrl_gpio_request(chip->base + offset);
2d65472b	251	if (error)
a53f7953	252	pm_runtime_put(p->dev);
2d65472b GU	253
2d65472b GU	254	return error;
dc3465a9 LP	255	}
	256
	257	static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
	258	{
2d65472b GU	259	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
2d65472b GU	260
a9a1d2a7	261	pinctrl_gpio_free(chip->base + offset);
dc3465a9	262
ce0e2c60 LW	263	/*
ce0e2c60 LW	264	* Set the GPIO as an input to ensure that the next GPIO request won't
dc3465a9 LP	265	* drive the GPIO pin as an output.
	266	*/
	267	gpio_rcar_config_general_input_output_mode(chip, offset, false);
2d65472b	268
a53f7953	269	pm_runtime_put(p->dev);
dc3465a9 LP	270	}
dc3465a9 LP	271
ad817297 GU	272	static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
	273	{
	274	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	275
	276	return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
	277	}
	278
119f5e44 MD	279	static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
	280	{
	281	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	282	return 0;
	283	}
	284
	285	static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
	286	{
ae9550f6 MD	287	u32 bit = BIT(offset);
	288
	289	/* testing on r8a7790 shows that INDT does not show correct pin state
	290	* when configured as output, so use OUTDT in case of output pins */
c7b6f457 LW	291	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
c7b6f457 LW	292	return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
ae9550f6	293	else
c7b6f457	294	return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
119f5e44 MD	295	}
	296
	297	static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
	298	{
c7b6f457	299	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	300	unsigned long flags;
	301
	302	spin_lock_irqsave(&p->lock, flags);
	303	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	304	spin_unlock_irqrestore(&p->lock, flags);
	305	}
	306
dbb763b8 GU	307	static void gpio_rcar_set_multiple(struct gpio_chip chip, unsigned long mask,
	308	unsigned long *bits)
	309	{
	310	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	311	unsigned long flags;
	312	u32 val, bankmask;
	313
	314	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
496069b8 BD	315	if (chip->valid_mask)
	316	bankmask &= chip->valid_mask[0];
	317
dbb763b8 GU	318	if (!bankmask)
	319	return;
	320
	321	spin_lock_irqsave(&p->lock, flags);
	322	val = gpio_rcar_read(p, OUTDT);
	323	val &= ~bankmask;
	324	val \|= (bankmask & bits[0]);
	325	gpio_rcar_write(p, OUTDT, val);
	326	spin_unlock_irqrestore(&p->lock, flags);
	327	}
	328
119f5e44 MD	329	static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
	330	int value)
	331	{
	332	/* write GPIO value to output before selecting output mode of pin */
	333	gpio_rcar_set(chip, offset, value);
	334	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	335	return 0;
	336	}
	337
850dfe17 LP	338	struct gpio_rcar_info {
	339	bool has_both_edge_trigger;
	340	};
	341
1fd2b49d HN	342	static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
	343	.has_both_edge_trigger = false,
	344	};
	345
	346	static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
	347	.has_both_edge_trigger = true,
	348	};
	349
850dfe17 LP	350	static const struct of_device_id gpio_rcar_of_table[] = {
850dfe17 LP	351	{
85bb4646 BD	352	.compatible = "renesas,gpio-r8a7743",
	353	/* RZ/G1 GPIO is identical to R-Car Gen2. */
	354	.data = &gpio_rcar_info_gen2,
	355	}, {
850dfe17	356	.compatible = "renesas,gpio-r8a7790",
1fd2b49d	357	.data = &gpio_rcar_info_gen2,
850dfe17 LP	358	}, {
850dfe17 LP	359	.compatible = "renesas,gpio-r8a7791",
1fd2b49d	360	.data = &gpio_rcar_info_gen2,
e79c5830 SS	361	}, {
	362	.compatible = "renesas,gpio-r8a7792",
	363	.data = &gpio_rcar_info_gen2,
1fd2b49d HN	364	}, {
	365	.compatible = "renesas,gpio-r8a7793",
	366	.data = &gpio_rcar_info_gen2,
	367	}, {
	368	.compatible = "renesas,gpio-r8a7794",
	369	.data = &gpio_rcar_info_gen2,
8cd14702 UH	370	}, {
	371	.compatible = "renesas,gpio-r8a7795",
	372	/* Gen3 GPIO is identical to Gen2. */
	373	.data = &gpio_rcar_info_gen2,
5d2f1d6e SH	374	}, {
	375	.compatible = "renesas,gpio-r8a7796",
	376	/* Gen3 GPIO is identical to Gen2. */
	377	.data = &gpio_rcar_info_gen2,
dbd1dad2 SH	378	}, {
	379	.compatible = "renesas,rcar-gen1-gpio",
	380	.data = &gpio_rcar_info_gen1,
	381	}, {
	382	.compatible = "renesas,rcar-gen2-gpio",
	383	.data = &gpio_rcar_info_gen2,
	384	}, {
	385	.compatible = "renesas,rcar-gen3-gpio",
	386	/* Gen3 GPIO is identical to Gen2. */
	387	.data = &gpio_rcar_info_gen2,
850dfe17 LP	388	}, {
850dfe17 LP	389	.compatible = "renesas,gpio-rcar",
1fd2b49d	390	.data = &gpio_rcar_info_gen1,
850dfe17 LP	391	}, {
	392	/* Terminator */
	393	},
	394	};
	395
	396	MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
	397
8b092be9	398	static int gpio_rcar_parse_dt(struct gpio_rcar_priv p, unsigned int npins)
159f8a02	399	{
a53f7953	400	struct device_node *np = p->dev->of_node;
8b092be9	401	const struct gpio_rcar_info *info;
159f8a02 LP	402	struct of_phandle_args args;
159f8a02 LP	403	int ret;
159f8a02	404
a53f7953	405	info = of_device_get_match_data(p->dev);
850dfe17	406
8b092be9 GU	407	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
	408	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
	409	p->has_both_edge_trigger = info->has_both_edge_trigger;
850dfe17	410
8b092be9	411	if (npins == 0 \|\| npins > RCAR_MAX_GPIO_PER_BANK) {
a53f7953 VZ	412	dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
a53f7953 VZ	413	*npins, RCAR_MAX_GPIO_PER_BANK);
8b092be9	414	*npins = RCAR_MAX_GPIO_PER_BANK;
159f8a02	415	}
850dfe17 LP	416
850dfe17 LP	417	return 0;
159f8a02 LP	418	}
159f8a02 LP	419
119f5e44 MD	420	static int gpio_rcar_probe(struct platform_device *pdev)
119f5e44 MD	421	{
119f5e44 MD	422	struct gpio_rcar_priv *p;
	423	struct resource io, irq;
	424	struct gpio_chip *gpio_chip;
	425	struct irq_chip *irq_chip;
b22978fc GU	426	struct device *dev = &pdev->dev;
b22978fc GU	427	const char *name = dev_name(dev);
8b092be9	428	unsigned int npins;
119f5e44 MD	429	int ret;
119f5e44 MD	430
b22978fc	431	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
7d82bf34 GU	432	if (!p)
7d82bf34 GU	433	return -ENOMEM;
119f5e44	434
a53f7953	435	p->dev = dev;
119f5e44 MD	436	spin_lock_init(&p->lock);
119f5e44 MD	437
8b092be9 GU	438	/* Get device configuration from DT node */
8b092be9 GU	439	ret = gpio_rcar_parse_dt(p, &npins);
850dfe17 LP	440	if (ret < 0)
850dfe17 LP	441	return ret;
159f8a02 LP	442
	443	platform_set_drvdata(pdev, p);
	444
df0c6c80	445	pm_runtime_enable(dev);
df0c6c80	446
119f5e44	447	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
5a24d4b6 SS	448	if (!irq) {
5a24d4b6 SS	449	dev_err(dev, "missing IRQ\n");
119f5e44 MD	450	ret = -EINVAL;
	451	goto err0;
	452	}
	453
5a24d4b6 SS	454	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	455	p->base = devm_ioremap_resource(dev, io);
	456	if (IS_ERR(p->base)) {
	457	ret = PTR_ERR(p->base);
119f5e44 MD	458	goto err0;
	459	}
	460
	461	gpio_chip = &p->gpio_chip;
dc3465a9 LP	462	gpio_chip->request = gpio_rcar_request;
dc3465a9 LP	463	gpio_chip->free = gpio_rcar_free;
ad817297	464	gpio_chip->get_direction = gpio_rcar_get_direction;
119f5e44 MD	465	gpio_chip->direction_input = gpio_rcar_direction_input;
	466	gpio_chip->get = gpio_rcar_get;
	467	gpio_chip->direction_output = gpio_rcar_direction_output;
	468	gpio_chip->set = gpio_rcar_set;
dbb763b8	469	gpio_chip->set_multiple = gpio_rcar_set_multiple;
119f5e44	470	gpio_chip->label = name;
58383c78	471	gpio_chip->parent = dev;
119f5e44	472	gpio_chip->owner = THIS_MODULE;
8b092be9 GU	473	gpio_chip->base = -1;
8b092be9 GU	474	gpio_chip->ngpio = npins;
119f5e44 MD	475
	476	irq_chip = &p->irq_chip;
	477	irq_chip->name = name;
47bd38a3	478	irq_chip->parent_device = dev;
119f5e44 MD	479	irq_chip->irq_mask = gpio_rcar_irq_disable;
119f5e44 MD	480	irq_chip->irq_unmask = gpio_rcar_irq_enable;
119f5e44	481	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
ab82fa7d GU	482	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
ab82fa7d GU	483	irq_chip->flags = IRQCHIP_SET_TYPE_MASKED \| IRQCHIP_MASK_ON_SUSPEND;
119f5e44	484
c7b6f457	485	ret = gpiochip_add_data(gpio_chip, p);
c7f3c5d3 GU	486	if (ret) {
c7f3c5d3 GU	487	dev_err(dev, "failed to add GPIO controller\n");
0c8aab8e	488	goto err0;
119f5e44 MD	489	}
119f5e44 MD	490
8b092be9 GU	491	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
8b092be9 GU	492	IRQ_TYPE_NONE);
c7f3c5d3 GU	493	if (ret) {
	494	dev_err(dev, "cannot add irqchip\n");
	495	goto err1;
	496	}
	497
ab82fa7d	498	p->irq_parent = irq->start;
b22978fc GU	499	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
	500	IRQF_SHARED, name, p)) {
	501	dev_err(dev, "failed to request IRQ\n");
119f5e44 MD	502	ret = -ENOENT;
	503	goto err1;
	504	}
	505
8b092be9	506	dev_info(dev, "driving %d GPIOs\n", npins);
dc3465a9	507
119f5e44 MD	508	return 0;
	509
	510	err1:
4d84b9e4	511	gpiochip_remove(gpio_chip);
119f5e44	512	err0:
df0c6c80	513	pm_runtime_disable(dev);
119f5e44 MD	514	return ret;
	515	}
	516
	517	static int gpio_rcar_remove(struct platform_device *pdev)
	518	{
	519	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
119f5e44	520
9f5132ae	521	gpiochip_remove(&p->gpio_chip);
119f5e44	522
df0c6c80	523	pm_runtime_disable(&pdev->dev);
119f5e44 MD	524	return 0;
	525	}
	526
51750fb1 HD	527	#ifdef CONFIG_PM_SLEEP
	528	static int gpio_rcar_suspend(struct device *dev)
	529	{
	530	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	531
	532	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
	533	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
	534	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
	535	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
	536	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
	537	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
	538	if (p->has_both_edge_trigger)
	539	p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
	540
9ac79ba9 GU	541	if (atomic_read(&p->wakeup_path))
	542	device_set_wakeup_path(dev);
	543
51750fb1 HD	544	return 0;
	545	}
	546
	547	static int gpio_rcar_resume(struct device *dev)
	548	{
	549	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	550	unsigned int offset;
	551	u32 mask;
	552
	553	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
496069b8 BD	554	if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
	555	continue;
	556
51750fb1 HD	557	mask = BIT(offset);
	558	/* I/O pin */
	559	if (!(p->bank_info.iointsel & mask)) {
	560	if (p->bank_info.inoutsel & mask)
	561	gpio_rcar_direction_output(
	562	&p->gpio_chip, offset,
	563	!!(p->bank_info.outdt & mask));
	564	else
	565	gpio_rcar_direction_input(&p->gpio_chip,
	566	offset);
	567	} else {
	568	/* Interrupt pin */
	569	gpio_rcar_config_interrupt_input_mode(
	570	p,
	571	offset,
	572	!(p->bank_info.posneg & mask),
	573	!(p->bank_info.edglevel & mask),
	574	!!(p->bank_info.bothedge & mask));
	575
	576	if (p->bank_info.intmsk & mask)
	577	gpio_rcar_write(p, MSKCLR, mask);
	578	}
	579	}
	580
	581	return 0;
	582	}
	583	#endif /* CONFIG_PM_SLEEP*/
	584
	585	static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
	586
119f5e44 MD	587	static struct platform_driver gpio_rcar_device_driver = {
	588	.probe = gpio_rcar_probe,
	589	.remove = gpio_rcar_remove,
	590	.driver = {
	591	.name = "gpio_rcar",
51750fb1	592	.pm = &gpio_rcar_pm_ops,
159f8a02	593	.of_match_table = of_match_ptr(gpio_rcar_of_table),
119f5e44 MD	594	}
	595	};
	596
	597	module_platform_driver(gpio_rcar_device_driver);
	598
	599	MODULE_AUTHOR("Magnus Damm");
	600	MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
	601	MODULE_LICENSE("GPL v2");