[linux-2.6-block.git] / drivers / gpio / gpio-octeon.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2011, 2012 Cavium Inc.
 */

#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/io.h>

#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-gpio-defs.h>

#define RX_DAT 0x80
#define TX_SET 0x88
#define TX_CLEAR 0x90
/*
 * The address offset of the GPIO configuration register for a given
 * line.
 */
static unsigned int bit_cfg_reg(unsigned int offset)
{
	/*
	 * The register stride is 8, with a discontinuity after the
	 * first 16.
	 */
	if (offset < 16)
		return 8 * offset;
	else
		return 8 * (offset - 16) + 0x100;
}

struct octeon_gpio {
	struct gpio_chip chip;
	u64 register_base;
};

static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
{
	struct octeon_gpio *gpio = gpiochip_get_data(chip);

	cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
	return 0;
}

static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct octeon_gpio *gpio = gpiochip_get_data(chip);
	u64 mask = 1ull << offset;
	u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
	cvmx_write_csr(reg, mask);
}

static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
			       int value)
{
	struct octeon_gpio *gpio = gpiochip_get_data(chip);
	union cvmx_gpio_bit_cfgx cfgx;

	octeon_gpio_set(chip, offset, value);

	cfgx.u64 = 0;
	cfgx.s.tx_oe = 1;

	cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
	return 0;
}

static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct octeon_gpio *gpio = gpiochip_get_data(chip);
	u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);

	return ((1ull << offset) & read_bits) != 0;
}

static int octeon_gpio_probe(struct platform_device *pdev)
{
	struct octeon_gpio *gpio;
	struct gpio_chip *chip;
	struct resource *res_mem;
	int err = 0;

	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	if (!gpio)
		return -ENOMEM;
	chip = &gpio->chip;

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res_mem == NULL) {
		dev_err(&pdev->dev, "found no memory resource\n");
		err = -ENXIO;
		goto out;
	}
	if (!devm_request_mem_region(&pdev->dev, res_mem->start,
					resource_size(res_mem),
				     res_mem->name)) {
		dev_err(&pdev->dev, "request_mem_region failed\n");
		err = -ENXIO;
		goto out;
	}
	gpio->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
						resource_size(res_mem));

	pdev->dev.platform_data = chip;
	chip->label = "octeon-gpio";
	chip->parent = &pdev->dev;
	chip->owner = THIS_MODULE;
	chip->base = 0;
	chip->can_sleep = false;
	chip->ngpio = 20;
	chip->direction_input = octeon_gpio_dir_in;
	chip->get = octeon_gpio_get;
	chip->direction_output = octeon_gpio_dir_out;
	chip->set = octeon_gpio_set;
	err = devm_gpiochip_add_data(&pdev->dev, chip, gpio);
	if (err)
		goto out;

	dev_info(&pdev->dev, "OCTEON GPIO driver probed.\n");
out:
	return err;
}

static struct of_device_id octeon_gpio_match[] = {
	{
		.compatible = "cavium,octeon-3860-gpio",
	},
	{},
};
MODULE_DEVICE_TABLE(of, octeon_gpio_match);

static struct platform_driver octeon_gpio_driver = {
	.driver = {
		.name		= "octeon_gpio",
		.of_match_table = octeon_gpio_match,
	},
	.probe		= octeon_gpio_probe,
};

module_platform_driver(octeon_gpio_driver);

MODULE_DESCRIPTION("Cavium Inc. OCTEON GPIO Driver");
MODULE_AUTHOR("David Daney");
MODULE_LICENSE("GPL");
Commit	Line	Data
aca58a66 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2011, 2012 Cavium Inc.
	7	*/
	8
	9	#include <linux/platform_device.h>
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/gpio.h>
	13	#include <linux/io.h>
	14
	15	#include <asm/octeon/octeon.h>
	16	#include <asm/octeon/cvmx-gpio-defs.h>
	17
	18	#define RX_DAT 0x80
	19	#define TX_SET 0x88
	20	#define TX_CLEAR 0x90
	21	/*
	22	* The address offset of the GPIO configuration register for a given
	23	* line.
	24	*/
	25	static unsigned int bit_cfg_reg(unsigned int offset)
	26	{
	27	/*
	28	* The register stride is 8, with a discontinuity after the
	29	* first 16.
	30	*/
	31	if (offset < 16)
	32	return 8 * offset;
	33	else
	34	return 8 * (offset - 16) + 0x100;
	35	}
	36
	37	struct octeon_gpio {
	38	struct gpio_chip chip;
	39	u64 register_base;
	40	};
	41
	42	static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
	43	{
f5cc554e	44	struct octeon_gpio *gpio = gpiochip_get_data(chip);
aca58a66 DD	45
	46	cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
	47	return 0;
	48	}
	49
	50	static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	51	{
f5cc554e	52	struct octeon_gpio *gpio = gpiochip_get_data(chip);
aca58a66 DD	53	u64 mask = 1ull << offset;
	54	u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
	55	cvmx_write_csr(reg, mask);
	56	}
	57
	58	static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
	59	int value)
	60	{
f5cc554e	61	struct octeon_gpio *gpio = gpiochip_get_data(chip);
aca58a66 DD	62	union cvmx_gpio_bit_cfgx cfgx;
	63
	64	octeon_gpio_set(chip, offset, value);
	65
	66	cfgx.u64 = 0;
	67	cfgx.s.tx_oe = 1;
	68
	69	cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
	70	return 0;
	71	}
	72
	73	static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
	74	{
f5cc554e	75	struct octeon_gpio *gpio = gpiochip_get_data(chip);
aca58a66 DD	76	u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
	77
	78	return ((1ull << offset) & read_bits) != 0;
	79	}
	80
	81	static int octeon_gpio_probe(struct platform_device *pdev)
	82	{
	83	struct octeon_gpio *gpio;
	84	struct gpio_chip *chip;
	85	struct resource *res_mem;
	86	int err = 0;
	87
	88	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	89	if (!gpio)
	90	return -ENOMEM;
	91	chip = &gpio->chip;
	92
	93	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	94	if (res_mem == NULL) {
	95	dev_err(&pdev->dev, "found no memory resource\n");
	96	err = -ENXIO;
	97	goto out;
	98	}
	99	if (!devm_request_mem_region(&pdev->dev, res_mem->start,
	100	resource_size(res_mem),
	101	res_mem->name)) {
	102	dev_err(&pdev->dev, "request_mem_region failed\n");
	103	err = -ENXIO;
	104	goto out;
	105	}
	106	gpio->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
	107	resource_size(res_mem));
	108
	109	pdev->dev.platform_data = chip;
	110	chip->label = "octeon-gpio";
58383c78	111	chip->parent = &pdev->dev;
aca58a66 DD	112	chip->owner = THIS_MODULE;
aca58a66 DD	113	chip->base = 0;
9fb1f39e	114	chip->can_sleep = false;
aca58a66 DD	115	chip->ngpio = 20;
	116	chip->direction_input = octeon_gpio_dir_in;
	117	chip->get = octeon_gpio_get;
	118	chip->direction_output = octeon_gpio_dir_out;
	119	chip->set = octeon_gpio_set;
1533d4fd	120	err = devm_gpiochip_add_data(&pdev->dev, chip, gpio);
aca58a66 DD	121	if (err)
	122	goto out;
	123
	124	dev_info(&pdev->dev, "OCTEON GPIO driver probed.\n");
	125	out:
	126	return err;
	127	}
	128
aca58a66 DD	129	static struct of_device_id octeon_gpio_match[] = {
	130	{
	131	.compatible = "cavium,octeon-3860-gpio",
	132	},
	133	{},
	134	};
	135	MODULE_DEVICE_TABLE(of, octeon_gpio_match);
	136
	137	static struct platform_driver octeon_gpio_driver = {
	138	.driver = {
	139	.name = "octeon_gpio",
aca58a66 DD	140	.of_match_table = octeon_gpio_match,
	141	},
	142	.probe = octeon_gpio_probe,
aca58a66 DD	143	};
	144
	145	module_platform_driver(octeon_gpio_driver);
	146
	147	MODULE_DESCRIPTION("Cavium Inc. OCTEON GPIO Driver");
	148	MODULE_AUTHOR("David Daney");
	149	MODULE_LICENSE("GPL");