[linux-2.6-block.git] / drivers / gpio / gpio-f7188x.c

/*
 * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
 *
 * Copyright (C) 2010-2013 LaCie
 *
 * Author: Simon Guinot <simon.guinot@sequanux.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>

#define DRVNAME "gpio-f7188x"

/*
 * Super-I/O registers
 */
#define SIO_LDSEL		0x07	/* Logical device select */
#define SIO_DEVID		0x20	/* Device ID (2 bytes) */
#define SIO_DEVREV		0x22	/* Device revision */
#define SIO_MANID		0x23	/* Fintek ID (2 bytes) */

#define SIO_LD_GPIO		0x06	/* GPIO logical device */
#define SIO_UNLOCK_KEY		0x87	/* Key to enable Super-I/O */
#define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */

#define SIO_FINTEK_ID		0x1934	/* Manufacturer ID */
#define SIO_F71869_ID		0x0814	/* F71869 chipset ID */
#define SIO_F71869A_ID		0x1007	/* F71869A chipset ID */
#define SIO_F71882_ID		0x0541	/* F71882 chipset ID */
#define SIO_F71889_ID		0x0909	/* F71889 chipset ID */
#define SIO_F81866_ID		0x1010	/* F81866 chipset ID */

enum chips { f71869, f71869a, f71882fg, f71889f, f81866 };

static const char * const f7188x_names[] = {
	"f71869",
	"f71869a",
	"f71882fg",
	"f71889f",
	"f81866",
};

struct f7188x_sio {
	int addr;
	enum chips type;
};

struct f7188x_gpio_bank {
	struct gpio_chip chip;
	unsigned int regbase;
	struct f7188x_gpio_data *data;
};

struct f7188x_gpio_data {
	struct f7188x_sio *sio;
	int nr_bank;
	struct f7188x_gpio_bank *bank;
};

/*
 * Super-I/O functions.
 */

static inline int superio_inb(int base, int reg)
{
	outb(reg, base);
	return inb(base + 1);
}

static int superio_inw(int base, int reg)
{
	int val;

	outb(reg++, base);
	val = inb(base + 1) << 8;
	outb(reg, base);
	val |= inb(base + 1);

	return val;
}

static inline void superio_outb(int base, int reg, int val)
{
	outb(reg, base);
	outb(val, base + 1);
}

static inline int superio_enter(int base)
{
	/* Don't step on other drivers' I/O space by accident. */
	if (!request_muxed_region(base, 2, DRVNAME)) {
		pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
		return -EBUSY;
	}

	/* According to the datasheet the key must be send twice. */
	outb(SIO_UNLOCK_KEY, base);
	outb(SIO_UNLOCK_KEY, base);

	return 0;
}

static inline void superio_select(int base, int ld)
{
	outb(SIO_LDSEL, base);
	outb(ld, base + 1);
}

static inline void superio_exit(int base)
{
	outb(SIO_LOCK_KEY, base);
	release_region(base, 2);
}

/*
 * GPIO chip.
 */

static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value);
static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);

#define F7188X_GPIO_BANK(_base, _ngpio, _regbase)			\
	{								\
		.chip = {						\
			.label            = DRVNAME,			\
			.owner            = THIS_MODULE,		\
			.direction_input  = f7188x_gpio_direction_in,	\
			.get              = f7188x_gpio_get,		\
			.direction_output = f7188x_gpio_direction_out,	\
			.set              = f7188x_gpio_set,		\
			.base             = _base,			\
			.ngpio            = _ngpio,			\
			.can_sleep        = true,			\
		},							\
		.regbase = _regbase,					\
	}

#define gpio_dir(base) (base + 0)
#define gpio_data_out(base) (base + 1)
#define gpio_data_in(base) (base + 2)
/* Output mode register (0:open drain 1:push-pull). */
#define gpio_out_mode(base) (base + 3)

static struct f7188x_gpio_bank f71869_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 6, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 6, 0x90),
};

static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 6, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
};

static struct f7188x_gpio_bank f71882_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 8, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 4, 0xC0),
	F7188X_GPIO_BANK(40, 4, 0xB0),
};

static struct f7188x_gpio_bank f71889_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 7, 0xF0),
	F7188X_GPIO_BANK(10, 7, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
};

static struct f7188x_gpio_bank f81866_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 8, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 8, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
	F7188X_GPIO_BANK(80, 8, 0x88),
};

static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir &= ~(1 << offset);
	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir = !!(dir & (1 << offset));
	if (dir)
		data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	else
		data = superio_inb(sio->addr, gpio_data_in(bank->regbase));

	superio_exit(sio->addr);

	return !!(data & 1 << offset);
}

static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data_out;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	if (value)
		data_out |= (1 << offset);
	else
		data_out &= ~(1 << offset);
	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir |= (1 << offset);
	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 data_out;

	err = superio_enter(sio->addr);
	if (err)
		return;
	superio_select(sio->addr, SIO_LD_GPIO);

	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	if (value)
		data_out |= (1 << offset);
	else
		data_out &= ~(1 << offset);
	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);

	superio_exit(sio->addr);
}

/*
 * Platform device and driver.
 */

static int f7188x_gpio_probe(struct platform_device *pdev)
{
	int err;
	int i;
	struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
	struct f7188x_gpio_data *data;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	switch (sio->type) {
	case f71869:
		data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
		data->bank = f71869_gpio_bank;
		break;
	case f71869a:
		data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
		data->bank = f71869a_gpio_bank;
		break;
	case f71882fg:
		data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
		data->bank = f71882_gpio_bank;
		break;
	case f71889f:
		data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
		data->bank = f71889_gpio_bank;
		break;
	case f81866:
		data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
		data->bank = f81866_gpio_bank;
		break;
	default:
		return -ENODEV;
	}
	data->sio = sio;

	platform_set_drvdata(pdev, data);

	/* For each GPIO bank, register a GPIO chip. */
	for (i = 0; i < data->nr_bank; i++) {
		struct f7188x_gpio_bank *bank = &data->bank[i];

		bank->chip.parent = &pdev->dev;
		bank->data = data;

		err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
		if (err) {
			dev_err(&pdev->dev,
				"Failed to register gpiochip %d: %d\n",
				i, err);
			return err;
		}
	}

	return 0;
}

static int __init f7188x_find(int addr, struct f7188x_sio *sio)
{
	int err;
	u16 devid;

	err = superio_enter(addr);
	if (err)
		return err;

	err = -ENODEV;
	devid = superio_inw(addr, SIO_MANID);
	if (devid != SIO_FINTEK_ID) {
		pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
		goto err;
	}

	devid = superio_inw(addr, SIO_DEVID);
	switch (devid) {
	case SIO_F71869_ID:
		sio->type = f71869;
		break;
	case SIO_F71869A_ID:
		sio->type = f71869a;
		break;
	case SIO_F71882_ID:
		sio->type = f71882fg;
		break;
	case SIO_F71889_ID:
		sio->type = f71889f;
		break;
	case SIO_F81866_ID:
		sio->type = f81866;
		break;
	default:
		pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
		goto err;
	}
	sio->addr = addr;
	err = 0;

	pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
		f7188x_names[sio->type],
		(unsigned int) addr,
		(int) superio_inb(addr, SIO_DEVREV));

err:
	superio_exit(addr);
	return err;
}

static struct platform_device *f7188x_gpio_pdev;

static int __init
f7188x_gpio_device_add(const struct f7188x_sio *sio)
{
	int err;

	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	if (!f7188x_gpio_pdev)
		return -ENOMEM;

	err = platform_device_add_data(f7188x_gpio_pdev,
				       sio, sizeof(*sio));
	if (err) {
		pr_err(DRVNAME "Platform data allocation failed\n");
		goto err;
	}

	err = platform_device_add(f7188x_gpio_pdev);
	if (err) {
		pr_err(DRVNAME "Device addition failed\n");
		goto err;
	}

	return 0;

err:
	platform_device_put(f7188x_gpio_pdev);

	return err;
}

/*
 * Try to match a supported Fintek device by reading the (hard-wired)
 * configuration I/O ports. If available, then register both the platform
 * device and driver to support the GPIOs.
 */

static struct platform_driver f7188x_gpio_driver = {
	.driver = {
		.name	= DRVNAME,
	},
	.probe		= f7188x_gpio_probe,
};

static int __init f7188x_gpio_init(void)
{
	int err;
	struct f7188x_sio sio;

	if (f7188x_find(0x2e, &sio) &&
	    f7188x_find(0x4e, &sio))
		return -ENODEV;

	err = platform_driver_register(&f7188x_gpio_driver);
	if (!err) {
		err = f7188x_gpio_device_add(&sio);
		if (err)
			platform_driver_unregister(&f7188x_gpio_driver);
	}

	return err;
}
subsys_initcall(f7188x_gpio_init);

static void __exit f7188x_gpio_exit(void)
{
	platform_device_unregister(f7188x_gpio_pdev);
	platform_driver_unregister(&f7188x_gpio_driver);
}
module_exit(f7188x_gpio_exit);

MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889F and F81866");
MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
6c17aa01	1	/*
1920906f	2	* GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
6c17aa01 SG	3	*
	4	* Copyright (C) 2010-2013 LaCie
	5	*
	6	* Author: Simon Guinot <simon.guinot@sequanux.org>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/io.h>
	18	#include <linux/gpio.h>
	19
	20	#define DRVNAME "gpio-f7188x"
	21
	22	/*
	23	* Super-I/O registers
	24	*/
	25	#define SIO_LDSEL 0x07 /* Logical device select */
	26	#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
	27	#define SIO_DEVREV 0x22 /* Device revision */
	28	#define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
	29
	30	#define SIO_LD_GPIO 0x06 /* GPIO logical device */
	31	#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
	32	#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
	33
	34	#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
24ccef35	35	#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
7e960363	36	#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
6c17aa01 SG	37	#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
6c17aa01 SG	38	#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
1920906f	39	#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
6c17aa01	40
1920906f	41	enum chips { f71869, f71869a, f71882fg, f71889f, f81866 };
6c17aa01 SG	42
6c17aa01 SG	43	static const char * const f7188x_names[] = {
24ccef35	44	"f71869",
7e960363	45	"f71869a",
6c17aa01 SG	46	"f71882fg",
6c17aa01 SG	47	"f71889f",
1920906f	48	"f81866",
6c17aa01 SG	49	};
	50
	51	struct f7188x_sio {
	52	int addr;
	53	enum chips type;
	54	};
	55
	56	struct f7188x_gpio_bank {
	57	struct gpio_chip chip;
	58	unsigned int regbase;
	59	struct f7188x_gpio_data *data;
	60	};
	61
	62	struct f7188x_gpio_data {
	63	struct f7188x_sio *sio;
	64	int nr_bank;
	65	struct f7188x_gpio_bank *bank;
	66	};
	67
	68	/*
	69	* Super-I/O functions.
	70	*/
	71
	72	static inline int superio_inb(int base, int reg)
	73	{
	74	outb(reg, base);
	75	return inb(base + 1);
	76	}
	77
	78	static int superio_inw(int base, int reg)
	79	{
	80	int val;
	81
	82	outb(reg++, base);
	83	val = inb(base + 1) << 8;
	84	outb(reg, base);
	85	val \|= inb(base + 1);
	86
	87	return val;
	88	}
	89
	90	static inline void superio_outb(int base, int reg, int val)
	91	{
	92	outb(reg, base);
	93	outb(val, base + 1);
	94	}
	95
	96	static inline int superio_enter(int base)
	97	{
	98	/* Don't step on other drivers' I/O space by accident. */
	99	if (!request_muxed_region(base, 2, DRVNAME)) {
	100	pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
	101	return -EBUSY;
	102	}
	103
	104	/* According to the datasheet the key must be send twice. */
	105	outb(SIO_UNLOCK_KEY, base);
	106	outb(SIO_UNLOCK_KEY, base);
	107
	108	return 0;
	109	}
	110
	111	static inline void superio_select(int base, int ld)
	112	{
113	outb(SIO_LDSEL, base);
114	outb(ld, base + 1);
115	}
116
117	static inline void superio_exit(int base)
118	{
119	outb(SIO_LOCK_KEY, base);
120	release_region(base, 2);
121	}
122
123	/*
124	* GPIO chip.
125	*/
126
127	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
128	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
129	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
130	unsigned offset, int value);
131	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
132
133	#define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
134	{ \
135	.chip = { \
136	.label = DRVNAME, \
137	.owner = THIS_MODULE, \
138	.direction_input = f7188x_gpio_direction_in, \
139	.get = f7188x_gpio_get, \
140	.direction_output = f7188x_gpio_direction_out, \
141	.set = f7188x_gpio_set, \
142	.base = _base, \
143	.ngpio = _ngpio, \
aeccc1b4	144	.can_sleep = true, \
6c17aa01 SG	145	}, \
	146	.regbase = _regbase, \
	147	}
	148
	149	#define gpio_dir(base) (base + 0)
	150	#define gpio_data_out(base) (base + 1)
	151	#define gpio_data_in(base) (base + 2)
	152	/* Output mode register (0:open drain 1:push-pull). */
	153	#define gpio_out_mode(base) (base + 3)
	154
24ccef35 AB	155	static struct f7188x_gpio_bank f71869_gpio_bank[] = {
	156	F7188X_GPIO_BANK(0, 6, 0xF0),
	157	F7188X_GPIO_BANK(10, 8, 0xE0),
	158	F7188X_GPIO_BANK(20, 8, 0xD0),
	159	F7188X_GPIO_BANK(30, 8, 0xC0),
	160	F7188X_GPIO_BANK(40, 8, 0xB0),
	161	F7188X_GPIO_BANK(50, 5, 0xA0),
	162	F7188X_GPIO_BANK(60, 6, 0x90),
	163	};
	164
7e960363 AB	165	static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
	166	F7188X_GPIO_BANK(0, 6, 0xF0),
	167	F7188X_GPIO_BANK(10, 8, 0xE0),
	168	F7188X_GPIO_BANK(20, 8, 0xD0),
	169	F7188X_GPIO_BANK(30, 8, 0xC0),
	170	F7188X_GPIO_BANK(40, 8, 0xB0),
	171	F7188X_GPIO_BANK(50, 5, 0xA0),
	172	F7188X_GPIO_BANK(60, 8, 0x90),
	173	F7188X_GPIO_BANK(70, 8, 0x80),
	174	};
	175
6c17aa01	176	static struct f7188x_gpio_bank f71882_gpio_bank[] = {
38e003f4	177	F7188X_GPIO_BANK(0, 8, 0xF0),
6c17aa01 SG	178	F7188X_GPIO_BANK(10, 8, 0xE0),
	179	F7188X_GPIO_BANK(20, 8, 0xD0),
	180	F7188X_GPIO_BANK(30, 4, 0xC0),
	181	F7188X_GPIO_BANK(40, 4, 0xB0),
	182	};
	183
	184	static struct f7188x_gpio_bank f71889_gpio_bank[] = {
38e003f4	185	F7188X_GPIO_BANK(0, 7, 0xF0),
6c17aa01 SG	186	F7188X_GPIO_BANK(10, 7, 0xE0),
	187	F7188X_GPIO_BANK(20, 8, 0xD0),
	188	F7188X_GPIO_BANK(30, 8, 0xC0),
	189	F7188X_GPIO_BANK(40, 8, 0xB0),
	190	F7188X_GPIO_BANK(50, 5, 0xA0),
	191	F7188X_GPIO_BANK(60, 8, 0x90),
	192	F7188X_GPIO_BANK(70, 8, 0x80),
	193	};
	194
1920906f PH	195	static struct f7188x_gpio_bank f81866_gpio_bank[] = {
	196	F7188X_GPIO_BANK(0, 8, 0xF0),
	197	F7188X_GPIO_BANK(10, 8, 0xE0),
	198	F7188X_GPIO_BANK(20, 8, 0xD0),
	199	F7188X_GPIO_BANK(30, 8, 0xC0),
	200	F7188X_GPIO_BANK(40, 8, 0xB0),
	201	F7188X_GPIO_BANK(50, 8, 0xA0),
	202	F7188X_GPIO_BANK(60, 8, 0x90),
	203	F7188X_GPIO_BANK(70, 8, 0x80),
	204	F7188X_GPIO_BANK(80, 8, 0x88),
	205	};
	206
6c17aa01 SG	207	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
	208	{
	209	int err;
f372d5f5	210	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	211	struct f7188x_sio *sio = bank->data->sio;
	212	u8 dir;
	213
	214	err = superio_enter(sio->addr);
	215	if (err)
	216	return err;
	217	superio_select(sio->addr, SIO_LD_GPIO);
	218
	219	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	220	dir &= ~(1 << offset);
	221	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
	222
	223	superio_exit(sio->addr);
	224
	225	return 0;
	226	}
	227
	228	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
	229	{
	230	int err;
f372d5f5	231	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	232	struct f7188x_sio *sio = bank->data->sio;
	233	u8 dir, data;
	234
	235	err = superio_enter(sio->addr);
	236	if (err)
	237	return err;
	238	superio_select(sio->addr, SIO_LD_GPIO);
	239
	240	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	241	dir = !!(dir & (1 << offset));
	242	if (dir)
	243	data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	244	else
	245	data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
	246
	247	superio_exit(sio->addr);
	248
	249	return !!(data & 1 << offset);
	250	}
	251
	252	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
	253	unsigned offset, int value)
	254	{
	255	int err;
f372d5f5	256	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	257	struct f7188x_sio *sio = bank->data->sio;
	258	u8 dir, data_out;
	259
	260	err = superio_enter(sio->addr);
	261	if (err)
	262	return err;
	263	superio_select(sio->addr, SIO_LD_GPIO);
	264
	265	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	266	if (value)
	267	data_out \|= (1 << offset);
	268	else
	269	data_out &= ~(1 << offset);
	270	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
	271
	272	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	273	dir \|= (1 << offset);
	274	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
	275
	276	superio_exit(sio->addr);
	277
	278	return 0;
	279	}
	280
	281	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	282	{
	283	int err;
f372d5f5	284	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	285	struct f7188x_sio *sio = bank->data->sio;
	286	u8 data_out;
	287
	288	err = superio_enter(sio->addr);
	289	if (err)
	290	return;
	291	superio_select(sio->addr, SIO_LD_GPIO);
	292
	293	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	294	if (value)
	295	data_out \|= (1 << offset);
	296	else
	297	data_out &= ~(1 << offset);
	298	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
	299
	300	superio_exit(sio->addr);
	301	}
	302
	303	/*
	304	* Platform device and driver.
	305	*/
	306
	307	static int f7188x_gpio_probe(struct platform_device *pdev)
	308	{
	309	int err;
	310	int i;
ab128afc	311	struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
6c17aa01 SG	312	struct f7188x_gpio_data *data;
	313
	314	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	315	if (!data)
	316	return -ENOMEM;
	317
	318	switch (sio->type) {
24ccef35 AB	319	case f71869:
	320	data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
	321	data->bank = f71869_gpio_bank;
	322	break;
7e960363 AB	323	case f71869a:
	324	data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
	325	data->bank = f71869a_gpio_bank;
	326	break;
6c17aa01 SG	327	case f71882fg:
	328	data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
	329	data->bank = f71882_gpio_bank;
	330	break;
	331	case f71889f:
	332	data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
	333	data->bank = f71889_gpio_bank;
	334	break;
1920906f PH	335	case f81866:
	336	data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
	337	data->bank = f81866_gpio_bank;
	338	break;
6c17aa01 SG	339	default:
	340	return -ENODEV;
	341	}
	342	data->sio = sio;
	343
	344	platform_set_drvdata(pdev, data);
	345
	346	/* For each GPIO bank, register a GPIO chip. */
	347	for (i = 0; i < data->nr_bank; i++) {
	348	struct f7188x_gpio_bank *bank = &data->bank[i];
	349
58383c78	350	bank->chip.parent = &pdev->dev;
6c17aa01 SG	351	bank->data = data;
6c17aa01 SG	352
330f4e56	353	err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
6c17aa01 SG	354	if (err) {
	355	dev_err(&pdev->dev,
	356	"Failed to register gpiochip %d: %d\n",
	357	i, err);
330f4e56	358	return err;
6c17aa01 SG	359	}
	360	}
	361
6c17aa01 SG	362	return 0;
	363	}
	364
	365	static int __init f7188x_find(int addr, struct f7188x_sio *sio)
	366	{
	367	int err;
	368	u16 devid;
	369
	370	err = superio_enter(addr);
	371	if (err)
	372	return err;
	373
	374	err = -ENODEV;
	375	devid = superio_inw(addr, SIO_MANID);
	376	if (devid != SIO_FINTEK_ID) {
	377	pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
	378	goto err;
	379	}
	380
	381	devid = superio_inw(addr, SIO_DEVID);
	382	switch (devid) {
24ccef35 AB	383	case SIO_F71869_ID:
	384	sio->type = f71869;
	385	break;
7e960363 AB	386	case SIO_F71869A_ID:
	387	sio->type = f71869a;
	388	break;
6c17aa01 SG	389	case SIO_F71882_ID:
	390	sio->type = f71882fg;
	391	break;
	392	case SIO_F71889_ID:
	393	sio->type = f71889f;
	394	break;
1920906f PH	395	case SIO_F81866_ID:
	396	sio->type = f81866;
	397	break;
6c17aa01 SG	398	default:
	399	pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
	400	goto err;
	401	}
	402	sio->addr = addr;
	403	err = 0;
	404
	405	pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
	406	f7188x_names[sio->type],
	407	(unsigned int) addr,
	408	(int) superio_inb(addr, SIO_DEVREV));
	409
	410	err:
	411	superio_exit(addr);
	412	return err;
	413	}
	414
	415	static struct platform_device *f7188x_gpio_pdev;
	416
	417	static int __init
	418	f7188x_gpio_device_add(const struct f7188x_sio *sio)
	419	{
	420	int err;
	421
	422	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	423	if (!f7188x_gpio_pdev)
	424	return -ENOMEM;
	425
	426	err = platform_device_add_data(f7188x_gpio_pdev,
	427	sio, sizeof(*sio));
	428	if (err) {
	429	pr_err(DRVNAME "Platform data allocation failed\n");
	430	goto err;
	431	}
	432
	433	err = platform_device_add(f7188x_gpio_pdev);
	434	if (err) {
	435	pr_err(DRVNAME "Device addition failed\n");
	436	goto err;
	437	}
	438
	439	return 0;
	440
	441	err:
	442	platform_device_put(f7188x_gpio_pdev);
	443
	444	return err;
	445	}
	446
	447	/*
3f8f4f19	448	* Try to match a supported Fintek device by reading the (hard-wired)
6c17aa01 SG	449	* configuration I/O ports. If available, then register both the platform
	450	* device and driver to support the GPIOs.
	451	*/
	452
	453	static struct platform_driver f7188x_gpio_driver = {
	454	.driver = {
6c17aa01 SG	455	.name = DRVNAME,
	456	},
	457	.probe = f7188x_gpio_probe,
6c17aa01 SG	458	};
	459
	460	static int __init f7188x_gpio_init(void)
	461	{
	462	int err;
	463	struct f7188x_sio sio;
	464
	465	if (f7188x_find(0x2e, &sio) &&
	466	f7188x_find(0x4e, &sio))
	467	return -ENODEV;
	468
	469	err = platform_driver_register(&f7188x_gpio_driver);
	470	if (!err) {
	471	err = f7188x_gpio_device_add(&sio);
	472	if (err)
	473	platform_driver_unregister(&f7188x_gpio_driver);
	474	}
	475
	476	return err;
	477	}
	478	subsys_initcall(f7188x_gpio_init);
	479
	480	static void __exit f7188x_gpio_exit(void)
	481	{
	482	platform_device_unregister(f7188x_gpio_pdev);
	483	platform_driver_unregister(&f7188x_gpio_driver);
	484	}
	485	module_exit(f7188x_gpio_exit);
	486
1920906f	487	MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889F and F81866");
6c17aa01 SG	488	MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
6c17aa01 SG	489	MODULE_LICENSE("GPL");