[linux-2.6-block.git] / drivers / gpio / gpio-adnp.c

/*
 * Copyright (C) 2011-2012 Avionic Design GmbH
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/gpio/driver.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/seq_file.h>
#include <linux/slab.h>

#define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
#define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
#define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
#define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
#define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)

struct adnp {
	struct i2c_client *client;
	struct gpio_chip gpio;
	unsigned int reg_shift;

	struct mutex i2c_lock;
	struct mutex irq_lock;

	u8 *irq_enable;
	u8 *irq_level;
	u8 *irq_rise;
	u8 *irq_fall;
	u8 *irq_high;
	u8 *irq_low;
};

static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
{
	int err;

	err = i2c_smbus_read_byte_data(adnp->client, offset);
	if (err < 0) {
		dev_err(adnp->gpio.parent, "%s failed: %d\n",
			"i2c_smbus_read_byte_data()", err);
		return err;
	}

	*value = err;
	return 0;
}

static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
{
	int err;

	err = i2c_smbus_write_byte_data(adnp->client, offset, value);
	if (err < 0) {
		dev_err(adnp->gpio.parent, "%s failed: %d\n",
			"i2c_smbus_write_byte_data()", err);
		return err;
	}

	return 0;
}

static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct adnp *adnp = gpiochip_get_data(chip);
	unsigned int reg = offset >> adnp->reg_shift;
	unsigned int pos = offset & 7;
	u8 value;
	int err;

	err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
	if (err < 0)
		return err;

	return (value & BIT(pos)) ? 1 : 0;
}

static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
{
	unsigned int reg = offset >> adnp->reg_shift;
	unsigned int pos = offset & 7;
	int err;
	u8 val;

	err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
	if (err < 0)
		return;

	if (value)
		val |= BIT(pos);
	else
		val &= ~BIT(pos);

	adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
}

static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct adnp *adnp = gpiochip_get_data(chip);

	mutex_lock(&adnp->i2c_lock);
	__adnp_gpio_set(adnp, offset, value);
	mutex_unlock(&adnp->i2c_lock);
}

static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct adnp *adnp = gpiochip_get_data(chip);
	unsigned int reg = offset >> adnp->reg_shift;
	unsigned int pos = offset & 7;
	u8 value;
	int err;

	mutex_lock(&adnp->i2c_lock);

	err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
	if (err < 0)
		goto out;

	value &= ~BIT(pos);

	err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
	if (err < 0)
		goto out;

	err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
	if (err < 0)
		goto out;

	if (err & BIT(pos))
		err = -EACCES;

	err = 0;

out:
	mutex_unlock(&adnp->i2c_lock);
	return err;
}

static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	struct adnp *adnp = gpiochip_get_data(chip);
	unsigned int reg = offset >> adnp->reg_shift;
	unsigned int pos = offset & 7;
	int err;
	u8 val;

	mutex_lock(&adnp->i2c_lock);

	err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
	if (err < 0)
		goto out;

	val |= BIT(pos);

	err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
	if (err < 0)
		goto out;

	err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
	if (err < 0)
		goto out;

	if (!(val & BIT(pos))) {
		err = -EPERM;
		goto out;
	}

	__adnp_gpio_set(adnp, offset, value);
	err = 0;

out:
	mutex_unlock(&adnp->i2c_lock);
	return err;
}

static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	struct adnp *adnp = gpiochip_get_data(chip);
	unsigned int num_regs = 1 << adnp->reg_shift, i, j;
	int err;

	for (i = 0; i < num_regs; i++) {
		u8 ddr, plr, ier, isr;

		mutex_lock(&adnp->i2c_lock);

		err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
		if (err < 0) {
			mutex_unlock(&adnp->i2c_lock);
			return;
		}

		err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
		if (err < 0) {
			mutex_unlock(&adnp->i2c_lock);
			return;
		}

		err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
		if (err < 0) {
			mutex_unlock(&adnp->i2c_lock);
			return;
		}

		err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
		if (err < 0) {
			mutex_unlock(&adnp->i2c_lock);
			return;
		}

		mutex_unlock(&adnp->i2c_lock);

		for (j = 0; j < 8; j++) {
			unsigned int bit = (i << adnp->reg_shift) + j;
			const char *direction = "input ";
			const char *level = "low ";
			const char *interrupt = "disabled";
			const char *pending = "";

			if (ddr & BIT(j))
				direction = "output";

			if (plr & BIT(j))
				level = "high";

			if (ier & BIT(j))
				interrupt = "enabled ";

			if (isr & BIT(j))
				pending = "pending";

			seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
				   direction, level, interrupt, pending);
		}
	}
}

static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
{
	struct gpio_chip *chip = &adnp->gpio;
	int err;

	adnp->reg_shift = get_count_order(num_gpios) - 3;

	chip->direction_input = adnp_gpio_direction_input;
	chip->direction_output = adnp_gpio_direction_output;
	chip->get = adnp_gpio_get;
	chip->set = adnp_gpio_set;
	chip->can_sleep = true;

	if (IS_ENABLED(CONFIG_DEBUG_FS))
		chip->dbg_show = adnp_gpio_dbg_show;

	chip->base = -1;
	chip->ngpio = num_gpios;
	chip->label = adnp->client->name;
	chip->parent = &adnp->client->dev;
	chip->of_node = chip->parent->of_node;
	chip->owner = THIS_MODULE;

	err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
	if (err)
		return err;

	return 0;
}

static irqreturn_t adnp_irq(int irq, void *data)
{
	struct adnp *adnp = data;
	unsigned int num_regs, i;

	num_regs = 1 << adnp->reg_shift;

	for (i = 0; i < num_regs; i++) {
		unsigned int base = i << adnp->reg_shift, bit;
		u8 changed, level, isr, ier;
		unsigned long pending;
		int err;

		mutex_lock(&adnp->i2c_lock);

		err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
		if (err < 0) {
			mutex_unlock(&adnp->i2c_lock);
			continue;
		}

		err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
		if (err < 0) {
			mutex_unlock(&adnp->i2c_lock);
			continue;
		}

		err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
		if (err < 0) {
			mutex_unlock(&adnp->i2c_lock);
			continue;
		}

		mutex_unlock(&adnp->i2c_lock);

		/* determine pins that changed levels */
		changed = level ^ adnp->irq_level[i];

		/* compute edge-triggered interrupts */
		pending = changed & ((adnp->irq_fall[i] & ~level) |
				     (adnp->irq_rise[i] & level));

		/* add in level-triggered interrupts */
		pending |= (adnp->irq_high[i] & level) |
			   (adnp->irq_low[i] & ~level);

		/* mask out non-pending and disabled interrupts */
		pending &= isr & ier;

		for_each_set_bit(bit, &pending, 8) {
			unsigned int child_irq;
			child_irq = irq_find_mapping(adnp->gpio.irqdomain,
						     base + bit);
			handle_nested_irq(child_irq);
		}
	}

	return IRQ_HANDLED;
}

static void adnp_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct adnp *adnp = gpiochip_get_data(gc);
	unsigned int reg = d->hwirq >> adnp->reg_shift;
	unsigned int pos = d->hwirq & 7;

	adnp->irq_enable[reg] &= ~BIT(pos);
}

static void adnp_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct adnp *adnp = gpiochip_get_data(gc);
	unsigned int reg = d->hwirq >> adnp->reg_shift;
	unsigned int pos = d->hwirq & 7;

	adnp->irq_enable[reg] |= BIT(pos);
}

static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct adnp *adnp = gpiochip_get_data(gc);
	unsigned int reg = d->hwirq >> adnp->reg_shift;
	unsigned int pos = d->hwirq & 7;

	if (type & IRQ_TYPE_EDGE_RISING)
		adnp->irq_rise[reg] |= BIT(pos);
	else
		adnp->irq_rise[reg] &= ~BIT(pos);

	if (type & IRQ_TYPE_EDGE_FALLING)
		adnp->irq_fall[reg] |= BIT(pos);
	else
		adnp->irq_fall[reg] &= ~BIT(pos);

	if (type & IRQ_TYPE_LEVEL_HIGH)
		adnp->irq_high[reg] |= BIT(pos);
	else
		adnp->irq_high[reg] &= ~BIT(pos);

	if (type & IRQ_TYPE_LEVEL_LOW)
		adnp->irq_low[reg] |= BIT(pos);
	else
		adnp->irq_low[reg] &= ~BIT(pos);

	return 0;
}

static void adnp_irq_bus_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct adnp *adnp = gpiochip_get_data(gc);

	mutex_lock(&adnp->irq_lock);
}

static void adnp_irq_bus_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct adnp *adnp = gpiochip_get_data(gc);
	unsigned int num_regs = 1 << adnp->reg_shift, i;

	mutex_lock(&adnp->i2c_lock);

	for (i = 0; i < num_regs; i++)
		adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);

	mutex_unlock(&adnp->i2c_lock);
	mutex_unlock(&adnp->irq_lock);
}

static struct irq_chip adnp_irq_chip = {
	.name = "gpio-adnp",
	.irq_mask = adnp_irq_mask,
	.irq_unmask = adnp_irq_unmask,
	.irq_set_type = adnp_irq_set_type,
	.irq_bus_lock = adnp_irq_bus_lock,
	.irq_bus_sync_unlock = adnp_irq_bus_unlock,
};

static int adnp_irq_setup(struct adnp *adnp)
{
	unsigned int num_regs = 1 << adnp->reg_shift, i;
	struct gpio_chip *chip = &adnp->gpio;
	int err;

	mutex_init(&adnp->irq_lock);

	/*
	 * Allocate memory to keep track of the current level and trigger
	 * modes of the interrupts. To avoid multiple allocations, a single
	 * large buffer is allocated and pointers are setup to point at the
	 * corresponding offsets. For consistency, the layout of the buffer
	 * is chosen to match the register layout of the hardware in that
	 * each segment contains the corresponding bits for all interrupts.
	 */
	adnp->irq_enable = devm_kzalloc(chip->parent, num_regs * 6,
					GFP_KERNEL);
	if (!adnp->irq_enable)
		return -ENOMEM;

	adnp->irq_level = adnp->irq_enable + (num_regs * 1);
	adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
	adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
	adnp->irq_high = adnp->irq_enable + (num_regs * 4);
	adnp->irq_low = adnp->irq_enable + (num_regs * 5);

	for (i = 0; i < num_regs; i++) {
		/*
		 * Read the initial level of all pins to allow the emulation
		 * of edge triggered interrupts.
		 */
		err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
		if (err < 0)
			return err;

		/* disable all interrupts */
		err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
		if (err < 0)
			return err;

		adnp->irq_enable[i] = 0x00;
	}

	err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
					NULL, adnp_irq,
					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
					dev_name(chip->parent), adnp);
	if (err != 0) {
		dev_err(chip->parent, "can't request IRQ#%d: %d\n",
			adnp->client->irq, err);
		return err;
	}

	err = gpiochip_irqchip_add(chip,
				   &adnp_irq_chip,
				   0,
				   handle_simple_irq,
				   IRQ_TYPE_NONE);
	if (err) {
		dev_err(chip->parent,
			"could not connect irqchip to gpiochip\n");
		return err;
	}

	return 0;
}

static int adnp_i2c_probe(struct i2c_client *client,
				    const struct i2c_device_id *id)
{
	struct device_node *np = client->dev.of_node;
	struct adnp *adnp;
	u32 num_gpios;
	int err;

	err = of_property_read_u32(np, "nr-gpios", &num_gpios);
	if (err < 0)
		return err;

	client->irq = irq_of_parse_and_map(np, 0);
	if (!client->irq)
		return -EPROBE_DEFER;

	adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
	if (!adnp)
		return -ENOMEM;

	mutex_init(&adnp->i2c_lock);
	adnp->client = client;

	err = adnp_gpio_setup(adnp, num_gpios);
	if (err)
		return err;

	if (of_find_property(np, "interrupt-controller", NULL)) {
		err = adnp_irq_setup(adnp);
		if (err)
			return err;
	}

	i2c_set_clientdata(client, adnp);

	return 0;
}

static const struct i2c_device_id adnp_i2c_id[] = {
	{ "gpio-adnp" },
	{ },
};
MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);

static const struct of_device_id adnp_of_match[] = {
	{ .compatible = "ad,gpio-adnp", },
	{ },
};
MODULE_DEVICE_TABLE(of, adnp_of_match);

static struct i2c_driver adnp_i2c_driver = {
	.driver = {
		.name = "gpio-adnp",
		.of_match_table = adnp_of_match,
	},
	.probe = adnp_i2c_probe,
	.id_table = adnp_i2c_id,
};
module_i2c_driver(adnp_i2c_driver);

MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
MODULE_LICENSE("GPL");
Commit	Line	Data
5e969a40 TR	1	/*
	2	* Copyright (C) 2011-2012 Avionic Design GmbH
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
0752e169	9	#include <linux/gpio/driver.h>
5e969a40 TR	10	#include <linux/i2c.h>
5e969a40 TR	11	#include <linux/interrupt.h>
5e969a40 TR	12	#include <linux/module.h>
	13	#include <linux/of_irq.h>
	14	#include <linux/seq_file.h>
	15	#include <linux/slab.h>
	16
	17	#define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
	18	#define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
	19	#define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
	20	#define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
	21	#define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
	22
	23	struct adnp {
	24	struct i2c_client *client;
	25	struct gpio_chip gpio;
	26	unsigned int reg_shift;
	27
	28	struct mutex i2c_lock;
5e969a40 TR	29	struct mutex irq_lock;
	30
	31	u8 *irq_enable;
	32	u8 *irq_level;
	33	u8 *irq_rise;
	34	u8 *irq_fall;
	35	u8 *irq_high;
	36	u8 *irq_low;
	37	};
	38
5e969a40 TR	39	static int adnp_read(struct adnp adnp, unsigned offset, uint8_t value)
	40	{
	41	int err;
	42
	43	err = i2c_smbus_read_byte_data(adnp->client, offset);
	44	if (err < 0) {
58383c78	45	dev_err(adnp->gpio.parent, "%s failed: %d\n",
5e969a40 TR	46	"i2c_smbus_read_byte_data()", err);
	47	return err;
	48	}
	49
	50	*value = err;
	51	return 0;
	52	}
	53
	54	static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
	55	{
	56	int err;
	57
	58	err = i2c_smbus_write_byte_data(adnp->client, offset, value);
	59	if (err < 0) {
58383c78	60	dev_err(adnp->gpio.parent, "%s failed: %d\n",
5e969a40 TR	61	"i2c_smbus_write_byte_data()", err);
	62	return err;
	63	}
	64
	65	return 0;
	66	}
	67
	68	static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
	69	{
1e69c4fe	70	struct adnp *adnp = gpiochip_get_data(chip);
5e969a40 TR	71	unsigned int reg = offset >> adnp->reg_shift;
	72	unsigned int pos = offset & 7;
	73	u8 value;
	74	int err;
	75
	76	err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
	77	if (err < 0)
	78	return err;
	79
	80	return (value & BIT(pos)) ? 1 : 0;
	81	}
	82
	83	static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
	84	{
	85	unsigned int reg = offset >> adnp->reg_shift;
	86	unsigned int pos = offset & 7;
	87	int err;
	88	u8 val;
	89
	90	err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
	91	if (err < 0)
	92	return;
	93
	94	if (value)
	95	val \|= BIT(pos);
	96	else
	97	val &= ~BIT(pos);
	98
	99	adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
	100	}
	101
	102	static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	103	{
1e69c4fe	104	struct adnp *adnp = gpiochip_get_data(chip);
5e969a40 TR	105
	106	mutex_lock(&adnp->i2c_lock);
	107	__adnp_gpio_set(adnp, offset, value);
	108	mutex_unlock(&adnp->i2c_lock);
	109	}
	110
	111	static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	112	{
1e69c4fe	113	struct adnp *adnp = gpiochip_get_data(chip);
5e969a40 TR	114	unsigned int reg = offset >> adnp->reg_shift;
	115	unsigned int pos = offset & 7;
	116	u8 value;
	117	int err;
	118
	119	mutex_lock(&adnp->i2c_lock);
	120
	121	err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
	122	if (err < 0)
	123	goto out;
	124
	125	value &= ~BIT(pos);
	126
	127	err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
	128	if (err < 0)
	129	goto out;
	130
	131	err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
	132	if (err < 0)
	133	goto out;
	134
	135	if (err & BIT(pos))
	136	err = -EACCES;
	137
	138	err = 0;
	139
	140	out:
	141	mutex_unlock(&adnp->i2c_lock);
	142	return err;
	143	}
	144
	145	static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	146	int value)
	147	{
1e69c4fe	148	struct adnp *adnp = gpiochip_get_data(chip);
5e969a40 TR	149	unsigned int reg = offset >> adnp->reg_shift;
	150	unsigned int pos = offset & 7;
	151	int err;
	152	u8 val;
	153
	154	mutex_lock(&adnp->i2c_lock);
	155
	156	err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
	157	if (err < 0)
	158	goto out;
	159
	160	val \|= BIT(pos);
	161
	162	err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
	163	if (err < 0)
	164	goto out;
	165
	166	err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
	167	if (err < 0)
	168	goto out;
	169
	170	if (!(val & BIT(pos))) {
	171	err = -EPERM;
	172	goto out;
	173	}
	174
	175	__adnp_gpio_set(adnp, offset, value);
	176	err = 0;
	177
	178	out:
	179	mutex_unlock(&adnp->i2c_lock);
	180	return err;
	181	}
	182
	183	static void adnp_gpio_dbg_show(struct seq_file s, struct gpio_chip chip)
	184	{
1e69c4fe	185	struct adnp *adnp = gpiochip_get_data(chip);
5e969a40 TR	186	unsigned int num_regs = 1 << adnp->reg_shift, i, j;
	187	int err;
	188
	189	for (i = 0; i < num_regs; i++) {
	190	u8 ddr, plr, ier, isr;
	191
	192	mutex_lock(&adnp->i2c_lock);
	193
	194	err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
	195	if (err < 0) {
	196	mutex_unlock(&adnp->i2c_lock);
	197	return;
	198	}
	199
	200	err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
	201	if (err < 0) {
	202	mutex_unlock(&adnp->i2c_lock);
	203	return;
	204	}
	205
	206	err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
	207	if (err < 0) {
	208	mutex_unlock(&adnp->i2c_lock);
	209	return;
	210	}
	211
	212	err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
	213	if (err < 0) {
	214	mutex_unlock(&adnp->i2c_lock);
	215	return;
	216	}
	217
	218	mutex_unlock(&adnp->i2c_lock);
	219
	220	for (j = 0; j < 8; j++) {
	221	unsigned int bit = (i << adnp->reg_shift) + j;
	222	const char *direction = "input ";
	223	const char *level = "low ";
	224	const char *interrupt = "disabled";
	225	const char *pending = "";
	226
	227	if (ddr & BIT(j))
	228	direction = "output";
	229
	230	if (plr & BIT(j))
	231	level = "high";
	232
	233	if (ier & BIT(j))
	234	interrupt = "enabled ";
	235
	236	if (isr & BIT(j))
	237	pending = "pending";
	238
	239	seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
	240	direction, level, interrupt, pending);
	241	}
	242	}
	243	}
	244
	245	static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
	246	{
	247	struct gpio_chip *chip = &adnp->gpio;
0752e169	248	int err;
5e969a40 TR	249
	250	adnp->reg_shift = get_count_order(num_gpios) - 3;
	251
	252	chip->direction_input = adnp_gpio_direction_input;
	253	chip->direction_output = adnp_gpio_direction_output;
	254	chip->get = adnp_gpio_get;
	255	chip->set = adnp_gpio_set;
9fb1f39e	256	chip->can_sleep = true;
5e969a40 TR	257
	258	if (IS_ENABLED(CONFIG_DEBUG_FS))
	259	chip->dbg_show = adnp_gpio_dbg_show;
	260
	261	chip->base = -1;
	262	chip->ngpio = num_gpios;
	263	chip->label = adnp->client->name;
58383c78 LW	264	chip->parent = &adnp->client->dev;
58383c78 LW	265	chip->of_node = chip->parent->of_node;
5e969a40 TR	266	chip->owner = THIS_MODULE;
5e969a40 TR	267
daa994bf	268	err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
0752e169 LW	269	if (err)
	270	return err;
	271
5e969a40 TR	272	return 0;
	273	}
	274
	275	static irqreturn_t adnp_irq(int irq, void *data)
	276	{
	277	struct adnp *adnp = data;
	278	unsigned int num_regs, i;
	279
	280	num_regs = 1 << adnp->reg_shift;
	281
	282	for (i = 0; i < num_regs; i++) {
	283	unsigned int base = i << adnp->reg_shift, bit;
	284	u8 changed, level, isr, ier;
	285	unsigned long pending;
	286	int err;
	287
	288	mutex_lock(&adnp->i2c_lock);
	289
	290	err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
	291	if (err < 0) {
	292	mutex_unlock(&adnp->i2c_lock);
	293	continue;
	294	}
	295
	296	err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
	297	if (err < 0) {
	298	mutex_unlock(&adnp->i2c_lock);
	299	continue;
	300	}
	301
	302	err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
	303	if (err < 0) {
	304	mutex_unlock(&adnp->i2c_lock);
	305	continue;
	306	}
	307
	308	mutex_unlock(&adnp->i2c_lock);
	309
	310	/* determine pins that changed levels */
	311	changed = level ^ adnp->irq_level[i];
	312
	313	/* compute edge-triggered interrupts */
	314	pending = changed & ((adnp->irq_fall[i] & ~level) \|
	315	(adnp->irq_rise[i] & level));
	316
	317	/* add in level-triggered interrupts */
	318	pending \|= (adnp->irq_high[i] & level) \|
	319	(adnp->irq_low[i] & ~level);
	320
	321	/* mask out non-pending and disabled interrupts */
	322	pending &= isr & ier;
	323
	324	for_each_set_bit(bit, &pending, 8) {
472f95b9	325	unsigned int child_irq;
0752e169 LW	326	child_irq = irq_find_mapping(adnp->gpio.irqdomain,
0752e169 LW	327	base + bit);
472f95b9	328	handle_nested_irq(child_irq);
5e969a40 TR	329	}
	330	}
	331
	332	return IRQ_HANDLED;
	333	}
	334
0752e169	335	static void adnp_irq_mask(struct irq_data *d)
5e969a40	336	{
0752e169	337	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1e69c4fe	338	struct adnp *adnp = gpiochip_get_data(gc);
0752e169 LW	339	unsigned int reg = d->hwirq >> adnp->reg_shift;
0752e169 LW	340	unsigned int pos = d->hwirq & 7;
5e969a40 TR	341
	342	adnp->irq_enable[reg] &= ~BIT(pos);
	343	}
	344
0752e169	345	static void adnp_irq_unmask(struct irq_data *d)
5e969a40	346	{
0752e169	347	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1e69c4fe	348	struct adnp *adnp = gpiochip_get_data(gc);
0752e169 LW	349	unsigned int reg = d->hwirq >> adnp->reg_shift;
0752e169 LW	350	unsigned int pos = d->hwirq & 7;
5e969a40 TR	351
	352	adnp->irq_enable[reg] \|= BIT(pos);
	353	}
	354
0752e169	355	static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
5e969a40	356	{
0752e169	357	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1e69c4fe	358	struct adnp *adnp = gpiochip_get_data(gc);
0752e169 LW	359	unsigned int reg = d->hwirq >> adnp->reg_shift;
0752e169 LW	360	unsigned int pos = d->hwirq & 7;
5e969a40 TR	361
	362	if (type & IRQ_TYPE_EDGE_RISING)
	363	adnp->irq_rise[reg] \|= BIT(pos);
	364	else
	365	adnp->irq_rise[reg] &= ~BIT(pos);
	366
	367	if (type & IRQ_TYPE_EDGE_FALLING)
	368	adnp->irq_fall[reg] \|= BIT(pos);
	369	else
	370	adnp->irq_fall[reg] &= ~BIT(pos);
	371
	372	if (type & IRQ_TYPE_LEVEL_HIGH)
	373	adnp->irq_high[reg] \|= BIT(pos);
	374	else
	375	adnp->irq_high[reg] &= ~BIT(pos);
	376
	377	if (type & IRQ_TYPE_LEVEL_LOW)
	378	adnp->irq_low[reg] \|= BIT(pos);
	379	else
	380	adnp->irq_low[reg] &= ~BIT(pos);
	381
	382	return 0;
	383	}
	384
0752e169	385	static void adnp_irq_bus_lock(struct irq_data *d)
5e969a40	386	{
0752e169	387	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1e69c4fe	388	struct adnp *adnp = gpiochip_get_data(gc);
5e969a40 TR	389
	390	mutex_lock(&adnp->irq_lock);
	391	}
	392
0752e169	393	static void adnp_irq_bus_unlock(struct irq_data *d)
5e969a40	394	{
0752e169	395	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1e69c4fe	396	struct adnp *adnp = gpiochip_get_data(gc);
5e969a40 TR	397	unsigned int num_regs = 1 << adnp->reg_shift, i;
	398
	399	mutex_lock(&adnp->i2c_lock);
	400
	401	for (i = 0; i < num_regs; i++)
	402	adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
	403
	404	mutex_unlock(&adnp->i2c_lock);
	405	mutex_unlock(&adnp->irq_lock);
	406	}
	407
	408	static struct irq_chip adnp_irq_chip = {
	409	.name = "gpio-adnp",
	410	.irq_mask = adnp_irq_mask,
	411	.irq_unmask = adnp_irq_unmask,
	412	.irq_set_type = adnp_irq_set_type,
	413	.irq_bus_lock = adnp_irq_bus_lock,
	414	.irq_bus_sync_unlock = adnp_irq_bus_unlock,
5e969a40 TR	415	};
	416
	417	static int adnp_irq_setup(struct adnp *adnp)
	418	{
	419	unsigned int num_regs = 1 << adnp->reg_shift, i;
	420	struct gpio_chip *chip = &adnp->gpio;
	421	int err;
	422
	423	mutex_init(&adnp->irq_lock);
	424
	425	/*
	426	* Allocate memory to keep track of the current level and trigger
	427	* modes of the interrupts. To avoid multiple allocations, a single
	428	* large buffer is allocated and pointers are setup to point at the
	429	* corresponding offsets. For consistency, the layout of the buffer
	430	* is chosen to match the register layout of the hardware in that
	431	* each segment contains the corresponding bits for all interrupts.
	432	*/
58383c78 LW	433	adnp->irq_enable = devm_kzalloc(chip->parent, num_regs * 6,
58383c78 LW	434	GFP_KERNEL);
5e969a40 TR	435	if (!adnp->irq_enable)
	436	return -ENOMEM;
	437
	438	adnp->irq_level = adnp->irq_enable + (num_regs * 1);
	439	adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
	440	adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
	441	adnp->irq_high = adnp->irq_enable + (num_regs * 4);
	442	adnp->irq_low = adnp->irq_enable + (num_regs * 5);
	443
	444	for (i = 0; i < num_regs; i++) {
	445	/*
	446	* Read the initial level of all pins to allow the emulation
	447	* of edge triggered interrupts.
	448	*/
	449	err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
	450	if (err < 0)
	451	return err;
	452
	453	/* disable all interrupts */
	454	err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
	455	if (err < 0)
	456	return err;
	457
	458	adnp->irq_enable[i] = 0x00;
	459	}
	460
58383c78	461	err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
0752e169 LW	462	NULL, adnp_irq,
0752e169 LW	463	IRQF_TRIGGER_RISING \| IRQF_ONESHOT,
58383c78	464	dev_name(chip->parent), adnp);
5e969a40	465	if (err != 0) {
58383c78	466	dev_err(chip->parent, "can't request IRQ#%d: %d\n",
5e969a40	467	adnp->client->irq, err);
5b21533b	468	return err;
5e969a40 TR	469	}
5e969a40 TR	470
0752e169 LW	471	err = gpiochip_irqchip_add(chip,
	472	&adnp_irq_chip,
	473	0,
	474	handle_simple_irq,
	475	IRQ_TYPE_NONE);
	476	if (err) {
58383c78	477	dev_err(chip->parent,
0752e169 LW	478	"could not connect irqchip to gpiochip\n");
0752e169 LW	479	return err;
5e969a40 TR	480	}
5e969a40 TR	481
0752e169	482	return 0;
5e969a40 TR	483	}
5e969a40 TR	484
3836309d	485	static int adnp_i2c_probe(struct i2c_client *client,
5e969a40 TR	486	const struct i2c_device_id *id)
	487	{
	488	struct device_node *np = client->dev.of_node;
	489	struct adnp *adnp;
	490	u32 num_gpios;
	491	int err;
	492
	493	err = of_property_read_u32(np, "nr-gpios", &num_gpios);
	494	if (err < 0)
	495	return err;
	496
	497	client->irq = irq_of_parse_and_map(np, 0);
	498	if (!client->irq)
	499	return -EPROBE_DEFER;
	500
	501	adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
	502	if (!adnp)
	503	return -ENOMEM;
	504
	505	mutex_init(&adnp->i2c_lock);
	506	adnp->client = client;
	507
	508	err = adnp_gpio_setup(adnp, num_gpios);
0752e169	509	if (err)
5e969a40 TR	510	return err;
	511
	512	if (of_find_property(np, "interrupt-controller", NULL)) {
	513	err = adnp_irq_setup(adnp);
0752e169 LW	514	if (err)
0752e169 LW	515	return err;
5e969a40 TR	516	}
5e969a40 TR	517
5e969a40	518	i2c_set_clientdata(client, adnp);
5e969a40	519
0752e169	520	return 0;
5e969a40 TR	521	}
5e969a40 TR	522
b5ba78de	523	static const struct i2c_device_id adnp_i2c_id[] = {
5e969a40 TR	524	{ "gpio-adnp" },
	525	{ },
	526	};
	527	MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
	528
b5ba78de	529	static const struct of_device_id adnp_of_match[] = {
5e969a40 TR	530	{ .compatible = "ad,gpio-adnp", },
	531	{ },
	532	};
	533	MODULE_DEVICE_TABLE(of, adnp_of_match);
	534
	535	static struct i2c_driver adnp_i2c_driver = {
	536	.driver = {
	537	.name = "gpio-adnp",
83924fb3	538	.of_match_table = adnp_of_match,
5e969a40 TR	539	},
5e969a40 TR	540	.probe = adnp_i2c_probe,
5e969a40 TR	541	.id_table = adnp_i2c_id,
	542	};
	543	module_i2c_driver(adnp_i2c_driver);
	544
	545	MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
	546	MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
	547	MODULE_LICENSE("GPL");