[linux-2.6-block.git] / drivers / gpio / gpio-74x164.c

/*
 *  74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
 *
 *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>
#include <linux/module.h>

#define GEN_74X164_NUMBER_GPIOS	8

struct gen_74x164_chip {
	struct gpio_chip	gpio_chip;
	struct mutex		lock;
	u32			registers;
	/*
	 * Since the registers are chained, every byte sent will make
	 * the previous byte shift to the next register in the
	 * chain. Thus, the first byte sent will end up in the last
	 * register at the end of the transfer. So, to have a logical
	 * numbering, store the bytes in reverse order.
	 */
	u8			buffer[0];
};

static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
{
	struct spi_transfer xfer = {
		.tx_buf = chip->buffer,
		.len = chip->registers,
	};

	return spi_sync_transfer(to_spi_device(chip->gpio_chip.parent),
				 &xfer, 1);
}

static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
	u8 bank = chip->registers - 1 - offset / 8;
	u8 pin = offset % 8;
	int ret;

	mutex_lock(&chip->lock);
	ret = (chip->buffer[bank] >> pin) & 0x1;
	mutex_unlock(&chip->lock);

	return ret;
}

static void gen_74x164_set_value(struct gpio_chip *gc,
		unsigned offset, int val)
{
	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
	u8 bank = chip->registers - 1 - offset / 8;
	u8 pin = offset % 8;

	mutex_lock(&chip->lock);
	if (val)
		chip->buffer[bank] |= (1 << pin);
	else
		chip->buffer[bank] &= ~(1 << pin);

	__gen_74x164_write_config(chip);
	mutex_unlock(&chip->lock);
}

static int gen_74x164_direction_output(struct gpio_chip *gc,
		unsigned offset, int val)
{
	gen_74x164_set_value(gc, offset, val);
	return 0;
}

static int gen_74x164_probe(struct spi_device *spi)
{
	struct gen_74x164_chip *chip;
	u32 nregs;
	int ret;

	/*
	 * bits_per_word cannot be configured in platform data
	 */
	spi->bits_per_word = 8;

	ret = spi_setup(spi);
	if (ret < 0)
		return ret;

	if (of_property_read_u32(spi->dev.of_node, "registers-number",
				 &nregs)) {
		dev_err(&spi->dev,
			"Missing registers-number property in the DT.\n");
		return -EINVAL;
	}

	chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	spi_set_drvdata(spi, chip);

	chip->gpio_chip.label = spi->modalias;
	chip->gpio_chip.direction_output = gen_74x164_direction_output;
	chip->gpio_chip.get = gen_74x164_get_value;
	chip->gpio_chip.set = gen_74x164_set_value;
	chip->gpio_chip.base = -1;

	chip->registers = nregs;
	chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;

	chip->gpio_chip.can_sleep = true;
	chip->gpio_chip.parent = &spi->dev;
	chip->gpio_chip.owner = THIS_MODULE;

	mutex_init(&chip->lock);

	ret = __gen_74x164_write_config(chip);
	if (ret) {
		dev_err(&spi->dev, "Failed writing: %d\n", ret);
		goto exit_destroy;
	}

	ret = gpiochip_add_data(&chip->gpio_chip, chip);
	if (!ret)
		return 0;

exit_destroy:
	mutex_destroy(&chip->lock);

	return ret;
}

static int gen_74x164_remove(struct spi_device *spi)
{
	struct gen_74x164_chip *chip = spi_get_drvdata(spi);

	gpiochip_remove(&chip->gpio_chip);
	mutex_destroy(&chip->lock);

	return 0;
}

static const struct of_device_id gen_74x164_dt_ids[] = {
	{ .compatible = "fairchild,74hc595" },
	{},
};
MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);

static struct spi_driver gen_74x164_driver = {
	.driver = {
		.name		= "74x164",
		.of_match_table	= gen_74x164_dt_ids,
	},
	.probe		= gen_74x164_probe,
	.remove		= gen_74x164_remove,
};
module_spi_driver(gen_74x164_driver);

MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ead6db08 MG	1	/*
	2	* 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
	3	*
	4	* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
	5	* Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/mutex.h>
	14	#include <linux/spi/spi.h>
ead6db08	15	#include <linux/gpio.h>
20bc4d5d	16	#include <linux/of_gpio.h>
ead6db08	17	#include <linux/slab.h>
bb207ef1	18	#include <linux/module.h>
ead6db08	19
20bc4d5d MR	20	#define GEN_74X164_NUMBER_GPIOS 8
20bc4d5d MR	21
ead6db08	22	struct gen_74x164_chip {
ead6db08 MG	23	struct gpio_chip gpio_chip;
ead6db08 MG	24	struct mutex lock;
20bc4d5d	25	u32 registers;
902e7e60 GU	26	/*
	27	* Since the registers are chained, every byte sent will make
	28	* the previous byte shift to the next register in the
	29	* chain. Thus, the first byte sent will end up in the last
	30	* register at the end of the transfer. So, to have a logical
	31	* numbering, store the bytes in reverse order.
	32	*/
410f4574	33	u8 buffer[0];
ead6db08 MG	34	};
ead6db08 MG	35
ead6db08 MG	36	static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
ead6db08 MG	37	{
902e7e60 GU	38	struct spi_transfer xfer = {
	39	.tx_buf = chip->buffer,
	40	.len = chip->registers,
	41	};
20bc4d5d	42
902e7e60 GU	43	return spi_sync_transfer(to_spi_device(chip->gpio_chip.parent),
902e7e60 GU	44	&xfer, 1);
ead6db08 MG	45	}
ead6db08 MG	46
ead6db08 MG	47	static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
ead6db08 MG	48	{
b2afc6f3	49	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
902e7e60	50	u8 bank = chip->registers - 1 - offset / 8;
20bc4d5d	51	u8 pin = offset % 8;
ead6db08 MG	52	int ret;
	53
	54	mutex_lock(&chip->lock);
20bc4d5d	55	ret = (chip->buffer[bank] >> pin) & 0x1;
ead6db08 MG	56	mutex_unlock(&chip->lock);
	57
	58	return ret;
	59	}
	60
	61	static void gen_74x164_set_value(struct gpio_chip *gc,
	62	unsigned offset, int val)
	63	{
b2afc6f3	64	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
902e7e60	65	u8 bank = chip->registers - 1 - offset / 8;
20bc4d5d	66	u8 pin = offset % 8;
ead6db08 MG	67
	68	mutex_lock(&chip->lock);
	69	if (val)
20bc4d5d	70	chip->buffer[bank] \|= (1 << pin);
ead6db08	71	else
20bc4d5d	72	chip->buffer[bank] &= ~(1 << pin);
ead6db08 MG	73
	74	__gen_74x164_write_config(chip);
	75	mutex_unlock(&chip->lock);
	76	}
	77
a3cc68c3 HS	78	static int gen_74x164_direction_output(struct gpio_chip *gc,
	79	unsigned offset, int val)
	80	{
	81	gen_74x164_set_value(gc, offset, val);
	82	return 0;
	83	}
	84
3836309d	85	static int gen_74x164_probe(struct spi_device *spi)
ead6db08 MG	86	{
ead6db08 MG	87	struct gen_74x164_chip *chip;
410f4574	88	u32 nregs;
ead6db08 MG	89	int ret;
ead6db08 MG	90
ead6db08 MG	91	/*
	92	* bits_per_word cannot be configured in platform data
	93	*/
	94	spi->bits_per_word = 8;
	95
	96	ret = spi_setup(spi);
	97	if (ret < 0)
	98	return ret;
	99
410f4574 GU	100	if (of_property_read_u32(spi->dev.of_node, "registers-number",
	101	&nregs)) {
	102	dev_err(&spi->dev,
	103	"Missing registers-number property in the DT.\n");
	104	return -EINVAL;
	105	}
	106
	107	chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL);
ead6db08 MG	108	if (!chip)
	109	return -ENOMEM;
	110
6c0cf42b	111	spi_set_drvdata(spi, chip);
ead6db08	112
a3cc68c3 HS	113	chip->gpio_chip.label = spi->modalias;
a3cc68c3 HS	114	chip->gpio_chip.direction_output = gen_74x164_direction_output;
ead6db08 MG	115	chip->gpio_chip.get = gen_74x164_get_value;
ead6db08 MG	116	chip->gpio_chip.set = gen_74x164_set_value;
61e73804	117	chip->gpio_chip.base = -1;
20bc4d5d	118
410f4574	119	chip->registers = nregs;
20bc4d5d	120	chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;
20bc4d5d	121
9fb1f39e	122	chip->gpio_chip.can_sleep = true;
58383c78	123	chip->gpio_chip.parent = &spi->dev;
ead6db08 MG	124	chip->gpio_chip.owner = THIS_MODULE;
ead6db08 MG	125
bcc0562c AS	126	mutex_init(&chip->lock);
bcc0562c AS	127
ead6db08 MG	128	ret = __gen_74x164_write_config(chip);
	129	if (ret) {
	130	dev_err(&spi->dev, "Failed writing: %d\n", ret);
	131	goto exit_destroy;
	132	}
	133
b2afc6f3	134	ret = gpiochip_add_data(&chip->gpio_chip, chip);
bcc0562c AS	135	if (!ret)
bcc0562c AS	136	return 0;
ead6db08 MG	137
ead6db08 MG	138	exit_destroy:
ead6db08	139	mutex_destroy(&chip->lock);
bcc0562c	140
ead6db08 MG	141	return ret;
	142	}
	143
206210ce	144	static int gen_74x164_remove(struct spi_device *spi)
ead6db08	145	{
bcc0562c	146	struct gen_74x164_chip *chip = spi_get_drvdata(spi);
ead6db08	147
9f5132ae	148	gpiochip_remove(&chip->gpio_chip);
9f5132ae	149	mutex_destroy(&chip->lock);
ead6db08	150
9f5132ae	151	return 0;
ead6db08 MG	152	}
ead6db08 MG	153
0a90a9fb MR	154	static const struct of_device_id gen_74x164_dt_ids[] = {
	155	{ .compatible = "fairchild,74hc595" },
	156	{},
	157	};
	158	MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);
	159
ead6db08 MG	160	static struct spi_driver gen_74x164_driver = {
ead6db08 MG	161	.driver = {
a3cc68c3	162	.name = "74x164",
187a53a5	163	.of_match_table = gen_74x164_dt_ids,
ead6db08 MG	164	},
ead6db08 MG	165	.probe = gen_74x164_probe,
8283c4ff	166	.remove = gen_74x164_remove,
ead6db08	167	};
ab3b8782	168	module_spi_driver(gen_74x164_driver);
ead6db08 MG	169
	170	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	171	MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
	172	MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
	173	MODULE_LICENSE("GPL v2");