Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
[linux-2.6-block.git] / drivers / firmware / qcom_scm.c
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9626b699 1/* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
2ce76a6a 2 * Copyright (C) 2015 Linaro Ltd.
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3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
16 * 02110-1301, USA.
17 */
18
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19#include <linux/cpumask.h>
20#include <linux/export.h>
21#include <linux/types.h>
916f743d 22#include <linux/qcom_scm.h>
2a1eb58a 23
b6a1dfbc 24#include "qcom_scm.h"
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25
26/**
27 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
28 * @entry: Entry point function for the cpus
29 * @cpus: The cpumask of cpus that will use the entry point
30 *
31 * Set the cold boot address of the cpus. Any cpu outside the supported
32 * range would be removed from the cpu present mask.
33 */
34int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
35{
b6a1dfbc 36 return __qcom_scm_set_cold_boot_addr(entry, cpus);
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37}
38EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
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39
40/**
41 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
42 * @entry: Entry point function for the cpus
43 * @cpus: The cpumask of cpus that will use the entry point
44 *
45 * Set the Linux entry point for the SCM to transfer control to when coming
46 * out of a power down. CPU power down may be executed on cpuidle or hotplug.
47 */
48int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
49{
b6a1dfbc 50 return __qcom_scm_set_warm_boot_addr(entry, cpus);
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51}
52EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
767b0235 53
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54/**
55 * qcom_scm_cpu_power_down() - Power down the cpu
56 * @flags - Flags to flush cache
57 *
58 * This is an end point to power down cpu. If there was a pending interrupt,
59 * the control would return from this function, otherwise, the cpu jumps to the
60 * warm boot entry point set for this cpu upon reset.
61 */
62void qcom_scm_cpu_power_down(u32 flags)
63{
b6a1dfbc 64 __qcom_scm_cpu_power_down(flags);
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65}
66EXPORT_SYMBOL(qcom_scm_cpu_power_down);
9626b699 67
68/**
69 * qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
70 *
71 * Return true if HDCP is supported, false if not.
72 */
73bool qcom_scm_hdcp_available(void)
74{
75 int ret;
76
77 ret = __qcom_scm_is_call_available(QCOM_SCM_SVC_HDCP,
78 QCOM_SCM_CMD_HDCP);
79
80 return (ret > 0) ? true : false;
81}
82EXPORT_SYMBOL(qcom_scm_hdcp_available);
83
84/**
85 * qcom_scm_hdcp_req() - Send HDCP request.
86 * @req: HDCP request array
87 * @req_cnt: HDCP request array count
88 * @resp: response buffer passed to SCM
89 *
90 * Write HDCP register(s) through SCM.
91 */
92int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
93{
94 return __qcom_scm_hdcp_req(req, req_cnt, resp);
95}
96EXPORT_SYMBOL(qcom_scm_hdcp_req);