[linux-2.6-block.git] / drivers / edac / r82600_edac.c

/*
 * Radisys 82600 Embedded chipset Memory Controller kernel module
 * (C) 2005 EADS Astrium
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
 * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
 *
 * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 * Written with reference to 82600 High Integration Dual PCI System
 * Controller Data Book:
 * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
 * references to this document given in []
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_core.h"

#define R82600_REVISION	" Ver: 2.0.2"
#define EDAC_MOD_STR	"r82600_edac"

#define r82600_printk(level, fmt, arg...) \
	edac_printk(level, "r82600", fmt, ##arg)

#define r82600_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)

/* Radisys say "The 82600 integrates a main memory SDRAM controller that
 * supports up to four banks of memory. The four banks can support a mix of
 * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
 * each of which can be any size from 16MB to 512MB. Both registered (control
 * signals buffered) and unbuffered DIMM types are supported. Mixing of
 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
 * is not allowed. The 82600 SDRAM interface operates at the same frequency as
 * the CPU bus, 66MHz, 100MHz or 133MHz."
 */

#define R82600_NR_CSROWS 4
#define R82600_NR_CHANS  1
#define R82600_NR_DIMMS  4

#define R82600_BRIDGE_ID  0x8200

/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
#define R82600_DRAMC	0x57	/* Various SDRAM related control bits
				 * all bits are R/W
				 *
				 * 7    SDRAM ISA Hole Enable
				 * 6    Flash Page Mode Enable
				 * 5    ECC Enable: 1=ECC 0=noECC
				 * 4    DRAM DIMM Type: 1=
				 * 3    BIOS Alias Disable
				 * 2    SDRAM BIOS Flash Write Enable
				 * 1:0  SDRAM Refresh Rate: 00=Disabled
				 *          01=7.8usec (256Mbit SDRAMs)
				 *          10=15.6us 11=125usec
				 */

#define R82600_SDRAMC	0x76	/* "SDRAM Control Register"
				 * More SDRAM related control bits
				 * all bits are R/W
				 *
				 * 15:8 Reserved.
				 *
				 * 7:5  Special SDRAM Mode Select
				 *
				 * 4    Force ECC
				 *
				 *        1=Drive ECC bits to 0 during
				 *          write cycles (i.e. ECC test mode)
				 *
				 *        0=Normal ECC functioning
				 *
				 * 3    Enhanced Paging Enable
				 *
				 * 2    CAS# Latency 0=3clks 1=2clks
				 *
				 * 1    RAS# to CAS# Delay 0=3 1=2
				 *
				 * 0    RAS# Precharge     0=3 1=2
				 */

#define R82600_EAP	0x80	/* ECC Error Address Pointer Register
				 *
				 * 31    Disable Hardware Scrubbing (RW)
				 *        0=Scrub on corrected read
				 *        1=Don't scrub on corrected read
				 *
				 * 30:12 Error Address Pointer (RO)
				 *        Upper 19 bits of error address
				 *
				 * 11:4  Syndrome Bits (RO)
				 *
				 * 3     BSERR# on multibit error (RW)
				 *        1=enable 0=disable
				 *
				 * 2     NMI on Single Bit Eror (RW)
				 *        1=NMI triggered by SBE n.b. other
				 *          prerequeists
				 *        0=NMI not triggered
				 *
				 * 1     MBE (R/WC)
				 *        read 1=MBE at EAP (see above)
				 *        read 0=no MBE, or SBE occurred first
				 *        write 1=Clear MBE status (must also
				 *          clear SBE)
				 *        write 0=NOP
				 *
				 * 1     SBE (R/WC)
				 *        read 1=SBE at EAP (see above)
				 *        read 0=no SBE, or MBE occurred first
				 *        write 1=Clear SBE status (must also
				 *          clear MBE)
				 *        write 0=NOP
				 */

#define R82600_DRBA	0x60	/* + 0x60..0x63 SDRAM Row Boundary Address
				 *  Registers
				 *
				 * 7:0  Address lines 30:24 - upper limit of
				 * each row [p57]
				 */

struct r82600_error_info {
	u32 eapr;
};

static bool disable_hardware_scrub;

static struct edac_pci_ctl_info *r82600_pci;

static void r82600_get_error_info(struct mem_ctl_info *mci,
				struct r82600_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->pdev);
	pci_read_config_dword(pdev, R82600_EAP, &info->eapr);

	if (info->eapr & BIT(0))
		/* Clear error to allow next error to be reported [p.62] */
		pci_write_bits32(pdev, R82600_EAP,
				 ((u32) BIT(0) & (u32) BIT(1)),
				 ((u32) BIT(0) & (u32) BIT(1)));

	if (info->eapr & BIT(1))
		/* Clear error to allow next error to be reported [p.62] */
		pci_write_bits32(pdev, R82600_EAP,
				 ((u32) BIT(0) & (u32) BIT(1)),
				 ((u32) BIT(0) & (u32) BIT(1)));
}

static int r82600_process_error_info(struct mem_ctl_info *mci,
				struct r82600_error_info *info,
				int handle_errors)
{
	int error_found;
	u32 eapaddr, page;
	u32 syndrome;

	error_found = 0;

	/* bits 30:12 store the upper 19 bits of the 32 bit error address */
	eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
	/* Syndrome in bits 11:4 [p.62]       */
	syndrome = (info->eapr >> 4) & 0xFF;

	/* the R82600 reports at less than page *
	 * granularity (upper 19 bits only)     */
	page = eapaddr >> PAGE_SHIFT;

	if (info->eapr & BIT(0)) {	/* CE? */
		error_found = 1;

		if (handle_errors)
			edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
					     page, 0, syndrome,
					     edac_mc_find_csrow_by_page(mci, page),
					     0, -1,
					     mci->ctl_name, "");
	}

	if (info->eapr & BIT(1)) {	/* UE? */
		error_found = 1;

		if (handle_errors)
			/* 82600 doesn't give enough info */
			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
					     page, 0, 0,
					     edac_mc_find_csrow_by_page(mci, page),
					     0, -1,
					     mci->ctl_name, "");
	}

	return error_found;
}

static void r82600_check(struct mem_ctl_info *mci)
{
	struct r82600_error_info info;

	edac_dbg(1, "MC%d\n", mci->mc_idx);
	r82600_get_error_info(mci, &info);
	r82600_process_error_info(mci, &info, 1);
}

static inline int ecc_enabled(u8 dramcr)
{
	return dramcr & BIT(5);
}

static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
			u8 dramcr)
{
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	int index;
	u8 drbar;		/* SDRAM Row Boundary Address Register */
	u32 row_high_limit, row_high_limit_last;
	u32 reg_sdram, ecc_on, row_base;

	ecc_on = ecc_enabled(dramcr);
	reg_sdram = dramcr & BIT(4);
	row_high_limit_last = 0;

	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = mci->csrows[index];
		dimm = csrow->channels[0]->dimm;

		/* find the DRAM Chip Select Base address and mask */
		pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);

		edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar);

		row_high_limit = ((u32) drbar << 24);
/*		row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */

		edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n",
			 index, row_high_limit, row_high_limit_last);

		/* Empty row [p.57] */
		if (row_high_limit == row_high_limit_last)
			continue;

		row_base = row_high_limit_last;

		csrow->first_page = row_base >> PAGE_SHIFT;
		csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;

		dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
		/* Error address is top 19 bits - so granularity is      *
		 * 14 bits                                               */
		dimm->grain = 1 << 14;
		dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
		/* FIXME - check that this is unknowable with this chipset */
		dimm->dtype = DEV_UNKNOWN;

		/* Mode is global on 82600 */
		dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
		row_high_limit_last = row_high_limit;
	}
}

static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
{
	struct mem_ctl_info *mci;
	struct edac_mc_layer layers[2];
	u8 dramcr;
	u32 eapr;
	u32 scrub_disabled;
	u32 sdram_refresh_rate;
	struct r82600_error_info discard;

	edac_dbg(0, "\n");
	pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
	pci_read_config_dword(pdev, R82600_EAP, &eapr);
	scrub_disabled = eapr & BIT(31);
	sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
	edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);
	edac_dbg(2, "DRAMC register = %#0x\n", dramcr);
	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = R82600_NR_CSROWS;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = R82600_NR_CHANS;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
	if (mci == NULL)
		return -ENOMEM;

	edac_dbg(0, "mci = %p\n", mci);
	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
	/* FIXME try to work out if the chip leads have been used for COM2
	 * instead on this board? [MA6?] MAYBE:
	 */

	/* On the R82600, the pins for memory bits 72:65 - i.e. the   *
	 * EC bits are shared with the pins for COM2 (!), so if COM2  *
	 * is enabled, we assume COM2 is wired up, and thus no EDAC   *
	 * is possible.                                               */
	mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;

	if (ecc_enabled(dramcr)) {
		if (scrub_disabled)
			edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n",
				 mci, eapr);
	} else
		mci->edac_cap = EDAC_FLAG_NONE;

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = R82600_REVISION;
	mci->ctl_name = "R82600";
	mci->dev_name = pci_name(pdev);
	mci->edac_check = r82600_check;
	mci->ctl_page_to_phys = NULL;
	r82600_init_csrows(mci, pdev, dramcr);
	r82600_get_error_info(mci, &discard);	/* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* get this far and it's successful */

	if (disable_hardware_scrub) {
		edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n");
		pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
	}

	/* allocating generic PCI control info */
	r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!r82600_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	edac_dbg(3, "success\n");
	return 0;

fail:
	edac_mc_free(mci);
	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int r82600_init_one(struct pci_dev *pdev,
			   const struct pci_device_id *ent)
{
	edac_dbg(0, "\n");

	/* don't need to call pci_enable_device() */
	return r82600_probe1(pdev, ent->driver_data);
}

static void r82600_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	edac_dbg(0, "\n");

	if (r82600_pci)
		edac_pci_release_generic_ctl(r82600_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id r82600_pci_tbl[] = {
	{
	 PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
	 },
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);

static struct pci_driver r82600_driver = {
	.name = EDAC_MOD_STR,
	.probe = r82600_init_one,
	.remove = r82600_remove_one,
	.id_table = r82600_pci_tbl,
};

static int __init r82600_init(void)
{
       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	return pci_register_driver(&r82600_driver);
}

static void __exit r82600_exit(void)
{
	pci_unregister_driver(&r82600_driver);
}

module_init(r82600_init);
module_exit(r82600_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
		"on behalf of EADS Astrium");
MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");

module_param(disable_hardware_scrub, bool, 0644);
MODULE_PARM_DESC(disable_hardware_scrub,
		 "If set, disable the chipset's automatic scrub for CEs");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
2f768af7 AC	1	/*
	2	* Radisys 82600 Embedded chipset Memory Controller kernel module
	3	* (C) 2005 EADS Astrium
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
	8	* Harbaugh, Dan Hollis <goemon at anime dot net> and others.
	9	*
	10	* $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
	11	*
	12	* Written with reference to 82600 High Integration Dual PCI System
	13	* Controller Data Book:
c4192705	14	* www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
2f768af7 AC	15	* references to this document given in []
	16	*/
	17
2f768af7 AC	18	#include <linux/module.h>
2f768af7 AC	19	#include <linux/init.h>
2f768af7 AC	20	#include <linux/pci.h>
2f768af7 AC	21	#include <linux/pci_ids.h>
c3c52bce	22	#include <linux/edac.h>
20bcb7a8	23	#include "edac_core.h"
2f768af7	24
152ba394	25	#define R82600_REVISION " Ver: 2.0.2"
929a40ec	26	#define EDAC_MOD_STR "r82600_edac"
37f04581	27
537fba28	28	#define r82600_printk(level, fmt, arg...) \
e7ecd891	29	edac_printk(level, "r82600", fmt, ##arg)
537fba28 DP	30
537fba28 DP	31	#define r82600_mc_printk(mci, level, fmt, arg...) \
e7ecd891	32	edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
537fba28	33
2f768af7 AC	34	/* Radisys say "The 82600 integrates a main memory SDRAM controller that
	35	* supports up to four banks of memory. The four banks can support a mix of
	36	* sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
	37	* each of which can be any size from 16MB to 512MB. Both registered (control
	38	* signals buffered) and unbuffered DIMM types are supported. Mixing of
	39	* registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
	40	* is not allowed. The 82600 SDRAM interface operates at the same frequency as
	41	* the CPU bus, 66MHz, 100MHz or 133MHz."
	42	*/
	43
	44	#define R82600_NR_CSROWS 4
	45	#define R82600_NR_CHANS 1
	46	#define R82600_NR_DIMMS 4
	47
	48	#define R82600_BRIDGE_ID 0x8200
	49
	50	/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
	51	#define R82600_DRAMC 0x57 /* Various SDRAM related control bits
	52	* all bits are R/W
	53	*
	54	* 7 SDRAM ISA Hole Enable
	55	* 6 Flash Page Mode Enable
	56	* 5 ECC Enable: 1=ECC 0=noECC
	57	* 4 DRAM DIMM Type: 1=
	58	* 3 BIOS Alias Disable
	59	* 2 SDRAM BIOS Flash Write Enable
	60	* 1:0 SDRAM Refresh Rate: 00=Disabled
	61	* 01=7.8usec (256Mbit SDRAMs)
	62	* 10=15.6us 11=125usec
	63	*/
	64
	65	#define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
	66	* More SDRAM related control bits
	67	* all bits are R/W
	68	*
	69	* 15:8 Reserved.
	70	*
	71	* 7:5 Special SDRAM Mode Select
	72	*
	73	* 4 Force ECC
	74	*
	75	* 1=Drive ECC bits to 0 during
	76	* write cycles (i.e. ECC test mode)
	77	*
	78	* 0=Normal ECC functioning
	79	*
	80	* 3 Enhanced Paging Enable
	81	*
	82	* 2 CAS# Latency 0=3clks 1=2clks
	83	*
	84	* 1 RAS# to CAS# Delay 0=3 1=2
	85	*
	86	* 0 RAS# Precharge 0=3 1=2
	87	*/
	88
	89	#define R82600_EAP 0x80 /* ECC Error Address Pointer Register
	90	*
	91	* 31 Disable Hardware Scrubbing (RW)
	92	* 0=Scrub on corrected read
	93	* 1=Don't scrub on corrected read
	94	*
	95	* 30:12 Error Address Pointer (RO)
	96	* Upper 19 bits of error address
	97	*
98	* 11:4 Syndrome Bits (RO)
99	*
100	* 3 BSERR# on multibit error (RW)
101	* 1=enable 0=disable
102	*
103	* 2 NMI on Single Bit Eror (RW)
104	* 1=NMI triggered by SBE n.b. other
105	* prerequeists
106	* 0=NMI not triggered
107	*
108	* 1 MBE (R/WC)
109	* read 1=MBE at EAP (see above)
110	* read 0=no MBE, or SBE occurred first
111	* write 1=Clear MBE status (must also
112	* clear SBE)
113	* write 0=NOP
114	*
115	* 1 SBE (R/WC)
116	* read 1=SBE at EAP (see above)
117	* read 0=no SBE, or MBE occurred first
118	* write 1=Clear SBE status (must also
119	* clear MBE)
120	* write 0=NOP
121	*/
122
25985edc	123	#define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address
2f768af7 AC	124	* Registers
	125	*
	126	* 7:0 Address lines 30:24 - upper limit of
	127	* each row [p57]
	128	*/
	129
	130	struct r82600_error_info {
	131	u32 eapr;
	132	};
	133
90ab5ee9	134	static bool disable_hardware_scrub;
2f768af7	135
456a2f95 DJ	136	static struct edac_pci_ctl_info *r82600_pci;
456a2f95 DJ	137
cddbfcac	138	static void r82600_get_error_info(struct mem_ctl_info *mci,
052dfb45	139	struct r82600_error_info *info)
2f768af7	140	{
37f04581 DT	141	struct pci_dev *pdev;
37f04581 DT	142
fd687502	143	pdev = to_pci_dev(mci->pdev);
37f04581	144	pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
2f768af7 AC	145
	146	if (info->eapr & BIT(0))
	147	/* Clear error to allow next error to be reported [p.62] */
37f04581	148	pci_write_bits32(pdev, R82600_EAP,
cddbfcac DT	149	((u32) BIT(0) & (u32) BIT(1)),
cddbfcac DT	150	((u32) BIT(0) & (u32) BIT(1)));
2f768af7 AC	151
	152	if (info->eapr & BIT(1))
	153	/* Clear error to allow next error to be reported [p.62] */
37f04581	154	pci_write_bits32(pdev, R82600_EAP,
cddbfcac DT	155	((u32) BIT(0) & (u32) BIT(1)),
cddbfcac DT	156	((u32) BIT(0) & (u32) BIT(1)));
2f768af7 AC	157	}
2f768af7 AC	158
cddbfcac	159	static int r82600_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	160	struct r82600_error_info *info,
052dfb45 DT	161	int handle_errors)
2f768af7 AC	162	{
	163	int error_found;
	164	u32 eapaddr, page;
	165	u32 syndrome;
	166
	167	error_found = 0;
	168
	169	/* bits 30:12 store the upper 19 bits of the 32 bit error address */
	170	eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
	171	/* Syndrome in bits 11:4 [p.62] */
	172	syndrome = (info->eapr >> 4) & 0xFF;
	173
	174	/* the R82600 reports at less than page *
	175	* granularity (upper 19 bits only) */
	176	page = eapaddr >> PAGE_SHIFT;
	177
cddbfcac	178	if (info->eapr & BIT(0)) { /* CE? */
2f768af7 AC	179	error_found = 1;
	180
	181	if (handle_errors)
9eb07a7f	182	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
63b5d1d9 MCC	183	page, 0, syndrome,
	184	edac_mc_find_csrow_by_page(mci, page),
	185	0, -1,
03f7eae8	186	mci->ctl_name, "");
2f768af7 AC	187	}
2f768af7 AC	188
cddbfcac	189	if (info->eapr & BIT(1)) { /* UE? */
2f768af7 AC	190	error_found = 1;
	191
	192	if (handle_errors)
	193	/* 82600 doesn't give enough info */
9eb07a7f	194	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
63b5d1d9 MCC	195	page, 0, 0,
	196	edac_mc_find_csrow_by_page(mci, page),
	197	0, -1,
03f7eae8	198	mci->ctl_name, "");
2f768af7 AC	199	}
	200
	201	return error_found;
	202	}
	203
	204	static void r82600_check(struct mem_ctl_info *mci)
	205	{
	206	struct r82600_error_info info;
	207
956b9ba1	208	edac_dbg(1, "MC%d\n", mci->mc_idx);
2f768af7 AC	209	r82600_get_error_info(mci, &info);
	210	r82600_process_error_info(mci, &info, 1);
	211	}
	212
13189525	213	static inline int ecc_enabled(u8 dramcr)
2f768af7	214	{
13189525 DT	215	return dramcr & BIT(5);
	216	}
	217
	218	static void r82600_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev,
052dfb45	219	u8 dramcr)
13189525 DT	220	{
13189525 DT	221	struct csrow_info *csrow;
084a4fcc	222	struct dimm_info *dimm;
2f768af7	223	int index;
25985edc	224	u8 drbar; /* SDRAM Row Boundary Address Register */
13189525 DT	225	u32 row_high_limit, row_high_limit_last;
	226	u32 reg_sdram, ecc_on, row_base;
	227
	228	ecc_on = ecc_enabled(dramcr);
	229	reg_sdram = dramcr & BIT(4);
	230	row_high_limit_last = 0;
	231
	232	for (index = 0; index < mci->nr_csrows; index++) {
de3910eb MCC	233	csrow = mci->csrows[index];
de3910eb MCC	234	dimm = csrow->channels[0]->dimm;
13189525 DT	235
	236	/* find the DRAM Chip Select Base address and mask */
	237	pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
	238
956b9ba1	239	edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar);
13189525 DT	240
	241	row_high_limit = ((u32) drbar << 24);
	242	/* row_high_limit = ((u32)drbar << 24) \| 0xffffffUL; */
	243
956b9ba1 JP	244	edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n",
956b9ba1 JP	245	index, row_high_limit, row_high_limit_last);
13189525 DT	246
	247	/* Empty row [p.57] */
	248	if (row_high_limit == row_high_limit_last)
	249	continue;
	250
	251	row_base = row_high_limit_last;
	252
	253	csrow->first_page = row_base >> PAGE_SHIFT;
	254	csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
a895bf8b MCC	255
a895bf8b MCC	256	dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
13189525 DT	257	/* Error address is top 19 bits - so granularity is *
13189525 DT	258	* 14 bits */
084a4fcc MCC	259	dimm->grain = 1 << 14;
084a4fcc MCC	260	dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
13189525	261	/* FIXME - check that this is unknowable with this chipset */
084a4fcc	262	dimm->dtype = DEV_UNKNOWN;
13189525 DT	263
13189525 DT	264	/* Mode is global on 82600 */
084a4fcc	265	dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
13189525 DT	266	row_high_limit_last = row_high_limit;
	267	}
	268	}
	269
	270	static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
	271	{
	272	struct mem_ctl_info *mci;
63b5d1d9	273	struct edac_mc_layer layers[2];
2f768af7	274	u8 dramcr;
2f768af7 AC	275	u32 eapr;
	276	u32 scrub_disabled;
	277	u32 sdram_refresh_rate;
749ede57	278	struct r82600_error_info discard;
2f768af7	279
956b9ba1	280	edac_dbg(0, "\n");
2f768af7 AC	281	pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
2f768af7 AC	282	pci_read_config_dword(pdev, R82600_EAP, &eapr);
2f768af7 AC	283	scrub_disabled = eapr & BIT(31);
2f768af7 AC	284	sdram_refresh_rate = dramcr & (BIT(0) \| BIT(1));
956b9ba1 JP	285	edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);
956b9ba1 JP	286	edac_dbg(2, "DRAMC register = %#0x\n", dramcr);
63b5d1d9 MCC	287	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	288	layers[0].size = R82600_NR_CSROWS;
	289	layers[0].is_virt_csrow = true;
	290	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	291	layers[1].size = R82600_NR_CHANS;
	292	layers[1].is_virt_csrow = false;
ca0907b9	293	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
13189525 DT	294	if (mci == NULL)
13189525 DT	295	return -ENOMEM;
2f768af7	296
956b9ba1	297	edac_dbg(0, "mci = %p\n", mci);
fd687502	298	mci->pdev = &pdev->dev;
2f768af7	299	mci->mtype_cap = MEM_FLAG_RDDR \| MEM_FLAG_DDR;
2f768af7	300	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
e7ecd891 DP	301	/* FIXME try to work out if the chip leads have been used for COM2
	302	* instead on this board? [MA6?] MAYBE:
	303	*/
2f768af7 AC	304
	305	/* On the R82600, the pins for memory bits 72:65 - i.e. the *
	306	* EC bits are shared with the pins for COM2 (!), so if COM2 *
	307	* is enabled, we assume COM2 is wired up, and thus no EDAC *
	308	* is possible. */
	309	mci->edac_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
e7ecd891	310
13189525	311	if (ecc_enabled(dramcr)) {
2f768af7	312	if (scrub_disabled)
956b9ba1 JP	313	edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n",
956b9ba1 JP	314	mci, eapr);
2f768af7 AC	315	} else
	316	mci->edac_cap = EDAC_FLAG_NONE;
	317
680cbbbb	318	mci->mod_name = EDAC_MOD_STR;
37f04581	319	mci->mod_ver = R82600_REVISION;
2f768af7	320	mci->ctl_name = "R82600";
c4192705	321	mci->dev_name = pci_name(pdev);
2f768af7 AC	322	mci->edac_check = r82600_check;
2f768af7 AC	323	mci->ctl_page_to_phys = NULL;
13189525	324	r82600_init_csrows(mci, pdev, dramcr);
cddbfcac	325	r82600_get_error_info(mci, &discard); /* clear counters */
2f768af7	326
2d7bbb91 DT	327	/* Here we assume that we will never see multiple instances of this
	328	* type of memory controller. The ID is therefore hardcoded to 0.
	329	*/
b8f6f975	330	if (edac_mc_add_mc(mci)) {
956b9ba1	331	edac_dbg(3, "failed edac_mc_add_mc()\n");
2f768af7 AC	332	goto fail;
	333	}
	334
	335	/* get this far and it's successful */
	336
2f768af7	337	if (disable_hardware_scrub) {
956b9ba1	338	edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n");
37f04581	339	pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
2f768af7 AC	340	}
2f768af7 AC	341
456a2f95 DJ	342	/* allocating generic PCI control info */
	343	r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	344	if (!r82600_pci) {
	345	printk(KERN_WARNING
	346	"%s(): Unable to create PCI control\n",
	347	__func__);
	348	printk(KERN_WARNING
	349	"%s(): PCI error report via EDAC not setup\n",
	350	__func__);
	351	}
	352
956b9ba1	353	edac_dbg(3, "success\n");
2f768af7 AC	354	return 0;
2f768af7 AC	355
052dfb45	356	fail:
13189525 DT	357	edac_mc_free(mci);
13189525 DT	358	return -ENODEV;
2f768af7 AC	359	}
	360
	361	/* returns count (>= 0), or negative on error */
9b3c6e85 GKH	362	static int r82600_init_one(struct pci_dev *pdev,
9b3c6e85 GKH	363	const struct pci_device_id *ent)
2f768af7	364	{
956b9ba1	365	edac_dbg(0, "\n");
2f768af7	366
ee6583f6	367	/* don't need to call pci_enable_device() */
2f768af7 AC	368	return r82600_probe1(pdev, ent->driver_data);
	369	}
	370
9b3c6e85	371	static void r82600_remove_one(struct pci_dev *pdev)
2f768af7 AC	372	{
	373	struct mem_ctl_info *mci;
	374
956b9ba1	375	edac_dbg(0, "\n");
2f768af7	376
456a2f95 DJ	377	if (r82600_pci)
	378	edac_pci_release_generic_ctl(r82600_pci);
	379
37f04581	380	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
18dbc337 DP	381	return;
	382
	383	edac_mc_free(mci);
2f768af7 AC	384	}
2f768af7 AC	385
ba935f40	386	static const struct pci_device_id r82600_pci_tbl[] = {
e7ecd891	387	{
cddbfcac DT	388	PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
cddbfcac DT	389	},
e7ecd891	390	{
cddbfcac DT	391	0,
cddbfcac DT	392	} /* 0 terminated list. */
2f768af7 AC	393	};
	394
	395	MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
	396
2f768af7	397	static struct pci_driver r82600_driver = {
680cbbbb	398	.name = EDAC_MOD_STR,
2f768af7	399	.probe = r82600_init_one,
9b3c6e85	400	.remove = r82600_remove_one,
2f768af7 AC	401	.id_table = r82600_pci_tbl,
	402	};
	403
da9bb1d2	404	static int __init r82600_init(void)
2f768af7	405	{
c3c52bce HM	406	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	407	opstate_init();
	408
2f768af7 AC	409	return pci_register_driver(&r82600_driver);
	410	}
	411
2f768af7 AC	412	static void __exit r82600_exit(void)
	413	{
	414	pci_unregister_driver(&r82600_driver);
	415	}
	416
2f768af7 AC	417	module_init(r82600_init);
	418	module_exit(r82600_exit);
	419
2f768af7 AC	420	MODULE_LICENSE("GPL");
2f768af7 AC	421	MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
052dfb45	422	"on behalf of EADS Astrium");
2f768af7 AC	423	MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
	424
	425	module_param(disable_hardware_scrub, bool, 0644);
	426	MODULE_PARM_DESC(disable_hardware_scrub,
	427	"If set, disable the chipset's automatic scrub for CEs");
c3c52bce HM	428
	429	module_param(edac_op_state, int, 0444);
	430	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");