[linux-2.6-block.git] / drivers / edac / i82860_edac.c

/*
 * Intel 82860 Memory Controller kernel module
 * (C) 2005 Red Hat (http://www.redhat.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Ben Woodard <woodard@redhat.com>
 * shamelessly copied from and based upon the edac_i82875 driver
 * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/edac.h>
#include "edac_core.h"

#define  I82860_REVISION " Ver: 2.0.2 " __DATE__
#define EDAC_MOD_STR	"i82860_edac"

#define i82860_printk(level, fmt, arg...) \
	edac_printk(level, "i82860", fmt, ##arg)

#define i82860_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)

#ifndef PCI_DEVICE_ID_INTEL_82860_0
#define PCI_DEVICE_ID_INTEL_82860_0	0x2531
#endif				/* PCI_DEVICE_ID_INTEL_82860_0 */

#define I82860_MCHCFG 0x50
#define I82860_GBA 0x60
#define I82860_GBA_MASK 0x7FF
#define I82860_GBA_SHIFT 24
#define I82860_ERRSTS 0xC8
#define I82860_EAP 0xE4
#define I82860_DERRCTL_STS 0xE2

enum i82860_chips {
	I82860 = 0,
};

struct i82860_dev_info {
	const char *ctl_name;
};

struct i82860_error_info {
	u16 errsts;
	u32 eap;
	u16 derrsyn;
	u16 errsts2;
};

static const struct i82860_dev_info i82860_devs[] = {
	[I82860] = {
		.ctl_name = "i82860"},
};

static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code
					 * has already registered driver
					 */
static struct edac_pci_ctl_info *i82860_pci;

static void i82860_get_error_info(struct mem_ctl_info *mci,
				struct i82860_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->dev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);

	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);

	/*
	 * If the error is the same for both reads then the first set of reads
	 * is valid.  If there is a change then there is a CE no info and the
	 * second set of reads is valid and should be UE info.
	 */
	if (!(info->errsts2 & 0x0003))
		return;

	if ((info->errsts ^ info->errsts2) & 0x0003) {
		pci_read_config_dword(pdev, I82860_EAP, &info->eap);
		pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	}
}

static int i82860_process_error_info(struct mem_ctl_info *mci,
				struct i82860_error_info *info,
				int handle_errors)
{
	int row;

	if (!(info->errsts2 & 0x0003))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & 0x0003) {
		edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
		info->errsts = info->errsts2;
	}

	info->eap >>= PAGE_SHIFT;
	row = edac_mc_find_csrow_by_page(mci, info->eap);

	if (info->errsts & 0x0002)
		edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
	else
		edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
				"i82860 UE");

	return 1;
}

static void i82860_check(struct mem_ctl_info *mci)
{
	struct i82860_error_info info;

	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
	i82860_get_error_info(mci, &info);
	i82860_process_error_info(mci, &info, 1);
}

static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
{
	unsigned long last_cumul_size;
	u16 mchcfg_ddim;	/* DRAM Data Integrity Mode 0=none, 2=edac */
	u16 value;
	u32 cumul_size;
	struct csrow_info *csrow;
	int index;

	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
	mchcfg_ddim = mchcfg_ddim & 0x180;
	last_cumul_size = 0;

	/* The group row boundary (GRA) reg values are boundary address
	 * for each DRAM row with a granularity of 16MB.  GRA regs are
	 * cumulative; therefore GRA15 will contain the total memory contained
	 * in all eight rows.
	 */
	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = &mci->csrows[index];
		pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
		cumul_size = (value & I82860_GBA_MASK) <<
			(I82860_GBA_SHIFT - PAGE_SHIFT);
		debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
			cumul_size);

		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		csrow->nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;
		csrow->grain = 1 << 12;	/* I82860_EAP has 4KiB reolution */
		csrow->mtype = MEM_RMBS;
		csrow->dtype = DEV_UNKNOWN;
		csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
	}
}

static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
{
	struct mem_ctl_info *mci;
	struct i82860_error_info discard;

	/* RDRAM has channels but these don't map onto the abstractions that
	   edac uses.
	   The device groups from the GRA registers seem to map reasonably
	   well onto the notion of a chip select row.
	   There are 16 GRA registers and since the name is associated with
	   the channel and the GRA registers map to physical devices so we are
	   going to make 1 channel for group.
	 */
	mci = edac_mc_alloc(0, 16, 1, 0);

	if (!mci)
		return -ENOMEM;

	debugf3("%s(): init mci\n", __func__);
	mci->dev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	/* I"m not sure about this but I think that all RDRAM is SECDED */
	mci->edac_cap = EDAC_FLAG_SECDED;
	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = I82860_REVISION;
	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i82860_check;
	mci->ctl_page_to_phys = NULL;
	i82860_init_csrows(mci, pdev);
	i82860_get_error_info(mci, &discard);	/* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci)) {
		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
		goto fail;
	}

	/* allocating generic PCI control info */
	i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i82860_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	debugf3("%s(): success\n", __func__);

	return 0;

fail:
	edac_mc_free(mci);
	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int __devinit i82860_init_one(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
	int rc;

	debugf0("%s()\n", __func__);
	i82860_printk(KERN_INFO, "i82860 init one\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i82860_probe1(pdev, ent->driver_data);

	if (rc == 0)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void __devexit i82860_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	debugf0("%s()\n", __func__);

	if (i82860_pci)
		edac_pci_release_generic_ctl(i82860_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
	{
	 PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 I82860},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);

static struct pci_driver i82860_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82860_init_one,
	.remove = __devexit_p(i82860_remove_one),
	.id_table = i82860_pci_tbl,
};

static int __init i82860_init(void)
{
	int pci_rc;

	debugf3("%s()\n", __func__);

       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
		goto fail0;

	if (!mci_pdev) {
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_82860_0, NULL);

		if (mci_pdev == NULL) {
			debugf0("860 pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);

		if (pci_rc < 0) {
			debugf0("860 init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i82860_driver);

fail0:
	if (mci_pdev != NULL)
		pci_dev_put(mci_pdev);

	return pci_rc;
}

static void __exit i82860_exit(void)
{
	debugf3("%s()\n", __func__);

	pci_unregister_driver(&i82860_driver);

	if (mci_pdev != NULL)
		pci_dev_put(mci_pdev);
}

module_init(i82860_init);
module_exit(i82860_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
		"Ben Woodard <woodard@redhat.com>");
MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
0d88a10e AC	1	/*
	2	* Intel 82860 Memory Controller kernel module
	3	* (C) 2005 Red Hat (http://www.redhat.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Ben Woodard <woodard@redhat.com>
	8	* shamelessly copied from and based upon the edac_i82875 driver
	9	* by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
	10	*/
	11
0d88a10e AC	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
	16	#include <linux/slab.h>
c3c52bce	17	#include <linux/edac.h>
20bcb7a8	18	#include "edac_core.h"
0d88a10e	19
20bcb7a8	20	#define I82860_REVISION " Ver: 2.0.2 " __DATE__
929a40ec	21	#define EDAC_MOD_STR "i82860_edac"
37f04581	22
537fba28	23	#define i82860_printk(level, fmt, arg...) \
e7ecd891	24	edac_printk(level, "i82860", fmt, ##arg)
537fba28 DP	25
537fba28 DP	26	#define i82860_mc_printk(mci, level, fmt, arg...) \
e7ecd891	27	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
537fba28	28
0d88a10e AC	29	#ifndef PCI_DEVICE_ID_INTEL_82860_0
	30	#define PCI_DEVICE_ID_INTEL_82860_0 0x2531
	31	#endif /* PCI_DEVICE_ID_INTEL_82860_0 */
	32
	33	#define I82860_MCHCFG 0x50
	34	#define I82860_GBA 0x60
	35	#define I82860_GBA_MASK 0x7FF
	36	#define I82860_GBA_SHIFT 24
	37	#define I82860_ERRSTS 0xC8
	38	#define I82860_EAP 0xE4
	39	#define I82860_DERRCTL_STS 0xE2
	40
	41	enum i82860_chips {
	42	I82860 = 0,
	43	};
	44
	45	struct i82860_dev_info {
	46	const char *ctl_name;
	47	};
	48
	49	struct i82860_error_info {
	50	u16 errsts;
	51	u32 eap;
	52	u16 derrsyn;
	53	u16 errsts2;
	54	};
	55
	56	static const struct i82860_dev_info i82860_devs[] = {
	57	[I82860] = {
052dfb45	58	.ctl_name = "i82860"},
0d88a10e AC	59	};
0d88a10e AC	60
f044091c	61	static struct pci_dev mci_pdev; / init dev: in case that AGP code
e7ecd891 DP	62	* has already registered driver
e7ecd891 DP	63	*/
456a2f95	64	static struct edac_pci_ctl_info *i82860_pci;
0d88a10e	65
e7ecd891	66	static void i82860_get_error_info(struct mem_ctl_info *mci,
052dfb45	67	struct i82860_error_info *info)
0d88a10e	68	{
37f04581 DT	69	struct pci_dev *pdev;
	70
	71	pdev = to_pci_dev(mci->dev);
	72
0d88a10e AC	73	/*
	74	* This is a mess because there is no atomic way to read all the
	75	* registers at once and the registers can transition from CE being
	76	* overwritten by UE.
	77	*/
37f04581 DT	78	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
	79	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
	80	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	81	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
0d88a10e	82
37f04581	83	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
0d88a10e AC	84
	85	/*
	86	* If the error is the same for both reads then the first set of reads
	87	* is valid. If there is a change then there is a CE no info and the
	88	* second set of reads is valid and should be UE info.
	89	*/
	90	if (!(info->errsts2 & 0x0003))
	91	return;
e7ecd891	92
0d88a10e	93	if ((info->errsts ^ info->errsts2) & 0x0003) {
37f04581	94	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
b4e8b372	95	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
0d88a10e AC	96	}
	97	}
	98
e7ecd891	99	static int i82860_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	100	struct i82860_error_info *info,
052dfb45 DT	101	int handle_errors)
0d88a10e AC	102	{
	103	int row;
	104
	105	if (!(info->errsts2 & 0x0003))
	106	return 0;
	107
	108	if (!handle_errors)
	109	return 1;
	110
	111	if ((info->errsts ^ info->errsts2) & 0x0003) {
	112	edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
	113	info->errsts = info->errsts2;
	114	}
	115
	116	info->eap >>= PAGE_SHIFT;
	117	row = edac_mc_find_csrow_by_page(mci, info->eap);
	118
	119	if (info->errsts & 0x0002)
	120	edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
	121	else
e7ecd891	122	edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
052dfb45	123	"i82860 UE");
0d88a10e AC	124
	125	return 1;
	126	}
	127
	128	static void i82860_check(struct mem_ctl_info *mci)
	129	{
	130	struct i82860_error_info info;
	131
537fba28	132	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
0d88a10e AC	133	i82860_get_error_info(mci, &info);
	134	i82860_process_error_info(mci, &info, 1);
	135	}
	136
13189525	137	static void i82860_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev)
0d88a10e	138	{
0d88a10e	139	unsigned long last_cumul_size;
b4e8b372	140	u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
13189525 DT	141	u16 value;
	142	u32 cumul_size;
	143	struct csrow_info *csrow;
	144	int index;
	145
	146	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
	147	mchcfg_ddim = mchcfg_ddim & 0x180;
	148	last_cumul_size = 0;
	149
	150	/* The group row boundary (GRA) reg values are boundary address
	151	* for each DRAM row with a granularity of 16MB. GRA regs are
	152	* cumulative; therefore GRA15 will contain the total memory contained
	153	* in all eight rows.
	154	*/
	155	for (index = 0; index < mci->nr_csrows; index++) {
	156	csrow = &mci->csrows[index];
	157	pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
	158	cumul_size = (value & I82860_GBA_MASK) <<
052dfb45	159	(I82860_GBA_SHIFT - PAGE_SHIFT);
13189525 DT	160	debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
13189525 DT	161	cumul_size);
0d88a10e	162
13189525 DT	163	if (cumul_size == last_cumul_size)
	164	continue; /* not populated */
	165
	166	csrow->first_page = last_cumul_size;
	167	csrow->last_page = cumul_size - 1;
	168	csrow->nr_pages = cumul_size - last_cumul_size;
	169	last_cumul_size = cumul_size;
	170	csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
	171	csrow->mtype = MEM_RMBS;
	172	csrow->dtype = DEV_UNKNOWN;
	173	csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
	174	}
	175	}
	176
	177	static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
	178	{
	179	struct mem_ctl_info *mci;
	180	struct i82860_error_info discard;
0d88a10e AC	181
	182	/* RDRAM has channels but these don't map onto the abstractions that
	183	edac uses.
	184	The device groups from the GRA registers seem to map reasonably
	185	well onto the notion of a chip select row.
	186	There are 16 GRA registers and since the name is associated with
	187	the channel and the GRA registers map to physical devices so we are
	188	going to make 1 channel for group.
	189	*/
b8f6f975	190	mci = edac_mc_alloc(0, 16, 1, 0);
e7ecd891	191
0d88a10e AC	192	if (!mci)
	193	return -ENOMEM;
	194
537fba28	195	debugf3("%s(): init mci\n", __func__);
37f04581	196	mci->dev = &pdev->dev;
0d88a10e	197	mci->mtype_cap = MEM_FLAG_DDR;
0d88a10e AC	198	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	199	/* I"m not sure about this but I think that all RDRAM is SECDED */
	200	mci->edac_cap = EDAC_FLAG_SECDED;
680cbbbb	201	mci->mod_name = EDAC_MOD_STR;
37f04581	202	mci->mod_ver = I82860_REVISION;
0d88a10e	203	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
c4192705	204	mci->dev_name = pci_name(pdev);
0d88a10e AC	205	mci->edac_check = i82860_check;
0d88a10e AC	206	mci->ctl_page_to_phys = NULL;
13189525	207	i82860_init_csrows(mci, pdev);
b4e8b372	208	i82860_get_error_info(mci, &discard); /* clear counters */
0d88a10e	209
2d7bbb91 DT	210	/* Here we assume that we will never see multiple instances of this
	211	* type of memory controller. The ID is therefore hardcoded to 0.
	212	*/
b8f6f975	213	if (edac_mc_add_mc(mci)) {
537fba28	214	debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
13189525	215	goto fail;
0d88a10e	216	}
e7ecd891	217
456a2f95 DJ	218	/* allocating generic PCI control info */
	219	i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	220	if (!i82860_pci) {
	221	printk(KERN_WARNING
	222	"%s(): Unable to create PCI control\n",
	223	__func__);
	224	printk(KERN_WARNING
	225	"%s(): PCI error report via EDAC not setup\n",
	226	__func__);
	227	}
	228
13189525 DT	229	/* get this far and it's successful */
	230	debugf3("%s(): success\n", __func__);
	231
	232	return 0;
	233
052dfb45	234	fail:
13189525 DT	235	edac_mc_free(mci);
13189525 DT	236	return -ENODEV;
0d88a10e AC	237	}
	238
	239	/* returns count (>= 0), or negative on error */
	240	static int __devinit i82860_init_one(struct pci_dev *pdev,
052dfb45	241	const struct pci_device_id *ent)
0d88a10e AC	242	{
	243	int rc;
	244
537fba28	245	debugf0("%s()\n", __func__);
537fba28	246	i82860_printk(KERN_INFO, "i82860 init one\n");
e7ecd891 DP	247
e7ecd891 DP	248	if (pci_enable_device(pdev) < 0)
0d88a10e	249	return -EIO;
e7ecd891	250
0d88a10e	251	rc = i82860_probe1(pdev, ent->driver_data);
e7ecd891 DP	252
e7ecd891 DP	253	if (rc == 0)
0d88a10e	254	mci_pdev = pci_dev_get(pdev);
e7ecd891	255
0d88a10e AC	256	return rc;
	257	}
	258
	259	static void __devexit i82860_remove_one(struct pci_dev *pdev)
	260	{
	261	struct mem_ctl_info *mci;
	262
537fba28	263	debugf0("%s()\n", __func__);
0d88a10e	264
456a2f95 DJ	265	if (i82860_pci)
	266	edac_pci_release_generic_ctl(i82860_pci);
	267
37f04581	268	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
18dbc337 DP	269	return;
	270
	271	edac_mc_free(mci);
0d88a10e AC	272	}
	273
	274	static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
e7ecd891	275	{
b4e8b372 DJ	276	PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
b4e8b372 DJ	277	I82860},
e7ecd891	278	{
b4e8b372 DJ	279	0,
b4e8b372 DJ	280	} /* 0 terminated list. */
0d88a10e AC	281	};
	282
	283	MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
	284
	285	static struct pci_driver i82860_driver = {
680cbbbb	286	.name = EDAC_MOD_STR,
0d88a10e AC	287	.probe = i82860_init_one,
	288	.remove = __devexit_p(i82860_remove_one),
	289	.id_table = i82860_pci_tbl,
	290	};
	291
da9bb1d2	292	static int __init i82860_init(void)
0d88a10e AC	293	{
	294	int pci_rc;
	295
537fba28	296	debugf3("%s()\n", __func__);
e7ecd891	297
c3c52bce HM	298	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	299	opstate_init();
	300
0d88a10e	301	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
e8a491b4	302	goto fail0;
0d88a10e AC	303
0d88a10e AC	304	if (!mci_pdev) {
0d88a10e	305	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45	306	PCI_DEVICE_ID_INTEL_82860_0, NULL);
e7ecd891	307
0d88a10e AC	308	if (mci_pdev == NULL) {
0d88a10e AC	309	debugf0("860 pci_get_device fail\n");
e8a491b4 DP	310	pci_rc = -ENODEV;
e8a491b4 DP	311	goto fail1;
0d88a10e	312	}
e7ecd891	313
0d88a10e	314	pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
e7ecd891	315
0d88a10e AC	316	if (pci_rc < 0) {
0d88a10e AC	317	debugf0("860 init fail\n");
e8a491b4 DP	318	pci_rc = -ENODEV;
e8a491b4 DP	319	goto fail1;
0d88a10e AC	320	}
0d88a10e AC	321	}
e7ecd891	322
0d88a10e	323	return 0;
e8a491b4	324
052dfb45	325	fail1:
e8a491b4 DP	326	pci_unregister_driver(&i82860_driver);
e8a491b4 DP	327
052dfb45	328	fail0:
e8a491b4 DP	329	if (mci_pdev != NULL)
	330	pci_dev_put(mci_pdev);
	331
	332	return pci_rc;
0d88a10e AC	333	}
	334
	335	static void __exit i82860_exit(void)
	336	{
537fba28	337	debugf3("%s()\n", __func__);
0d88a10e AC	338
0d88a10e AC	339	pci_unregister_driver(&i82860_driver);
e8a491b4 DP	340
e8a491b4 DP	341	if (mci_pdev != NULL)
0d88a10e	342	pci_dev_put(mci_pdev);
0d88a10e AC	343	}
	344
	345	module_init(i82860_init);
	346	module_exit(i82860_exit);
	347
	348	MODULE_LICENSE("GPL");
e7ecd891	349	MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
052dfb45	350	"Ben Woodard <woodard@redhat.com>");
0d88a10e	351	MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
c3c52bce HM	352
	353	module_param(edac_op_state, int, 0444);
	354	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");