[linux-2.6-block.git] / drivers / edac / i82443bxgx_edac.c

/*
 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
 * module (C) 2006 Tim Small
 *
 * This file may be distributed under the terms of the GNU General
 * Public License.
 *
 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
 * others.
 *
 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
 *
 * Written with reference to 82443BX Host Bridge Datasheet:
 * http://download.intel.com/design/chipsets/datashts/29063301.pdf
 * references to this document given in [].
 *
 * This module doesn't support the 440LX, but it may be possible to
 * make it do so (the 440LX's register definitions are different, but
 * not completely so - I haven't studied them in enough detail to know
 * how easy this would be).
 */

#include <linux/module.h>
#include <linux/init.h>

#include <linux/pci.h>
#include <linux/pci_ids.h>


#include <linux/edac.h>
#include "edac_core.h"

#define I82443_REVISION	"0.1"

#define EDAC_MOD_STR    "i82443bxgx_edac"

/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
 * rows" "The 82443BX supports multiple-bit error detection and
 * single-bit error correction when ECC mode is enabled and
 * single/multi-bit error detection when correction is disabled.
 * During writes to the DRAM, the 82443BX generates ECC for the data
 * on a QWord basis. Partial QWord writes require a read-modify-write
 * cycle when ECC is enabled."
*/

/* "Additionally, the 82443BX ensures that the data is corrected in
 * main memory so that accumulation of errors is prevented. Another
 * error within the same QWord would result in a double-bit error
 * which is unrecoverable. This is known as hardware scrubbing since
 * it requires no software intervention to correct the data in memory."
 */

/* [Also see page 100 (section 4.3), "DRAM Interface"]
 * [Also see page 112 (section 4.6.1.4), ECC]
 */

#define I82443BXGX_NR_CSROWS 8
#define I82443BXGX_NR_CHANS  1
#define I82443BXGX_NR_DIMMS  4

/* 82443 PCI Device 0 */
#define I82443BXGX_NBXCFG 0x50	/* 32bit register starting at this PCI
				 * config space offset */
#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24	/* Array of bits, zero if
						 * row is non-ECC */
#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12	/* 2 bits,00=100MHz,10=66 MHz */

#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7	/* 2 bits:       */
#define I82443BXGX_NBXCFG_INTEGRITY_NONE   0x0	/* 00 = Non-ECC */
#define I82443BXGX_NBXCFG_INTEGRITY_EC     0x1	/* 01 = EC (only) */
#define I82443BXGX_NBXCFG_INTEGRITY_ECC    0x2	/* 10 = ECC */
#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB  0x3	/* 11 = ECC + HW Scrub */

#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE  6

/* 82443 PCI Device 0 */
#define I82443BXGX_EAP   0x80	/* 32bit register starting at this PCI
				 * config space offset, Error Address
				 * Pointer Register */
#define I82443BXGX_EAP_OFFSET_EAP  12	/* High 20 bits of error address */
#define I82443BXGX_EAP_OFFSET_MBE  BIT(1)	/* Err at EAP was multi-bit (W1TC) */
#define I82443BXGX_EAP_OFFSET_SBE  BIT(0)	/* Err at EAP was single-bit (W1TC) */

#define I82443BXGX_ERRCMD  0x90	/* 8bit register starting at this PCI
				 * config space offset. */
#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1)	/* 1 = enable */
#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0)	/* 1 = enable */

#define I82443BXGX_ERRSTS  0x91	/* 16bit register starting at this PCI
				 * config space offset. */
#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5	/* 3 bits - first err row multibit */
#define I82443BXGX_ERRSTS_OFFSET_MEF   BIT(4)	/* 1 = MBE occurred */
#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1	/* 3 bits - first err row singlebit */
#define I82443BXGX_ERRSTS_OFFSET_SEF   BIT(0)	/* 1 = SBE occurred */

#define I82443BXGX_DRAMC 0x57	/* 8bit register starting at this PCI
				 * config space offset. */
#define I82443BXGX_DRAMC_OFFSET_DT 3	/* 2 bits, DRAM Type */
#define I82443BXGX_DRAMC_DRAM_IS_EDO 0	/* 00 = EDO */
#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1	/* 01 = SDRAM */
#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2	/* 10 = Registered SDRAM */

#define I82443BXGX_DRB 0x60	/* 8x 8bit registers starting at this PCI
				 * config space offset. */

/* FIXME - don't poll when ECC disabled? */

struct i82443bxgx_edacmc_error_info {
	u32 eap;
};

static struct edac_pci_ctl_info *i82443bxgx_pci;

static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code has
					 * already registered driver
					 */

static int i82443bxgx_registered = 1;

static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
				struct i82443bxgx_edacmc_error_info
				*info)
{
	struct pci_dev *pdev;
	pdev = to_pci_dev(mci->pdev);
	pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
	if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
		/* Clear error to allow next error to be reported [p.61] */
		pci_write_bits32(pdev, I82443BXGX_EAP,
				 I82443BXGX_EAP_OFFSET_SBE,
				 I82443BXGX_EAP_OFFSET_SBE);

	if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
		/* Clear error to allow next error to be reported [p.61] */
		pci_write_bits32(pdev, I82443BXGX_EAP,
				 I82443BXGX_EAP_OFFSET_MBE,
				 I82443BXGX_EAP_OFFSET_MBE);
}

static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
						struct
						i82443bxgx_edacmc_error_info
						*info, int handle_errors)
{
	int error_found = 0;
	u32 eapaddr, page, pageoffset;

	/* bits 30:12 hold the 4kb block in which the error occurred
	 * [p.61] */
	eapaddr = (info->eap & 0xfffff000);
	page = eapaddr >> PAGE_SHIFT;
	pageoffset = eapaddr - (page << PAGE_SHIFT);

	if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
		error_found = 1;
		if (handle_errors)
			edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
					     page, pageoffset, 0,
					     edac_mc_find_csrow_by_page(mci, page),
					     0, -1, mci->ctl_name, "");
	}

	if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
		error_found = 1;
		if (handle_errors)
			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
					     page, pageoffset, 0,
					     edac_mc_find_csrow_by_page(mci, page),
					     0, -1, mci->ctl_name, "");
	}

	return error_found;
}

static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
{
	struct i82443bxgx_edacmc_error_info info;

	edac_dbg(1, "MC%d\n", mci->mc_idx);
	i82443bxgx_edacmc_get_error_info(mci, &info);
	i82443bxgx_edacmc_process_error_info(mci, &info, 1);
}

static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
				struct pci_dev *pdev,
				enum edac_type edac_mode,
				enum mem_type mtype)
{
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	int index;
	u8 drbar, dramc;
	u32 row_base, row_high_limit, row_high_limit_last;

	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
	row_high_limit_last = 0;
	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = mci->csrows[index];
		dimm = csrow->channels[0]->dimm;

		pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
		edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n",
			 mci->mc_idx, index, drbar);
		row_high_limit = ((u32) drbar << 23);
		/* find the DRAM Chip Select Base address and mask */
		edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n",
			 mci->mc_idx, index, row_high_limit,
			 row_high_limit_last);

		/* 440GX goes to 2GB, represented with a DRB of 0. */
		if (row_high_limit_last && !row_high_limit)
			row_high_limit = 1UL << 31;

		/* This row is empty [p.49] */
		if (row_high_limit == row_high_limit_last)
			continue;
		row_base = row_high_limit_last;
		csrow->first_page = row_base >> PAGE_SHIFT;
		csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
		dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
		/* EAP reports in 4kilobyte granularity [61] */
		dimm->grain = 1 << 12;
		dimm->mtype = mtype;
		/* I don't think 440BX can tell you device type? FIXME? */
		dimm->dtype = DEV_UNKNOWN;
		/* Mode is global to all rows on 440BX */
		dimm->edac_mode = edac_mode;
		row_high_limit_last = row_high_limit;
	}
}

static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
{
	struct mem_ctl_info *mci;
	struct edac_mc_layer layers[2];
	u8 dramc;
	u32 nbxcfg, ecc_mode;
	enum mem_type mtype;
	enum edac_type edac_mode;

	edac_dbg(0, "MC:\n");

	/* Something is really hosed if PCI config space reads from
	 * the MC aren't working.
	 */
	if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
		return -EIO;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = I82443BXGX_NR_CSROWS;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = I82443BXGX_NR_CHANS;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
	if (mci == NULL)
		return -ENOMEM;

	edac_dbg(0, "MC: mci = %p\n", mci);
	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
	switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
	case I82443BXGX_DRAMC_DRAM_IS_EDO:
		mtype = MEM_EDO;
		break;
	case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
		mtype = MEM_SDR;
		break;
	case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
		mtype = MEM_RDR;
		break;
	default:
		edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n");
		mtype = -MEM_UNKNOWN;
	}

	if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
		mci->edac_cap = mci->edac_ctl_cap;
	else
		mci->edac_cap = EDAC_FLAG_NONE;

	mci->scrub_cap = SCRUB_FLAG_HW_SRC;
	pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
	ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
		(BIT(0) | BIT(1)));

	mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
		? SCRUB_HW_SRC : SCRUB_NONE;

	switch (ecc_mode) {
	case I82443BXGX_NBXCFG_INTEGRITY_NONE:
		edac_mode = EDAC_NONE;
		break;
	case I82443BXGX_NBXCFG_INTEGRITY_EC:
		edac_mode = EDAC_EC;
		break;
	case I82443BXGX_NBXCFG_INTEGRITY_ECC:
	case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
		edac_mode = EDAC_SECDED;
		break;
	default:
		edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n");
		edac_mode = EDAC_UNKNOWN;
		break;
	}

	i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);

	/* Many BIOSes don't clear error flags on boot, so do this
	 * here, or we get "phantom" errors occurring at module-load
	 * time. */
	pci_write_bits32(pdev, I82443BXGX_EAP,
			(I82443BXGX_EAP_OFFSET_SBE |
				I82443BXGX_EAP_OFFSET_MBE),
			(I82443BXGX_EAP_OFFSET_SBE |
				I82443BXGX_EAP_OFFSET_MBE));

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = I82443_REVISION;
	mci->ctl_name = "I82443BXGX";
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i82443bxgx_edacmc_check;
	mci->ctl_page_to_phys = NULL;

	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* allocating generic PCI control info */
	i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i82443bxgx_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	edac_dbg(3, "MC: success\n");
	return 0;

fail:
	edac_mc_free(mci);
	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
				      const struct pci_device_id *ent)
{
	int rc;

	edac_dbg(0, "MC:\n");

	/* don't need to call pci_enable_device() */
	rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);

	if (mci_pdev == NULL)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	edac_dbg(0, "\n");

	if (i82443bxgx_pci)
		edac_pci_release_generic_ctl(i82443bxgx_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id i82443bxgx_pci_tbl[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
	{0,}			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);

static struct pci_driver i82443bxgx_edacmc_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82443bxgx_edacmc_init_one,
	.remove = i82443bxgx_edacmc_remove_one,
	.id_table = i82443bxgx_pci_tbl,
};

static int __init i82443bxgx_edacmc_init(void)
{
	int pci_rc;
       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
	if (pci_rc < 0)
		goto fail0;

	if (mci_pdev == NULL) {
		const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
		int i = 0;
		i82443bxgx_registered = 0;

		while (mci_pdev == NULL && id->vendor != 0) {
			mci_pdev = pci_get_device(id->vendor,
					id->device, NULL);
			i++;
			id = &i82443bxgx_pci_tbl[i];
		}
		if (!mci_pdev) {
			edac_dbg(0, "i82443bxgx pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);

		if (pci_rc < 0) {
			edac_dbg(0, "i82443bxgx init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i82443bxgx_edacmc_driver);

fail0:
	pci_dev_put(mci_pdev);
	return pci_rc;
}

static void __exit i82443bxgx_edacmc_exit(void)
{
	pci_unregister_driver(&i82443bxgx_edacmc_driver);

	if (!i82443bxgx_registered)
		i82443bxgx_edacmc_remove_one(mci_pdev);

	pci_dev_put(mci_pdev);
}

module_init(i82443bxgx_edacmc_init);
module_exit(i82443bxgx_edacmc_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
5a2c675c TS	1	/*
	2	* Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
	3	* module (C) 2006 Tim Small
	4	*
	5	* This file may be distributed under the terms of the GNU General
	6	* Public License.
	7	*
	8	* Written by Tim Small <tim@buttersideup.com>, based on work by Linux
	9	* Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
	10	* others.
	11	*
	12	* 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
	13	*
	14	* Written with reference to 82443BX Host Bridge Datasheet:
084a4fcc	15	* http://download.intel.com/design/chipsets/datashts/29063301.pdf
5a2c675c TS	16	* references to this document given in [].
	17	*
	18	* This module doesn't support the 440LX, but it may be possible to
	19	* make it do so (the 440LX's register definitions are different, but
	20	* not completely so - I haven't studied them in enough detail to know
	21	* how easy this would be).
	22	*/
	23
	24	#include <linux/module.h>
	25	#include <linux/init.h>
	26
	27	#include <linux/pci.h>
	28	#include <linux/pci_ids.h>
	29
5a2c675c	30
c3c52bce	31	#include <linux/edac.h>
20bcb7a8	32	#include "edac_core.h"
5a2c675c TS	33
	34	#define I82443_REVISION "0.1"
	35
	36	#define EDAC_MOD_STR "i82443bxgx_edac"
	37
5a2c675c TS	38	/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
	39	* Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
	40	* rows" "The 82443BX supports multiple-bit error detection and
	41	* single-bit error correction when ECC mode is enabled and
	42	* single/multi-bit error detection when correction is disabled.
	43	* During writes to the DRAM, the 82443BX generates ECC for the data
	44	* on a QWord basis. Partial QWord writes require a read-modify-write
	45	* cycle when ECC is enabled."
	46	*/
	47
	48	/* "Additionally, the 82443BX ensures that the data is corrected in
	49	* main memory so that accumulation of errors is prevented. Another
	50	* error within the same QWord would result in a double-bit error
	51	* which is unrecoverable. This is known as hardware scrubbing since
	52	* it requires no software intervention to correct the data in memory."
	53	*/
	54
	55	/* [Also see page 100 (section 4.3), "DRAM Interface"]
	56	* [Also see page 112 (section 4.6.1.4), ECC]
	57	*/
	58
	59	#define I82443BXGX_NR_CSROWS 8
	60	#define I82443BXGX_NR_CHANS 1
	61	#define I82443BXGX_NR_DIMMS 4
	62
5a2c675c	63	/* 82443 PCI Device 0 */
11116601 DT	64	#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
	65	* config space offset */
	66	#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
	67	* row is non-ECC */
	68	#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
	69
	70	#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
	71	#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
	72	#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
	73	#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
	74	#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
5a2c675c TS	75
	76	#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
	77
5a2c675c	78	/* 82443 PCI Device 0 */
11116601 DT	79	#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
	80	* config space offset, Error Address
	81	* Pointer Register */
	82	#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
	83	#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
	84	#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
	85
	86	#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
5a2c675c	87	* config space offset. */
11116601 DT	88	#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
11116601 DT	89	#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
5a2c675c	90
11116601	91	#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
5a2c675c	92	* config space offset. */
11116601 DT	93	#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
	94	#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
	95	#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
	96	#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
5a2c675c	97
11116601 DT	98	#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
	99	* config space offset. */
	100	#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
	101	#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
5a2c675c	102	#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
11116601	103	#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
5a2c675c	104
11116601 DT	105	#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
11116601 DT	106	* config space offset. */
5a2c675c TS	107
	108	/* FIXME - don't poll when ECC disabled? */
	109
5a2c675c TS	110	struct i82443bxgx_edacmc_error_info {
	111	u32 eap;
	112	};
	113
456a2f95 DJ	114	static struct edac_pci_ctl_info *i82443bxgx_pci;
456a2f95 DJ	115
53a2fe58 VB	116	static struct pci_dev mci_pdev; / init dev: in case that AGP code has
	117	* already registered driver
	118	*/
	119
	120	static int i82443bxgx_registered = 1;
	121
11116601	122	static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
052dfb45 DT	123	struct i82443bxgx_edacmc_error_info
052dfb45 DT	124	*info)
5a2c675c TS	125	{
5a2c675c TS	126	struct pci_dev *pdev;
fd687502	127	pdev = to_pci_dev(mci->pdev);
5a2c675c TS	128	pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
	129	if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
	130	/* Clear error to allow next error to be reported [p.61] */
	131	pci_write_bits32(pdev, I82443BXGX_EAP,
	132	I82443BXGX_EAP_OFFSET_SBE,
	133	I82443BXGX_EAP_OFFSET_SBE);
	134
	135	if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
	136	/* Clear error to allow next error to be reported [p.61] */
	137	pci_write_bits32(pdev, I82443BXGX_EAP,
	138	I82443BXGX_EAP_OFFSET_MBE,
	139	I82443BXGX_EAP_OFFSET_MBE);
	140	}
	141
11116601 DT	142	static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
	143	struct
	144	i82443bxgx_edacmc_error_info
	145	*info, int handle_errors)
5a2c675c TS	146	{
	147	int error_found = 0;
	148	u32 eapaddr, page, pageoffset;
	149
	150	/* bits 30:12 hold the 4kb block in which the error occurred
	151	* [p.61] */
	152	eapaddr = (info->eap & 0xfffff000);
	153	page = eapaddr >> PAGE_SHIFT;
	154	pageoffset = eapaddr - (page << PAGE_SHIFT);
	155
11116601	156	if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
5a2c675c TS	157	error_found = 1;
5a2c675c TS	158	if (handle_errors)
9eb07a7f	159	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
40f562b1 MCC	160	page, pageoffset, 0,
40f562b1 MCC	161	edac_mc_find_csrow_by_page(mci, page),
03f7eae8	162	0, -1, mci->ctl_name, "");
5a2c675c TS	163	}
5a2c675c TS	164
11116601	165	if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
5a2c675c TS	166	error_found = 1;
5a2c675c TS	167	if (handle_errors)
9eb07a7f	168	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
40f562b1 MCC	169	page, pageoffset, 0,
40f562b1 MCC	170	edac_mc_find_csrow_by_page(mci, page),
03f7eae8	171	0, -1, mci->ctl_name, "");
5a2c675c TS	172	}
	173
	174	return error_found;
	175	}
	176
5a2c675c TS	177	static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
	178	{
	179	struct i82443bxgx_edacmc_error_info info;
	180
956b9ba1	181	edac_dbg(1, "MC%d\n", mci->mc_idx);
5a2c675c TS	182	i82443bxgx_edacmc_get_error_info(mci, &info);
	183	i82443bxgx_edacmc_process_error_info(mci, &info, 1);
	184	}
	185
5a2c675c	186	static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
052dfb45 DT	187	struct pci_dev *pdev,
	188	enum edac_type edac_mode,
	189	enum mem_type mtype)
5a2c675c TS	190	{
5a2c675c TS	191	struct csrow_info *csrow;
084a4fcc	192	struct dimm_info *dimm;
5a2c675c TS	193	int index;
	194	u8 drbar, dramc;
	195	u32 row_base, row_high_limit, row_high_limit_last;
	196
	197	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
	198	row_high_limit_last = 0;
	199	for (index = 0; index < mci->nr_csrows; index++) {
de3910eb MCC	200	csrow = mci->csrows[index];
de3910eb MCC	201	dimm = csrow->channels[0]->dimm;
084a4fcc	202
5a2c675c	203	pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
956b9ba1 JP	204	edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n",
956b9ba1 JP	205	mci->mc_idx, index, drbar);
5a2c675c TS	206	row_high_limit = ((u32) drbar << 23);
5a2c675c TS	207	/* find the DRAM Chip Select Base address and mask */
956b9ba1 JP	208	edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n",
	209	mci->mc_idx, index, row_high_limit,
	210	row_high_limit_last);
5a2c675c TS	211
	212	/* 440GX goes to 2GB, represented with a DRB of 0. */
	213	if (row_high_limit_last && !row_high_limit)
	214	row_high_limit = 1UL << 31;
	215
	216	/* This row is empty [p.49] */
	217	if (row_high_limit == row_high_limit_last)
	218	continue;
	219	row_base = row_high_limit_last;
	220	csrow->first_page = row_base >> PAGE_SHIFT;
	221	csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
a895bf8b	222	dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
5a2c675c	223	/* EAP reports in 4kilobyte granularity [61] */
084a4fcc MCC	224	dimm->grain = 1 << 12;
084a4fcc MCC	225	dimm->mtype = mtype;
5a2c675c	226	/* I don't think 440BX can tell you device type? FIXME? */
084a4fcc	227	dimm->dtype = DEV_UNKNOWN;
5a2c675c	228	/* Mode is global to all rows on 440BX */
084a4fcc	229	dimm->edac_mode = edac_mode;
5a2c675c TS	230	row_high_limit_last = row_high_limit;
	231	}
	232	}
	233
11116601	234	static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
5a2c675c TS	235	{
5a2c675c TS	236	struct mem_ctl_info *mci;
40f562b1	237	struct edac_mc_layer layers[2];
5a2c675c TS	238	u8 dramc;
	239	u32 nbxcfg, ecc_mode;
	240	enum mem_type mtype;
	241	enum edac_type edac_mode;
	242
956b9ba1	243	edac_dbg(0, "MC:\n");
5a2c675c TS	244
5a2c675c TS	245	/* Something is really hosed if PCI config space reads from
052dfb45 DT	246	* the MC aren't working.
052dfb45 DT	247	*/
5a2c675c TS	248	if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
	249	return -EIO;
	250
40f562b1 MCC	251	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	252	layers[0].size = I82443BXGX_NR_CSROWS;
	253	layers[0].is_virt_csrow = true;
	254	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	255	layers[1].size = I82443BXGX_NR_CHANS;
	256	layers[1].is_virt_csrow = false;
ca0907b9	257	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
5a2c675c TS	258	if (mci == NULL)
	259	return -ENOMEM;
	260
956b9ba1	261	edac_dbg(0, "MC: mci = %p\n", mci);
fd687502	262	mci->pdev = &pdev->dev;
5a2c675c TS	263	mci->mtype_cap = MEM_FLAG_EDO \| MEM_FLAG_SDR \| MEM_FLAG_RDR;
	264	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
	265	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
	266	switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) \| BIT(1))) {
11116601	267	case I82443BXGX_DRAMC_DRAM_IS_EDO:
5a2c675c TS	268	mtype = MEM_EDO;
	269	break;
	270	case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
	271	mtype = MEM_SDR;
	272	break;
	273	case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
	274	mtype = MEM_RDR;
	275	break;
	276	default:
956b9ba1	277	edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n");
5a2c675c TS	278	mtype = -MEM_UNKNOWN;
	279	}
	280
	281	if ((mtype == MEM_SDR) \|\| (mtype == MEM_RDR))
	282	mci->edac_cap = mci->edac_ctl_cap;
	283	else
	284	mci->edac_cap = EDAC_FLAG_NONE;
	285
	286	mci->scrub_cap = SCRUB_FLAG_HW_SRC;
	287	pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
	288	ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
052dfb45	289	(BIT(0) \| BIT(1)));
5a2c675c TS	290
5a2c675c TS	291	mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
052dfb45	292	? SCRUB_HW_SRC : SCRUB_NONE;
5a2c675c	293
11116601	294	switch (ecc_mode) {
5a2c675c TS	295	case I82443BXGX_NBXCFG_INTEGRITY_NONE:
	296	edac_mode = EDAC_NONE;
	297	break;
	298	case I82443BXGX_NBXCFG_INTEGRITY_EC:
	299	edac_mode = EDAC_EC;
	300	break;
	301	case I82443BXGX_NBXCFG_INTEGRITY_ECC:
	302	case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
	303	edac_mode = EDAC_SECDED;
	304	break;
	305	default:
956b9ba1	306	edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n");
5a2c675c TS	307	edac_mode = EDAC_UNKNOWN;
	308	break;
	309	}
	310
	311	i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
	312
	313	/* Many BIOSes don't clear error flags on boot, so do this
25985edc	314	* here, or we get "phantom" errors occurring at module-load
5a2c675c TS	315	* time. */
5a2c675c TS	316	pci_write_bits32(pdev, I82443BXGX_EAP,
052dfb45 DT	317	(I82443BXGX_EAP_OFFSET_SBE \|
	318	I82443BXGX_EAP_OFFSET_MBE),
	319	(I82443BXGX_EAP_OFFSET_SBE \|
	320	I82443BXGX_EAP_OFFSET_MBE));
5a2c675c TS	321
	322	mci->mod_name = EDAC_MOD_STR;
	323	mci->mod_ver = I82443_REVISION;
	324	mci->ctl_name = "I82443BXGX";
c4192705	325	mci->dev_name = pci_name(pdev);
5a2c675c TS	326	mci->edac_check = i82443bxgx_edacmc_check;
	327	mci->ctl_page_to_phys = NULL;
	328
b8f6f975	329	if (edac_mc_add_mc(mci)) {
956b9ba1	330	edac_dbg(3, "failed edac_mc_add_mc()\n");
5a2c675c TS	331	goto fail;
	332	}
	333
456a2f95 DJ	334	/* allocating generic PCI control info */
	335	i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	336	if (!i82443bxgx_pci) {
	337	printk(KERN_WARNING
	338	"%s(): Unable to create PCI control\n",
	339	__func__);
	340	printk(KERN_WARNING
	341	"%s(): PCI error report via EDAC not setup\n",
	342	__func__);
	343	}
	344
956b9ba1	345	edac_dbg(3, "MC: success\n");
5a2c675c TS	346	return 0;
5a2c675c TS	347
052dfb45	348	fail:
5a2c675c TS	349	edac_mc_free(mci);
	350	return -ENODEV;
	351	}
11116601	352
5a2c675c	353	/* returns count (>= 0), or negative on error */
9b3c6e85 GKH	354	static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
9b3c6e85 GKH	355	const struct pci_device_id *ent)
5a2c675c	356	{
53a2fe58 VB	357	int rc;
53a2fe58 VB	358
956b9ba1	359	edac_dbg(0, "MC:\n");
5a2c675c	360
ee6583f6	361	/* don't need to call pci_enable_device() */
53a2fe58 VB	362	rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
	363
	364	if (mci_pdev == NULL)
	365	mci_pdev = pci_dev_get(pdev);
	366
	367	return rc;
5a2c675c TS	368	}
5a2c675c TS	369
9b3c6e85	370	static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
5a2c675c TS	371	{
	372	struct mem_ctl_info *mci;
	373
956b9ba1	374	edac_dbg(0, "\n");
5a2c675c	375
456a2f95 DJ	376	if (i82443bxgx_pci)
	377	edac_pci_release_generic_ctl(i82443bxgx_pci);
	378
11116601	379	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
5a2c675c TS	380	return;
	381
	382	edac_mc_free(mci);
	383	}
5a2c675c	384
ba935f40	385	static const struct pci_device_id i82443bxgx_pci_tbl[] = {
5a2c675c TS	386	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
	387	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
	388	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
	389	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
	390	{0,} /* 0 terminated list. */
	391	};
	392
	393	MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
	394
5a2c675c TS	395	static struct pci_driver i82443bxgx_edacmc_driver = {
	396	.name = EDAC_MOD_STR,
	397	.probe = i82443bxgx_edacmc_init_one,
9b3c6e85	398	.remove = i82443bxgx_edacmc_remove_one,
5a2c675c TS	399	.id_table = i82443bxgx_pci_tbl,
	400	};
	401
5a2c675c TS	402	static int __init i82443bxgx_edacmc_init(void)
5a2c675c TS	403	{
53a2fe58	404	int pci_rc;
c3c52bce HM	405	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	406	opstate_init();
	407
53a2fe58 VB	408	pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
	409	if (pci_rc < 0)
	410	goto fail0;
	411
	412	if (mci_pdev == NULL) {
	413	const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
	414	int i = 0;
	415	i82443bxgx_registered = 0;
	416
	417	while (mci_pdev == NULL && id->vendor != 0) {
	418	mci_pdev = pci_get_device(id->vendor,
	419	id->device, NULL);
	420	i++;
	421	id = &i82443bxgx_pci_tbl[i];
	422	}
	423	if (!mci_pdev) {
956b9ba1	424	edac_dbg(0, "i82443bxgx pci_get_device fail\n");
53a2fe58 VB	425	pci_rc = -ENODEV;
	426	goto fail1;
	427	}
	428
	429	pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
	430
	431	if (pci_rc < 0) {
956b9ba1	432	edac_dbg(0, "i82443bxgx init fail\n");
53a2fe58 VB	433	pci_rc = -ENODEV;
	434	goto fail1;
	435	}
	436	}
	437
	438	return 0;
	439
	440	fail1:
	441	pci_unregister_driver(&i82443bxgx_edacmc_driver);
	442
	443	fail0:
72601945	444	pci_dev_put(mci_pdev);
53a2fe58	445	return pci_rc;
5a2c675c TS	446	}
5a2c675c TS	447
5a2c675c TS	448	static void __exit i82443bxgx_edacmc_exit(void)
	449	{
	450	pci_unregister_driver(&i82443bxgx_edacmc_driver);
53a2fe58 VB	451
	452	if (!i82443bxgx_registered)
	453	i82443bxgx_edacmc_remove_one(mci_pdev);
	454
0a98babd	455	pci_dev_put(mci_pdev);
5a2c675c TS	456	}
5a2c675c TS	457
5a2c675c TS	458	module_init(i82443bxgx_edacmc_init);
	459	module_exit(i82443bxgx_edacmc_exit);
	460
5a2c675c TS	461	MODULE_LICENSE("GPL");
	462	MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
	463	MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
c3c52bce HM	464
	465	module_param(edac_op_state, int, 0444);
	466	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");