Linux 3.9-rc4
[linux-2.6-block.git] / drivers / edac / edac_mc_sysfs.c
CommitLineData
7c9281d7
DT
1/*
2 * edac_mc kernel module
42a8e397
DT
3 * (C) 2005-2007 Linux Networx (http://lnxi.com)
4 *
7c9281d7
DT
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
42a8e397 8 * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
7c9281d7 9 *
e7100478 10 * (c) 2012-2013 - Mauro Carvalho Chehab <mchehab@redhat.com>
7a623c03
MCC
11 * The entire API were re-written, and ported to use struct device
12 *
7c9281d7
DT
13 */
14
7c9281d7 15#include <linux/ctype.h>
5a0e3ad6 16#include <linux/slab.h>
30e1f7a8 17#include <linux/edac.h>
8096cfaf 18#include <linux/bug.h>
7a623c03 19#include <linux/pm_runtime.h>
452a6bf9 20#include <linux/uaccess.h>
7c9281d7 21
20bcb7a8 22#include "edac_core.h"
7c9281d7
DT
23#include "edac_module.h"
24
25/* MC EDAC Controls, setable by module parameter, and sysfs */
4de78c68
DJ
26static int edac_mc_log_ue = 1;
27static int edac_mc_log_ce = 1;
f044091c 28static int edac_mc_panic_on_ue;
4de78c68 29static int edac_mc_poll_msec = 1000;
7c9281d7
DT
30
31/* Getter functions for above */
4de78c68 32int edac_mc_get_log_ue(void)
7c9281d7 33{
4de78c68 34 return edac_mc_log_ue;
7c9281d7
DT
35}
36
4de78c68 37int edac_mc_get_log_ce(void)
7c9281d7 38{
4de78c68 39 return edac_mc_log_ce;
7c9281d7
DT
40}
41
4de78c68 42int edac_mc_get_panic_on_ue(void)
7c9281d7 43{
4de78c68 44 return edac_mc_panic_on_ue;
7c9281d7
DT
45}
46
81d87cb1
DJ
47/* this is temporary */
48int edac_mc_get_poll_msec(void)
49{
4de78c68 50 return edac_mc_poll_msec;
7c9281d7
DT
51}
52
096846e2
AJ
53static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
54{
55 long l;
56 int ret;
57
58 if (!val)
59 return -EINVAL;
60
61 ret = strict_strtol(val, 0, &l);
62 if (ret == -EINVAL || ((int)l != l))
63 return -EINVAL;
64 *((int *)kp->arg) = l;
65
66 /* notify edac_mc engine to reset the poll period */
67 edac_mc_reset_delay_period(l);
68
69 return 0;
70}
71
7c9281d7 72/* Parameter declarations for above */
4de78c68
DJ
73module_param(edac_mc_panic_on_ue, int, 0644);
74MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
75module_param(edac_mc_log_ue, int, 0644);
76MODULE_PARM_DESC(edac_mc_log_ue,
079708b9 77 "Log uncorrectable error to console: 0=off 1=on");
4de78c68
DJ
78module_param(edac_mc_log_ce, int, 0644);
79MODULE_PARM_DESC(edac_mc_log_ce,
079708b9 80 "Log correctable error to console: 0=off 1=on");
096846e2
AJ
81module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
82 &edac_mc_poll_msec, 0644);
4de78c68 83MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
7c9281d7 84
de3910eb 85static struct device *mci_pdev;
7a623c03 86
7c9281d7
DT
87/*
88 * various constants for Memory Controllers
89 */
90static const char *mem_types[] = {
91 [MEM_EMPTY] = "Empty",
92 [MEM_RESERVED] = "Reserved",
93 [MEM_UNKNOWN] = "Unknown",
94 [MEM_FPM] = "FPM",
95 [MEM_EDO] = "EDO",
96 [MEM_BEDO] = "BEDO",
97 [MEM_SDR] = "Unbuffered-SDR",
98 [MEM_RDR] = "Registered-SDR",
99 [MEM_DDR] = "Unbuffered-DDR",
100 [MEM_RDDR] = "Registered-DDR",
1a9b85e6
DJ
101 [MEM_RMBS] = "RMBS",
102 [MEM_DDR2] = "Unbuffered-DDR2",
103 [MEM_FB_DDR2] = "FullyBuffered-DDR2",
1d5f726c 104 [MEM_RDDR2] = "Registered-DDR2",
b1cfebc9
YS
105 [MEM_XDR] = "XDR",
106 [MEM_DDR3] = "Unbuffered-DDR3",
107 [MEM_RDDR3] = "Registered-DDR3"
7c9281d7
DT
108};
109
110static const char *dev_types[] = {
111 [DEV_UNKNOWN] = "Unknown",
112 [DEV_X1] = "x1",
113 [DEV_X2] = "x2",
114 [DEV_X4] = "x4",
115 [DEV_X8] = "x8",
116 [DEV_X16] = "x16",
117 [DEV_X32] = "x32",
118 [DEV_X64] = "x64"
119};
120
121static const char *edac_caps[] = {
122 [EDAC_UNKNOWN] = "Unknown",
123 [EDAC_NONE] = "None",
124 [EDAC_RESERVED] = "Reserved",
125 [EDAC_PARITY] = "PARITY",
126 [EDAC_EC] = "EC",
127 [EDAC_SECDED] = "SECDED",
128 [EDAC_S2ECD2ED] = "S2ECD2ED",
129 [EDAC_S4ECD4ED] = "S4ECD4ED",
130 [EDAC_S8ECD8ED] = "S8ECD8ED",
131 [EDAC_S16ECD16ED] = "S16ECD16ED"
132};
133
19974710 134#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
135/*
136 * EDAC sysfs CSROW data structures and methods
137 */
138
139#define to_csrow(k) container_of(k, struct csrow_info, dev)
140
141/*
142 * We need it to avoid namespace conflicts between the legacy API
143 * and the per-dimm/per-rank one
7c9281d7 144 */
7a623c03 145#define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
fbe2d361 146 static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
7a623c03
MCC
147
148struct dev_ch_attribute {
149 struct device_attribute attr;
150 int channel;
151};
152
153#define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
154 struct dev_ch_attribute dev_attr_legacy_##_name = \
155 { __ATTR(_name, _mode, _show, _store), (_var) }
156
157#define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
7c9281d7
DT
158
159/* Set of more default csrow<id> attribute show/store functions */
7a623c03
MCC
160static ssize_t csrow_ue_count_show(struct device *dev,
161 struct device_attribute *mattr, char *data)
7c9281d7 162{
7a623c03
MCC
163 struct csrow_info *csrow = to_csrow(dev);
164
079708b9 165 return sprintf(data, "%u\n", csrow->ue_count);
7c9281d7
DT
166}
167
7a623c03
MCC
168static ssize_t csrow_ce_count_show(struct device *dev,
169 struct device_attribute *mattr, char *data)
7c9281d7 170{
7a623c03
MCC
171 struct csrow_info *csrow = to_csrow(dev);
172
079708b9 173 return sprintf(data, "%u\n", csrow->ce_count);
7c9281d7
DT
174}
175
7a623c03
MCC
176static ssize_t csrow_size_show(struct device *dev,
177 struct device_attribute *mattr, char *data)
7c9281d7 178{
7a623c03 179 struct csrow_info *csrow = to_csrow(dev);
a895bf8b
MCC
180 int i;
181 u32 nr_pages = 0;
182
183 for (i = 0; i < csrow->nr_channels; i++)
de3910eb 184 nr_pages += csrow->channels[i]->dimm->nr_pages;
a895bf8b 185 return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
7c9281d7
DT
186}
187
7a623c03
MCC
188static ssize_t csrow_mem_type_show(struct device *dev,
189 struct device_attribute *mattr, char *data)
7c9281d7 190{
7a623c03
MCC
191 struct csrow_info *csrow = to_csrow(dev);
192
de3910eb 193 return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
7c9281d7
DT
194}
195
7a623c03
MCC
196static ssize_t csrow_dev_type_show(struct device *dev,
197 struct device_attribute *mattr, char *data)
7c9281d7 198{
7a623c03
MCC
199 struct csrow_info *csrow = to_csrow(dev);
200
de3910eb 201 return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
7c9281d7
DT
202}
203
7a623c03
MCC
204static ssize_t csrow_edac_mode_show(struct device *dev,
205 struct device_attribute *mattr,
206 char *data)
7c9281d7 207{
7a623c03
MCC
208 struct csrow_info *csrow = to_csrow(dev);
209
de3910eb 210 return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
7c9281d7
DT
211}
212
213/* show/store functions for DIMM Label attributes */
7a623c03
MCC
214static ssize_t channel_dimm_label_show(struct device *dev,
215 struct device_attribute *mattr,
216 char *data)
7c9281d7 217{
7a623c03
MCC
218 struct csrow_info *csrow = to_csrow(dev);
219 unsigned chan = to_channel(mattr);
de3910eb 220 struct rank_info *rank = csrow->channels[chan];
7a623c03 221
124682c7 222 /* if field has not been initialized, there is nothing to send */
7a623c03 223 if (!rank->dimm->label[0])
124682c7
AJ
224 return 0;
225
226 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
7a623c03 227 rank->dimm->label);
7c9281d7
DT
228}
229
7a623c03
MCC
230static ssize_t channel_dimm_label_store(struct device *dev,
231 struct device_attribute *mattr,
232 const char *data, size_t count)
7c9281d7 233{
7a623c03
MCC
234 struct csrow_info *csrow = to_csrow(dev);
235 unsigned chan = to_channel(mattr);
de3910eb 236 struct rank_info *rank = csrow->channels[chan];
7a623c03 237
7c9281d7
DT
238 ssize_t max_size = 0;
239
079708b9 240 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
7a623c03
MCC
241 strncpy(rank->dimm->label, data, max_size);
242 rank->dimm->label[max_size] = '\0';
7c9281d7
DT
243
244 return max_size;
245}
246
247/* show function for dynamic chX_ce_count attribute */
7a623c03
MCC
248static ssize_t channel_ce_count_show(struct device *dev,
249 struct device_attribute *mattr, char *data)
7c9281d7 250{
7a623c03
MCC
251 struct csrow_info *csrow = to_csrow(dev);
252 unsigned chan = to_channel(mattr);
de3910eb 253 struct rank_info *rank = csrow->channels[chan];
7a623c03
MCC
254
255 return sprintf(data, "%u\n", rank->ce_count);
7c9281d7
DT
256}
257
7a623c03
MCC
258/* cwrow<id>/attribute files */
259DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
260DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
261DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
262DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
263DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
264DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
7c9281d7 265
7a623c03
MCC
266/* default attributes of the CSROW<id> object */
267static struct attribute *csrow_attrs[] = {
268 &dev_attr_legacy_dev_type.attr,
269 &dev_attr_legacy_mem_type.attr,
270 &dev_attr_legacy_edac_mode.attr,
271 &dev_attr_legacy_size_mb.attr,
272 &dev_attr_legacy_ue_count.attr,
273 &dev_attr_legacy_ce_count.attr,
274 NULL,
275};
7c9281d7 276
7a623c03
MCC
277static struct attribute_group csrow_attr_grp = {
278 .attrs = csrow_attrs,
279};
7c9281d7 280
7a623c03
MCC
281static const struct attribute_group *csrow_attr_groups[] = {
282 &csrow_attr_grp,
283 NULL
284};
7c9281d7 285
de3910eb 286static void csrow_attr_release(struct device *dev)
7c9281d7 287{
de3910eb
MCC
288 struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
289
956b9ba1 290 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 291 kfree(csrow);
7c9281d7
DT
292}
293
7a623c03
MCC
294static struct device_type csrow_attr_type = {
295 .groups = csrow_attr_groups,
296 .release = csrow_attr_release,
7c9281d7
DT
297};
298
7a623c03
MCC
299/*
300 * possible dynamic channel DIMM Label attribute files
301 *
302 */
7c9281d7 303
7a623c03 304#define EDAC_NR_CHANNELS 6
7c9281d7 305
7a623c03 306DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 307 channel_dimm_label_show, channel_dimm_label_store, 0);
7a623c03 308DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 309 channel_dimm_label_show, channel_dimm_label_store, 1);
7a623c03 310DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 311 channel_dimm_label_show, channel_dimm_label_store, 2);
7a623c03 312DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 313 channel_dimm_label_show, channel_dimm_label_store, 3);
7a623c03 314DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 315 channel_dimm_label_show, channel_dimm_label_store, 4);
7a623c03 316DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 317 channel_dimm_label_show, channel_dimm_label_store, 5);
7c9281d7
DT
318
319/* Total possible dynamic DIMM Label attribute file table */
7a623c03
MCC
320static struct device_attribute *dynamic_csrow_dimm_attr[] = {
321 &dev_attr_legacy_ch0_dimm_label.attr,
322 &dev_attr_legacy_ch1_dimm_label.attr,
323 &dev_attr_legacy_ch2_dimm_label.attr,
324 &dev_attr_legacy_ch3_dimm_label.attr,
325 &dev_attr_legacy_ch4_dimm_label.attr,
326 &dev_attr_legacy_ch5_dimm_label.attr
7c9281d7
DT
327};
328
329/* possible dynamic channel ce_count attribute files */
7a623c03
MCC
330DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR,
331 channel_ce_count_show, NULL, 0);
332DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR,
333 channel_ce_count_show, NULL, 1);
334DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR,
335 channel_ce_count_show, NULL, 2);
336DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR,
337 channel_ce_count_show, NULL, 3);
338DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR,
339 channel_ce_count_show, NULL, 4);
340DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR,
341 channel_ce_count_show, NULL, 5);
7c9281d7
DT
342
343/* Total possible dynamic ce_count attribute file table */
7a623c03
MCC
344static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
345 &dev_attr_legacy_ch0_ce_count.attr,
346 &dev_attr_legacy_ch1_ce_count.attr,
347 &dev_attr_legacy_ch2_ce_count.attr,
348 &dev_attr_legacy_ch3_ce_count.attr,
349 &dev_attr_legacy_ch4_ce_count.attr,
350 &dev_attr_legacy_ch5_ce_count.attr
7c9281d7
DT
351};
352
e39f4ea9
MCC
353static inline int nr_pages_per_csrow(struct csrow_info *csrow)
354{
355 int chan, nr_pages = 0;
356
357 for (chan = 0; chan < csrow->nr_channels; chan++)
de3910eb 358 nr_pages += csrow->channels[chan]->dimm->nr_pages;
e39f4ea9
MCC
359
360 return nr_pages;
361}
362
7a623c03
MCC
363/* Create a CSROW object under specifed edac_mc_device */
364static int edac_create_csrow_object(struct mem_ctl_info *mci,
365 struct csrow_info *csrow, int index)
7c9281d7 366{
7a623c03 367 int err, chan;
7c9281d7 368
7a623c03
MCC
369 if (csrow->nr_channels >= EDAC_NR_CHANNELS)
370 return -ENODEV;
7c9281d7 371
7a623c03
MCC
372 csrow->dev.type = &csrow_attr_type;
373 csrow->dev.bus = &mci->bus;
374 device_initialize(&csrow->dev);
375 csrow->dev.parent = &mci->dev;
921a6899 376 csrow->mci = mci;
7a623c03
MCC
377 dev_set_name(&csrow->dev, "csrow%d", index);
378 dev_set_drvdata(&csrow->dev, csrow);
7c9281d7 379
956b9ba1
JP
380 edac_dbg(0, "creating (virtual) csrow node %s\n",
381 dev_name(&csrow->dev));
7c9281d7 382
7a623c03
MCC
383 err = device_add(&csrow->dev);
384 if (err < 0)
385 return err;
7c9281d7 386
7a623c03 387 for (chan = 0; chan < csrow->nr_channels; chan++) {
e39f4ea9 388 /* Only expose populated DIMMs */
de3910eb 389 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 390 continue;
7a623c03
MCC
391 err = device_create_file(&csrow->dev,
392 dynamic_csrow_dimm_attr[chan]);
393 if (err < 0)
394 goto error;
395 err = device_create_file(&csrow->dev,
396 dynamic_csrow_ce_count_attr[chan]);
397 if (err < 0) {
398 device_remove_file(&csrow->dev,
399 dynamic_csrow_dimm_attr[chan]);
400 goto error;
401 }
402 }
8096cfaf 403
7a623c03 404 return 0;
8096cfaf 405
7a623c03
MCC
406error:
407 for (--chan; chan >= 0; chan--) {
408 device_remove_file(&csrow->dev,
409 dynamic_csrow_dimm_attr[chan]);
410 device_remove_file(&csrow->dev,
411 dynamic_csrow_ce_count_attr[chan]);
412 }
413 put_device(&csrow->dev);
7c9281d7 414
7a623c03
MCC
415 return err;
416}
7c9281d7
DT
417
418/* Create a CSROW object under specifed edac_mc_device */
7a623c03 419static int edac_create_csrow_objects(struct mem_ctl_info *mci)
7c9281d7 420{
7a623c03
MCC
421 int err, i, chan;
422 struct csrow_info *csrow;
7c9281d7 423
7a623c03 424 for (i = 0; i < mci->nr_csrows; i++) {
de3910eb 425 csrow = mci->csrows[i];
e39f4ea9
MCC
426 if (!nr_pages_per_csrow(csrow))
427 continue;
de3910eb 428 err = edac_create_csrow_object(mci, mci->csrows[i], i);
3d958823
MCC
429 if (err < 0) {
430 edac_dbg(1,
431 "failure: create csrow objects for csrow %d\n",
432 i);
7a623c03 433 goto error;
3d958823 434 }
7a623c03
MCC
435 }
436 return 0;
8096cfaf 437
7a623c03
MCC
438error:
439 for (--i; i >= 0; i--) {
de3910eb 440 csrow = mci->csrows[i];
e39f4ea9
MCC
441 if (!nr_pages_per_csrow(csrow))
442 continue;
7a623c03 443 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 444 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 445 continue;
7a623c03
MCC
446 device_remove_file(&csrow->dev,
447 dynamic_csrow_dimm_attr[chan]);
448 device_remove_file(&csrow->dev,
449 dynamic_csrow_ce_count_attr[chan]);
450 }
de3910eb 451 put_device(&mci->csrows[i]->dev);
8096cfaf 452 }
7c9281d7 453
7a623c03
MCC
454 return err;
455}
8096cfaf 456
7a623c03
MCC
457static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
458{
459 int i, chan;
460 struct csrow_info *csrow;
8096cfaf 461
7a623c03 462 for (i = mci->nr_csrows - 1; i >= 0; i--) {
de3910eb 463 csrow = mci->csrows[i];
e39f4ea9
MCC
464 if (!nr_pages_per_csrow(csrow))
465 continue;
7a623c03 466 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 467 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 468 continue;
956b9ba1
JP
469 edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
470 i, chan);
7a623c03
MCC
471 device_remove_file(&csrow->dev,
472 dynamic_csrow_dimm_attr[chan]);
473 device_remove_file(&csrow->dev,
474 dynamic_csrow_ce_count_attr[chan]);
7c9281d7 475 }
44d22e24 476 device_unregister(&mci->csrows[i]->dev);
7c9281d7 477 }
7c9281d7 478}
19974710
MCC
479#endif
480
481/*
482 * Per-dimm (or per-rank) devices
483 */
484
485#define to_dimm(k) container_of(k, struct dimm_info, dev)
486
487/* show/store functions for DIMM Label attributes */
488static ssize_t dimmdev_location_show(struct device *dev,
489 struct device_attribute *mattr, char *data)
490{
491 struct dimm_info *dimm = to_dimm(dev);
19974710 492
6e84d359 493 return edac_dimm_info_location(dimm, data, PAGE_SIZE);
19974710
MCC
494}
495
496static ssize_t dimmdev_label_show(struct device *dev,
497 struct device_attribute *mattr, char *data)
498{
499 struct dimm_info *dimm = to_dimm(dev);
500
501 /* if field has not been initialized, there is nothing to send */
502 if (!dimm->label[0])
503 return 0;
504
505 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
506}
507
508static ssize_t dimmdev_label_store(struct device *dev,
509 struct device_attribute *mattr,
510 const char *data,
511 size_t count)
512{
513 struct dimm_info *dimm = to_dimm(dev);
514
515 ssize_t max_size = 0;
516
517 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
518 strncpy(dimm->label, data, max_size);
519 dimm->label[max_size] = '\0';
520
521 return max_size;
522}
523
524static ssize_t dimmdev_size_show(struct device *dev,
525 struct device_attribute *mattr, char *data)
526{
527 struct dimm_info *dimm = to_dimm(dev);
528
529 return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
530}
531
532static ssize_t dimmdev_mem_type_show(struct device *dev,
533 struct device_attribute *mattr, char *data)
534{
535 struct dimm_info *dimm = to_dimm(dev);
536
537 return sprintf(data, "%s\n", mem_types[dimm->mtype]);
538}
539
540static ssize_t dimmdev_dev_type_show(struct device *dev,
541 struct device_attribute *mattr, char *data)
542{
543 struct dimm_info *dimm = to_dimm(dev);
544
545 return sprintf(data, "%s\n", dev_types[dimm->dtype]);
546}
547
548static ssize_t dimmdev_edac_mode_show(struct device *dev,
549 struct device_attribute *mattr,
550 char *data)
551{
552 struct dimm_info *dimm = to_dimm(dev);
553
554 return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
555}
556
557/* dimm/rank attribute files */
558static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
559 dimmdev_label_show, dimmdev_label_store);
560static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
561static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
562static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
563static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
564static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
565
566/* attributes of the dimm<id>/rank<id> object */
567static struct attribute *dimm_attrs[] = {
568 &dev_attr_dimm_label.attr,
569 &dev_attr_dimm_location.attr,
570 &dev_attr_size.attr,
571 &dev_attr_dimm_mem_type.attr,
572 &dev_attr_dimm_dev_type.attr,
573 &dev_attr_dimm_edac_mode.attr,
574 NULL,
575};
576
577static struct attribute_group dimm_attr_grp = {
578 .attrs = dimm_attrs,
579};
580
581static const struct attribute_group *dimm_attr_groups[] = {
582 &dimm_attr_grp,
583 NULL
584};
585
de3910eb 586static void dimm_attr_release(struct device *dev)
19974710 587{
de3910eb
MCC
588 struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
589
956b9ba1 590 edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
de3910eb 591 kfree(dimm);
19974710
MCC
592}
593
594static struct device_type dimm_attr_type = {
595 .groups = dimm_attr_groups,
596 .release = dimm_attr_release,
597};
598
599/* Create a DIMM object under specifed memory controller device */
600static int edac_create_dimm_object(struct mem_ctl_info *mci,
601 struct dimm_info *dimm,
602 int index)
603{
604 int err;
605 dimm->mci = mci;
606
607 dimm->dev.type = &dimm_attr_type;
608 dimm->dev.bus = &mci->bus;
609 device_initialize(&dimm->dev);
610
611 dimm->dev.parent = &mci->dev;
9713faec 612 if (mci->csbased)
19974710
MCC
613 dev_set_name(&dimm->dev, "rank%d", index);
614 else
615 dev_set_name(&dimm->dev, "dimm%d", index);
616 dev_set_drvdata(&dimm->dev, dimm);
617 pm_runtime_forbid(&mci->dev);
618
619 err = device_add(&dimm->dev);
620
956b9ba1 621 edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
19974710
MCC
622
623 return err;
624}
7c9281d7 625
7a623c03
MCC
626/*
627 * Memory controller device
628 */
629
630#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
7c9281d7 631
7a623c03
MCC
632static ssize_t mci_reset_counters_store(struct device *dev,
633 struct device_attribute *mattr,
079708b9 634 const char *data, size_t count)
7c9281d7 635{
7a623c03
MCC
636 struct mem_ctl_info *mci = to_mci(dev);
637 int cnt, row, chan, i;
5926ff50
MCC
638 mci->ue_mc = 0;
639 mci->ce_mc = 0;
7a623c03
MCC
640 mci->ue_noinfo_count = 0;
641 mci->ce_noinfo_count = 0;
7c9281d7
DT
642
643 for (row = 0; row < mci->nr_csrows; row++) {
de3910eb 644 struct csrow_info *ri = mci->csrows[row];
7c9281d7
DT
645
646 ri->ue_count = 0;
647 ri->ce_count = 0;
648
649 for (chan = 0; chan < ri->nr_channels; chan++)
de3910eb 650 ri->channels[chan]->ce_count = 0;
7c9281d7
DT
651 }
652
7a623c03
MCC
653 cnt = 1;
654 for (i = 0; i < mci->n_layers; i++) {
655 cnt *= mci->layers[i].size;
656 memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
657 memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
658 }
659
7c9281d7
DT
660 mci->start_time = jiffies;
661 return count;
662}
663
39094443
BP
664/* Memory scrubbing interface:
665 *
666 * A MC driver can limit the scrubbing bandwidth based on the CPU type.
667 * Therefore, ->set_sdram_scrub_rate should be made to return the actual
668 * bandwidth that is accepted or 0 when scrubbing is to be disabled.
669 *
670 * Negative value still means that an error has occurred while setting
671 * the scrub rate.
672 */
7a623c03
MCC
673static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
674 struct device_attribute *mattr,
eba042a8 675 const char *data, size_t count)
7c9281d7 676{
7a623c03 677 struct mem_ctl_info *mci = to_mci(dev);
eba042a8 678 unsigned long bandwidth = 0;
39094443 679 int new_bw = 0;
7c9281d7 680
eba042a8
BP
681 if (strict_strtoul(data, 10, &bandwidth) < 0)
682 return -EINVAL;
7c9281d7 683
39094443 684 new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
4949603a
MT
685 if (new_bw < 0) {
686 edac_printk(KERN_WARNING, EDAC_MC,
687 "Error setting scrub rate to: %lu\n", bandwidth);
688 return -EINVAL;
7c9281d7 689 }
39094443 690
4949603a 691 return count;
7c9281d7
DT
692}
693
39094443
BP
694/*
695 * ->get_sdram_scrub_rate() return value semantics same as above.
696 */
7a623c03
MCC
697static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
698 struct device_attribute *mattr,
699 char *data)
7c9281d7 700{
7a623c03 701 struct mem_ctl_info *mci = to_mci(dev);
39094443 702 int bandwidth = 0;
eba042a8 703
39094443
BP
704 bandwidth = mci->get_sdram_scrub_rate(mci);
705 if (bandwidth < 0) {
eba042a8 706 edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
39094443 707 return bandwidth;
7c9281d7 708 }
39094443 709
39094443 710 return sprintf(data, "%d\n", bandwidth);
7c9281d7
DT
711}
712
713/* default attribute files for the MCI object */
7a623c03
MCC
714static ssize_t mci_ue_count_show(struct device *dev,
715 struct device_attribute *mattr,
716 char *data)
7c9281d7 717{
7a623c03
MCC
718 struct mem_ctl_info *mci = to_mci(dev);
719
5926ff50 720 return sprintf(data, "%d\n", mci->ue_mc);
7c9281d7
DT
721}
722
7a623c03
MCC
723static ssize_t mci_ce_count_show(struct device *dev,
724 struct device_attribute *mattr,
725 char *data)
7c9281d7 726{
7a623c03
MCC
727 struct mem_ctl_info *mci = to_mci(dev);
728
5926ff50 729 return sprintf(data, "%d\n", mci->ce_mc);
7c9281d7
DT
730}
731
7a623c03
MCC
732static ssize_t mci_ce_noinfo_show(struct device *dev,
733 struct device_attribute *mattr,
734 char *data)
7c9281d7 735{
7a623c03
MCC
736 struct mem_ctl_info *mci = to_mci(dev);
737
079708b9 738 return sprintf(data, "%d\n", mci->ce_noinfo_count);
7c9281d7
DT
739}
740
7a623c03
MCC
741static ssize_t mci_ue_noinfo_show(struct device *dev,
742 struct device_attribute *mattr,
743 char *data)
7c9281d7 744{
7a623c03
MCC
745 struct mem_ctl_info *mci = to_mci(dev);
746
079708b9 747 return sprintf(data, "%d\n", mci->ue_noinfo_count);
7c9281d7
DT
748}
749
7a623c03
MCC
750static ssize_t mci_seconds_show(struct device *dev,
751 struct device_attribute *mattr,
752 char *data)
7c9281d7 753{
7a623c03
MCC
754 struct mem_ctl_info *mci = to_mci(dev);
755
079708b9 756 return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
7c9281d7
DT
757}
758
7a623c03
MCC
759static ssize_t mci_ctl_name_show(struct device *dev,
760 struct device_attribute *mattr,
761 char *data)
7c9281d7 762{
7a623c03
MCC
763 struct mem_ctl_info *mci = to_mci(dev);
764
079708b9 765 return sprintf(data, "%s\n", mci->ctl_name);
7c9281d7
DT
766}
767
7a623c03
MCC
768static ssize_t mci_size_mb_show(struct device *dev,
769 struct device_attribute *mattr,
770 char *data)
7c9281d7 771{
7a623c03 772 struct mem_ctl_info *mci = to_mci(dev);
a895bf8b 773 int total_pages = 0, csrow_idx, j;
7c9281d7 774
a895bf8b 775 for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
de3910eb 776 struct csrow_info *csrow = mci->csrows[csrow_idx];
7c9281d7 777
1eef1282
MCC
778 for (j = 0; j < csrow->nr_channels; j++) {
779 struct dimm_info *dimm = csrow->channels[j]->dimm;
3c062276 780
1eef1282 781 total_pages += dimm->nr_pages;
a895bf8b 782 }
7c9281d7
DT
783 }
784
079708b9 785 return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
7c9281d7
DT
786}
787
8ad6c78a
MCC
788static ssize_t mci_max_location_show(struct device *dev,
789 struct device_attribute *mattr,
790 char *data)
791{
792 struct mem_ctl_info *mci = to_mci(dev);
793 int i;
794 char *p = data;
795
796 for (i = 0; i < mci->n_layers; i++) {
797 p += sprintf(p, "%s %d ",
798 edac_layer_name[mci->layers[i].type],
799 mci->layers[i].size - 1);
800 }
801
802 return p - data;
803}
804
452a6bf9
MCC
805#ifdef CONFIG_EDAC_DEBUG
806static ssize_t edac_fake_inject_write(struct file *file,
807 const char __user *data,
808 size_t count, loff_t *ppos)
809{
810 struct device *dev = file->private_data;
811 struct mem_ctl_info *mci = to_mci(dev);
812 static enum hw_event_mc_err_type type;
38ced28b
MCC
813 u16 errcount = mci->fake_inject_count;
814
815 if (!errcount)
816 errcount = 1;
452a6bf9
MCC
817
818 type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
819 : HW_EVENT_ERR_CORRECTED;
820
821 printk(KERN_DEBUG
38ced28b
MCC
822 "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
823 errcount,
452a6bf9 824 (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
38ced28b 825 errcount > 1 ? "s" : "",
452a6bf9
MCC
826 mci->fake_inject_layer[0],
827 mci->fake_inject_layer[1],
828 mci->fake_inject_layer[2]
829 );
38ced28b 830 edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
452a6bf9
MCC
831 mci->fake_inject_layer[0],
832 mci->fake_inject_layer[1],
833 mci->fake_inject_layer[2],
03f7eae8 834 "FAKE ERROR", "for EDAC testing only");
452a6bf9
MCC
835
836 return count;
837}
838
452a6bf9 839static const struct file_operations debug_fake_inject_fops = {
db7312a2 840 .open = simple_open,
452a6bf9
MCC
841 .write = edac_fake_inject_write,
842 .llseek = generic_file_llseek,
843};
844#endif
845
7c9281d7 846/* default Control file */
7a623c03 847DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
7c9281d7
DT
848
849/* default Attribute files */
7a623c03
MCC
850DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
851DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
852DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
853DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
854DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
855DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
856DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
8ad6c78a 857DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
7c9281d7
DT
858
859/* memory scrubber attribute file */
e7100478 860DEVICE_ATTR(sdram_scrub_rate, 0, NULL, NULL);
7c9281d7 861
7a623c03
MCC
862static struct attribute *mci_attrs[] = {
863 &dev_attr_reset_counters.attr,
864 &dev_attr_mc_name.attr,
865 &dev_attr_size_mb.attr,
866 &dev_attr_seconds_since_reset.attr,
867 &dev_attr_ue_noinfo_count.attr,
868 &dev_attr_ce_noinfo_count.attr,
869 &dev_attr_ue_count.attr,
870 &dev_attr_ce_count.attr,
8ad6c78a 871 &dev_attr_max_location.attr,
7c9281d7
DT
872 NULL
873};
874
7a623c03
MCC
875static struct attribute_group mci_attr_grp = {
876 .attrs = mci_attrs,
cc301b3a
MCC
877};
878
7a623c03
MCC
879static const struct attribute_group *mci_attr_groups[] = {
880 &mci_attr_grp,
881 NULL
cc301b3a
MCC
882};
883
de3910eb 884static void mci_attr_release(struct device *dev)
42a8e397 885{
de3910eb
MCC
886 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
887
956b9ba1 888 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 889 kfree(mci);
42a8e397
DT
890}
891
7a623c03
MCC
892static struct device_type mci_attr_type = {
893 .groups = mci_attr_groups,
894 .release = mci_attr_release,
895};
8096cfaf 896
452a6bf9 897#ifdef CONFIG_EDAC_DEBUG
e7930ba4
RH
898static struct dentry *edac_debugfs;
899
900int __init edac_debugfs_init(void)
901{
902 edac_debugfs = debugfs_create_dir("edac", NULL);
903 if (IS_ERR(edac_debugfs)) {
904 edac_debugfs = NULL;
905 return -ENOMEM;
906 }
907 return 0;
908}
909
910void __exit edac_debugfs_exit(void)
911{
912 debugfs_remove(edac_debugfs);
913}
914
452a6bf9
MCC
915int edac_create_debug_nodes(struct mem_ctl_info *mci)
916{
917 struct dentry *d, *parent;
918 char name[80];
919 int i;
920
e7930ba4
RH
921 if (!edac_debugfs)
922 return -ENODEV;
923
924 d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
452a6bf9
MCC
925 if (!d)
926 return -ENOMEM;
927 parent = d;
928
929 for (i = 0; i < mci->n_layers; i++) {
930 sprintf(name, "fake_inject_%s",
931 edac_layer_name[mci->layers[i].type]);
932 d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
933 &mci->fake_inject_layer[i]);
934 if (!d)
935 goto nomem;
936 }
937
938 d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
939 &mci->fake_inject_ue);
940 if (!d)
941 goto nomem;
942
38ced28b
MCC
943 d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
944 &mci->fake_inject_count);
945 if (!d)
946 goto nomem;
947
452a6bf9
MCC
948 d = debugfs_create_file("fake_inject", S_IWUSR, parent,
949 &mci->dev,
950 &debug_fake_inject_fops);
951 if (!d)
952 goto nomem;
953
e7930ba4 954 mci->debugfs = parent;
452a6bf9
MCC
955 return 0;
956nomem:
957 debugfs_remove(mci->debugfs);
958 return -ENOMEM;
959}
960#endif
961
7c9281d7
DT
962/*
963 * Create a new Memory Controller kobject instance,
964 * mc<id> under the 'mc' directory
965 *
966 * Return:
967 * 0 Success
968 * !0 Failure
969 */
970int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
971{
7a623c03 972 int i, err;
7c9281d7 973
de3910eb
MCC
974 /*
975 * The memory controller needs its own bus, in order to avoid
976 * namespace conflicts at /sys/bus/edac.
977 */
978 mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
979 if (!mci->bus.name)
980 return -ENOMEM;
956b9ba1 981 edac_dbg(0, "creating bus %s\n", mci->bus.name);
de3910eb
MCC
982 err = bus_register(&mci->bus);
983 if (err < 0)
984 return err;
7c9281d7 985
7a623c03 986 /* get the /sys/devices/system/edac subsys reference */
7a623c03
MCC
987 mci->dev.type = &mci_attr_type;
988 device_initialize(&mci->dev);
7c9281d7 989
de3910eb 990 mci->dev.parent = mci_pdev;
7a623c03
MCC
991 mci->dev.bus = &mci->bus;
992 dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
993 dev_set_drvdata(&mci->dev, mci);
994 pm_runtime_forbid(&mci->dev);
995
956b9ba1 996 edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
7a623c03
MCC
997 err = device_add(&mci->dev);
998 if (err < 0) {
3d958823 999 edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev));
7a623c03
MCC
1000 bus_unregister(&mci->bus);
1001 kfree(mci->bus.name);
1002 return err;
42a8e397
DT
1003 }
1004
e7100478
MCC
1005 if (mci->set_sdram_scrub_rate || mci->get_sdram_scrub_rate) {
1006 if (mci->get_sdram_scrub_rate) {
1007 dev_attr_sdram_scrub_rate.attr.mode |= S_IRUGO;
1008 dev_attr_sdram_scrub_rate.show = &mci_sdram_scrub_rate_show;
1009 }
1010 if (mci->set_sdram_scrub_rate) {
1011 dev_attr_sdram_scrub_rate.attr.mode |= S_IWUSR;
1012 dev_attr_sdram_scrub_rate.store = &mci_sdram_scrub_rate_store;
1013 }
1014 err = device_create_file(&mci->dev,
1015 &dev_attr_sdram_scrub_rate);
1016 if (err) {
1017 edac_dbg(1, "failure: create sdram_scrub_rate\n");
1018 goto fail2;
1019 }
1020 }
7a623c03
MCC
1021 /*
1022 * Create the dimm/rank devices
7c9281d7 1023 */
7a623c03 1024 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 1025 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1026 /* Only expose populated DIMMs */
1027 if (dimm->nr_pages == 0)
1028 continue;
1029#ifdef CONFIG_EDAC_DEBUG
956b9ba1 1030 edac_dbg(1, "creating dimm%d, located at ", i);
7a623c03
MCC
1031 if (edac_debug_level >= 1) {
1032 int lay;
1033 for (lay = 0; lay < mci->n_layers; lay++)
1034 printk(KERN_CONT "%s %d ",
1035 edac_layer_name[mci->layers[lay].type],
1036 dimm->location[lay]);
1037 printk(KERN_CONT "\n");
7c9281d7 1038 }
7a623c03 1039#endif
19974710
MCC
1040 err = edac_create_dimm_object(mci, dimm, i);
1041 if (err) {
956b9ba1 1042 edac_dbg(1, "failure: create dimm %d obj\n", i);
19974710
MCC
1043 goto fail;
1044 }
7c9281d7
DT
1045 }
1046
19974710 1047#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
1048 err = edac_create_csrow_objects(mci);
1049 if (err < 0)
1050 goto fail;
19974710 1051#endif
7a623c03 1052
452a6bf9
MCC
1053#ifdef CONFIG_EDAC_DEBUG
1054 edac_create_debug_nodes(mci);
1055#endif
7c9281d7
DT
1056 return 0;
1057
7a623c03 1058fail:
079708b9 1059 for (i--; i >= 0; i--) {
de3910eb 1060 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1061 if (dimm->nr_pages == 0)
1062 continue;
44d22e24 1063 device_unregister(&dimm->dev);
7c9281d7 1064 }
e7100478 1065fail2:
44d22e24 1066 device_unregister(&mci->dev);
7a623c03
MCC
1067 bus_unregister(&mci->bus);
1068 kfree(mci->bus.name);
7c9281d7
DT
1069 return err;
1070}
1071
1072/*
1073 * remove a Memory Controller instance
1074 */
1075void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
1076{
7a623c03 1077 int i;
7c9281d7 1078
956b9ba1 1079 edac_dbg(0, "\n");
7c9281d7 1080
452a6bf9
MCC
1081#ifdef CONFIG_EDAC_DEBUG
1082 debugfs_remove(mci->debugfs);
1083#endif
19974710 1084#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03 1085 edac_delete_csrow_objects(mci);
19974710 1086#endif
7c9281d7 1087
7a623c03 1088 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 1089 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1090 if (dimm->nr_pages == 0)
1091 continue;
956b9ba1 1092 edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
44d22e24 1093 device_unregister(&dimm->dev);
6fe1108f 1094 }
7c9281d7 1095}
8096cfaf 1096
7a623c03
MCC
1097void edac_unregister_sysfs(struct mem_ctl_info *mci)
1098{
956b9ba1 1099 edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
44d22e24 1100 device_unregister(&mci->dev);
7a623c03
MCC
1101 bus_unregister(&mci->bus);
1102 kfree(mci->bus.name);
1103}
8096cfaf 1104
de3910eb 1105static void mc_attr_release(struct device *dev)
7a623c03 1106{
de3910eb
MCC
1107 /*
1108 * There's no container structure here, as this is just the mci
1109 * parent device, used to create the /sys/devices/mc sysfs node.
1110 * So, there are no attributes on it.
1111 */
956b9ba1 1112 edac_dbg(1, "Releasing device %s\n", dev_name(dev));
de3910eb 1113 kfree(dev);
7a623c03 1114}
8096cfaf 1115
7a623c03
MCC
1116static struct device_type mc_attr_type = {
1117 .release = mc_attr_release,
1118};
8096cfaf 1119/*
7a623c03 1120 * Init/exit code for the module. Basically, creates/removes /sys/class/rc
8096cfaf 1121 */
7a623c03 1122int __init edac_mc_sysfs_init(void)
8096cfaf 1123{
fe5ff8b8 1124 struct bus_type *edac_subsys;
7a623c03 1125 int err;
8096cfaf 1126
fe5ff8b8
KS
1127 /* get the /sys/devices/system/edac subsys reference */
1128 edac_subsys = edac_get_sysfs_subsys();
1129 if (edac_subsys == NULL) {
956b9ba1 1130 edac_dbg(1, "no edac_subsys\n");
2d56b109
DK
1131 err = -EINVAL;
1132 goto out;
8096cfaf
DT
1133 }
1134
de3910eb 1135 mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
2d56b109
DK
1136 if (!mci_pdev) {
1137 err = -ENOMEM;
1138 goto out_put_sysfs;
1139 }
de3910eb
MCC
1140
1141 mci_pdev->bus = edac_subsys;
1142 mci_pdev->type = &mc_attr_type;
1143 device_initialize(mci_pdev);
1144 dev_set_name(mci_pdev, "mc");
8096cfaf 1145
de3910eb 1146 err = device_add(mci_pdev);
7a623c03 1147 if (err < 0)
2d56b109 1148 goto out_dev_free;
8096cfaf 1149
956b9ba1 1150 edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
de3910eb 1151
8096cfaf 1152 return 0;
2d56b109
DK
1153
1154 out_dev_free:
1155 kfree(mci_pdev);
1156 out_put_sysfs:
1157 edac_put_sysfs_subsys();
1158 out:
1159 return err;
8096cfaf
DT
1160}
1161
7a623c03 1162void __exit edac_mc_sysfs_exit(void)
8096cfaf 1163{
44d22e24 1164 device_unregister(mci_pdev);
fe5ff8b8 1165 edac_put_sysfs_subsys();
8096cfaf 1166}