[linux-2.6-block.git] / drivers / edac / amd64_edac.h

/*
 * AMD64 class Memory Controller kernel module
 *
 * Copyright (c) 2009 SoftwareBitMaker.
 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 */

#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/mmzone.h>
#include <linux/edac.h>
#include <asm/msr.h>
#include "edac_core.h"
#include "mce_amd.h"

#define amd64_debug(fmt, arg...) \
	edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)

#define amd64_info(fmt, arg...) \
	edac_printk(KERN_INFO, "amd64", fmt, ##arg)

#define amd64_notice(fmt, arg...) \
	edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)

#define amd64_warn(fmt, arg...) \
	edac_printk(KERN_WARNING, "amd64", fmt, ##arg)

#define amd64_err(fmt, arg...) \
	edac_printk(KERN_ERR, "amd64", fmt, ##arg)

#define amd64_mc_warn(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)

#define amd64_mc_err(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)

/*
 * Throughout the comments in this code, the following terms are used:
 *
 *	SysAddr, DramAddr, and InputAddr
 *
 *  These terms come directly from the amd64 documentation
 * (AMD publication #26094).  They are defined as follows:
 *
 *     SysAddr:
 *         This is a physical address generated by a CPU core or a device
 *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
 *         a virtual to physical address translation by the CPU core's address
 *         translation mechanism (MMU).
 *
 *     DramAddr:
 *         A DramAddr is derived from a SysAddr by subtracting an offset that
 *         depends on which node the SysAddr maps to and whether the SysAddr
 *         is within a range affected by memory hoisting.  The DRAM Base
 *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
 *         determine which node a SysAddr maps to.
 *
 *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
 *         is within the range of addresses specified by this register, then
 *         a value x from the DHAR is subtracted from the SysAddr to produce a
 *         DramAddr.  Here, x represents the base address for the node that
 *         the SysAddr maps to plus an offset due to memory hoisting.  See
 *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
 *         sys_addr_to_dram_addr() below for more information.
 *
 *         If the SysAddr is not affected by the DHAR then a value y is
 *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
 *         base address for the node that the SysAddr maps to.  See section
 *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
 *         information.
 *
 *     InputAddr:
 *         A DramAddr is translated to an InputAddr before being passed to the
 *         memory controller for the node that the DramAddr is associated
 *         with.  The memory controller then maps the InputAddr to a csrow.
 *         If node interleaving is not in use, then the InputAddr has the same
 *         value as the DramAddr.  Otherwise, the InputAddr is produced by
 *         discarding the bits used for node interleaving from the DramAddr.
 *         See section 3.4.4 for more information.
 *
 *         The memory controller for a given node uses its DRAM CS Base and
 *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
 *         sections 3.5.4 and 3.5.5 for more information.
 */

#define EDAC_AMD64_VERSION		"3.4.0"
#define EDAC_MOD_STR			"amd64_edac"

/* Extended Model from CPUID, for CPU Revision numbers */
#define K8_REV_D			1
#define K8_REV_E			2
#define K8_REV_F			4

/* Hardware limit on ChipSelect rows per MC and processors per system */
#define NUM_CHIPSELECTS			8
#define DRAM_RANGES			8

#define ON true
#define OFF false

/*
 * PCI-defined configuration space registers
 */
#define PCI_DEVICE_ID_AMD_15H_NB_F1	0x1601
#define PCI_DEVICE_ID_AMD_15H_NB_F2	0x1602
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
#define PCI_DEVICE_ID_AMD_16H_NB_F1	0x1531
#define PCI_DEVICE_ID_AMD_16H_NB_F2	0x1532
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582

/*
 * Function 1 - Address Map
 */
#define DRAM_BASE_LO			0x40
#define DRAM_LIMIT_LO			0x44

/*
 * F15 M30h D18F1x2[1C:00]
 */
#define DRAM_CONT_BASE			0x200
#define DRAM_CONT_LIMIT			0x204

/*
 * F15 M30h D18F1x2[4C:40]
 */
#define DRAM_CONT_HIGH_OFF		0x240

#define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))
#define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
#define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))

#define DHAR				0xf0
#define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
#define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
#define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)

					/* NOTE: Extra mask bit vs K8 */
#define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)

#define DCT_CFG_SEL			0x10C

#define DRAM_LOCAL_NODE_BASE		0x120
#define DRAM_LOCAL_NODE_LIM		0x124

#define DRAM_BASE_HI			0x140
#define DRAM_LIMIT_HI			0x144


/*
 * Function 2 - DRAM controller
 */
#define DCSB0				0x40
#define DCSB1				0x140
#define DCSB_CS_ENABLE			BIT(0)

#define DCSM0				0x60
#define DCSM1				0x160

#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)

#define DRAM_CONTROL			0x78

#define DBAM0				0x80
#define DBAM1				0x180

/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
#define DBAM_DIMM(i, reg)		((((reg) >> (4*(i)))) & 0xF)

#define DBAM_MAX_VALUE			11

#define DCLR0				0x90
#define DCLR1				0x190
#define REVE_WIDTH_128			BIT(16)
#define WIDTH_128			BIT(11)

#define DCHR0				0x94
#define DCHR1				0x194
#define DDR3_MODE			BIT(8)

#define DCT_SEL_LO			0x110
#define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
#define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))

#define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))

#define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
#define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))

#define SWAP_INTLV_REG			0x10c

#define DCT_SEL_HI			0x114

#define F15H_M60H_SCRCTRL		0x1C8

/*
 * Function 3 - Misc Control
 */
#define NBCTL				0x40

#define NBCFG				0x44
#define NBCFG_CHIPKILL			BIT(23)
#define NBCFG_ECC_ENABLE		BIT(22)

/* F3x48: NBSL */
#define F10_NBSL_EXT_ERR_ECC		0x8
#define NBSL_PP_OBS			0x2

#define SCRCTRL				0x58

#define F10_ONLINE_SPARE		0xB0
#define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
#define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)

#define F10_NB_ARRAY_ADDR		0xB8
#define F10_NB_ARRAY_DRAM		BIT(31)

/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
#define SET_NB_ARRAY_ADDR(section)	(((section) & 0x3) << 1)

#define F10_NB_ARRAY_DATA		0xBC
#define F10_NB_ARR_ECC_WR_REQ		BIT(17)
#define SET_NB_DRAM_INJECTION_WRITE(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
#define SET_NB_DRAM_INJECTION_READ(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					BIT(16) |  inj.bit_map)


#define NBCAP				0xE8
#define NBCAP_CHIPKILL			BIT(4)
#define NBCAP_SECDED			BIT(3)
#define NBCAP_DCT_DUAL			BIT(0)

#define EXT_NB_MCA_CFG			0x180

/* MSRs */
#define MSR_MCGCTL_NBE			BIT(4)

enum amd_families {
	K8_CPUS = 0,
	F10_CPUS,
	F15_CPUS,
	F15_M30H_CPUS,
	F15_M60H_CPUS,
	F16_CPUS,
	F16_M30H_CPUS,
	NUM_FAMILIES,
};

/* Error injection control structure */
struct error_injection {
	u32	 section;
	u32	 word;
	u32	 bit_map;
};

/* low and high part of PCI config space regs */
struct reg_pair {
	u32 lo, hi;
};

/*
 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
 */
struct dram_range {
	struct reg_pair base;
	struct reg_pair lim;
};

/* A DCT chip selects collection */
struct chip_select {
	u32 csbases[NUM_CHIPSELECTS];
	u8 b_cnt;

	u32 csmasks[NUM_CHIPSELECTS];
	u8 m_cnt;
};

struct amd64_pvt {
	struct low_ops *ops;

	/* pci_device handles which we utilize */
	struct pci_dev *F1, *F2, *F3;

	u16 mc_node_id;		/* MC index of this MC node */
	u8 fam;			/* CPU family */
	u8 model;		/* ... model */
	u8 stepping;		/* ... stepping */

	int ext_model;		/* extended model value of this node */
	int channel_count;

	/* Raw registers */
	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
	u32 nbcap;		/* North Bridge Capabilities */
	u32 nbcfg;		/* F10 North Bridge Configuration */
	u32 ext_nbcfg;		/* Extended F10 North Bridge Configuration */
	u32 dhar;		/* DRAM Hoist reg */
	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */

	/* one for each DCT */
	struct chip_select csels[2];

	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
	struct dram_range ranges[DRAM_RANGES];

	u64 top_mem;		/* top of memory below 4GB */
	u64 top_mem2;		/* top of memory above 4GB */

	u32 dct_sel_lo;		/* DRAM Controller Select Low */
	u32 dct_sel_hi;		/* DRAM Controller Select High */
	u32 online_spare;	/* On-Line spare Reg */

	/* x4 or x8 syndromes in use */
	u8 ecc_sym_sz;

	/* place to store error injection parameters prior to issue */
	struct error_injection injection;

	/* cache the dram_type */
	enum mem_type dram_type;
};

enum err_codes {
	DECODE_OK	=  0,
	ERR_NODE	= -1,
	ERR_CSROW	= -2,
	ERR_CHANNEL	= -3,
};

struct err_info {
	int err_code;
	struct mem_ctl_info *src_mci;
	int csrow;
	int channel;
	u16 syndrome;
	u32 page;
	u32 offset;
};

static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
{
	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;

	if (boot_cpu_data.x86 == 0xf)
		return addr;

	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
}

static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
{
	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;

	if (boot_cpu_data.x86 == 0xf)
		return lim;

	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
}

static inline u16 extract_syndrome(u64 status)
{
	return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
}

static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30)
		return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
			((pvt->dct_sel_lo >> 6) & 0x3);

	return	((pvt)->dct_sel_lo >> 6) & 0x3;
}
/*
 * per-node ECC settings descriptor
 */
struct ecc_settings {
	u32 old_nbctl;
	bool nbctl_valid;

	struct flags {
		unsigned long nb_mce_enable:1;
		unsigned long nb_ecc_prev:1;
	} flags;
};

#ifdef CONFIG_EDAC_DEBUG
extern const struct attribute_group amd64_edac_dbg_group;
#endif

#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
extern const struct attribute_group amd64_edac_inj_group;
#endif

/*
 * Each of the PCI Device IDs types have their own set of hardware accessor
 * functions and per device encoding/decoding logic.
 */
struct low_ops {
	int (*early_channel_count)	(struct amd64_pvt *pvt);
	void (*map_sysaddr_to_csrow)	(struct mem_ctl_info *mci, u64 sys_addr,
					 struct err_info *);
	int (*dbam_to_cs)		(struct amd64_pvt *pvt, u8 dct,
					 unsigned cs_mode, int cs_mask_nr);
};

struct amd64_family_type {
	const char *ctl_name;
	u16 f1_id, f2_id;
	struct low_ops ops;
};

int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
			       u32 *val, const char *func);
int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func);

#define amd64_read_pci_cfg(pdev, offset, val)	\
	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)

#define amd64_write_pci_cfg(pdev, offset, val)	\
	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)

int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
			     u64 *hole_offset, u64 *hole_size);

#define to_mci(k) container_of(k, struct mem_ctl_info, dev)

/* Injection helpers */
static inline void disable_caches(void *dummy)
{
	write_cr0(read_cr0() | X86_CR0_CD);
	wbinvd();
}

static inline void enable_caches(void *dummy)
{
	write_cr0(read_cr0() & ~X86_CR0_CD);
}

static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
		return (u8) tmp & 0xF;
	}
	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
}

static inline u8 dhar_valid(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 1) & BIT(0);
	}
	return (pvt)->dhar & BIT(0);
}

static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 11) & 0x1FFF;
	}
	return (pvt)->dct_sel_lo & 0xFFFFF800;
}
Commit	Line	Data
cfe40fdb DT	1	/*
	2	* AMD64 class Memory Controller kernel module
	3	*
	4	* Copyright (c) 2009 SoftwareBitMaker.
1a8bc770	5	* Copyright (c) 2009-15 Advanced Micro Devices, Inc.
cfe40fdb DT	6	*
	7	* This file may be distributed under the terms of the
	8	* GNU General Public License.
cfe40fdb DT	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/ctype.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
	16	#include <linux/slab.h>
	17	#include <linux/mmzone.h>
	18	#include <linux/edac.h>
f9431992	19	#include <asm/msr.h>
cfe40fdb	20	#include "edac_core.h"
47ca08a4	21	#include "mce_amd.h"
cfe40fdb	22
24f9a7fe BP	23	#define amd64_debug(fmt, arg...) \
24f9a7fe BP	24	edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
cfe40fdb	25
24f9a7fe BP	26	#define amd64_info(fmt, arg...) \
	27	edac_printk(KERN_INFO, "amd64", fmt, ##arg)
	28
	29	#define amd64_notice(fmt, arg...) \
	30	edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
	31
	32	#define amd64_warn(fmt, arg...) \
	33	edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
	34
	35	#define amd64_err(fmt, arg...) \
	36	edac_printk(KERN_ERR, "amd64", fmt, ##arg)
	37
	38	#define amd64_mc_warn(mci, fmt, arg...) \
	39	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
	40
	41	#define amd64_mc_err(mci, fmt, arg...) \
	42	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
cfe40fdb DT	43
	44	/*
	45	* Throughout the comments in this code, the following terms are used:
	46	*
	47	* SysAddr, DramAddr, and InputAddr
	48	*
	49	* These terms come directly from the amd64 documentation
	50	* (AMD publication #26094). They are defined as follows:
	51	*
	52	* SysAddr:
	53	* This is a physical address generated by a CPU core or a device
	54	* doing DMA. If generated by a CPU core, a SysAddr is the result of
	55	* a virtual to physical address translation by the CPU core's address
	56	* translation mechanism (MMU).
	57	*
	58	* DramAddr:
	59	* A DramAddr is derived from a SysAddr by subtracting an offset that
	60	* depends on which node the SysAddr maps to and whether the SysAddr
	61	* is within a range affected by memory hoisting. The DRAM Base
	62	* (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
	63	* determine which node a SysAddr maps to.
	64	*
	65	* If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
	66	* is within the range of addresses specified by this register, then
	67	* a value x from the DHAR is subtracted from the SysAddr to produce a
	68	* DramAddr. Here, x represents the base address for the node that
	69	* the SysAddr maps to plus an offset due to memory hoisting. See
	70	* section 3.4.8 and the comments in amd64_get_dram_hole_info() and
	71	* sys_addr_to_dram_addr() below for more information.
	72	*
	73	* If the SysAddr is not affected by the DHAR then a value y is
	74	* subtracted from the SysAddr to produce a DramAddr. Here, y is the
	75	* base address for the node that the SysAddr maps to. See section
	76	* 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
	77	* information.
	78	*
	79	* InputAddr:
	80	* A DramAddr is translated to an InputAddr before being passed to the
	81	* memory controller for the node that the DramAddr is associated
	82	* with. The memory controller then maps the InputAddr to a csrow.
	83	* If node interleaving is not in use, then the InputAddr has the same
	84	* value as the DramAddr. Otherwise, the InputAddr is produced by
	85	* discarding the bits used for node interleaving from the DramAddr.
	86	* See section 3.4.4 for more information.
	87	*
	88	* The memory controller for a given node uses its DRAM CS Base and
	89	* DRAM CS Mask registers to map an InputAddr to a csrow. See
	90	* sections 3.5.4 and 3.5.5 for more information.
	91	*/
	92
df71a053	93	#define EDAC_AMD64_VERSION "3.4.0"
cfe40fdb DT	94	#define EDAC_MOD_STR "amd64_edac"
	95
	96	/* Extended Model from CPUID, for CPU Revision numbers */
1433eb99 BP	97	#define K8_REV_D 1
	98	#define K8_REV_E 2
	99	#define K8_REV_F 4
cfe40fdb DT	100
cfe40fdb DT	101	/* Hardware limit on ChipSelect rows per MC and processors per system */
7f19bf75 BP	102	#define NUM_CHIPSELECTS 8
7f19bf75 BP	103	#define DRAM_RANGES 8
cfe40fdb	104
f6d6ae96 BP	105	#define ON true
f6d6ae96 BP	106	#define OFF false
cfe40fdb DT	107
	108	/*
	109	* PCI-defined configuration space registers
	110	*/
df71a053 BP	111	#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
df71a053 BP	112	#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
a597d2a5 AG	113	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
	114	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
	115	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
	116	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
94c1acf2 AG	117	#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
94c1acf2 AG	118	#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
85a8885b AG	119	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
85a8885b AG	120	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
cfe40fdb DT	121
	122	/*
	123	* Function 1 - Address Map
	124	*/
7f19bf75 BP	125	#define DRAM_BASE_LO 0x40
	126	#define DRAM_LIMIT_LO 0x44
	127
18b94f66 AG	128	/*
	129	* F15 M30h D18F1x2[1C:00]
	130	*/
	131	#define DRAM_CONT_BASE 0x200
	132	#define DRAM_CONT_LIMIT 0x204
	133
	134	/*
	135	* F15 M30h D18F1x2[4C:40]
	136	*/
	137	#define DRAM_CONT_HIGH_OFF 0x240
	138
151fa71c BP	139	#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
	140	#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
	141	#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
7f19bf75	142
bc21fa57	143	#define DHAR 0xf0
c8e518d5 BP	144	#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
	145	#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
	146	#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
cfe40fdb	147
cfe40fdb	148	/* NOTE: Extra mask bit vs K8 */
c8e518d5	149	#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
cfe40fdb	150
b2b0c605	151	#define DCT_CFG_SEL 0x10C
cfe40fdb	152
c1ae6830	153	#define DRAM_LOCAL_NODE_BASE 0x120
f08e457c BP	154	#define DRAM_LOCAL_NODE_LIM 0x124
f08e457c BP	155
7f19bf75 BP	156	#define DRAM_BASE_HI 0x140
7f19bf75 BP	157	#define DRAM_LIMIT_HI 0x144
cfe40fdb DT	158
	159
	160	/*
	161	* Function 2 - DRAM controller
	162	*/
11c75ead BP	163	#define DCSB0 0x40
	164	#define DCSB1 0x140
	165	#define DCSB_CS_ENABLE BIT(0)
cfe40fdb	166
11c75ead BP	167	#define DCSM0 0x60
11c75ead BP	168	#define DCSM1 0x160
cfe40fdb	169
11c75ead	170	#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
cfe40fdb	171
a597d2a5 AG	172	#define DRAM_CONTROL 0x78
a597d2a5 AG	173
cfe40fdb DT	174	#define DBAM0 0x80
	175	#define DBAM1 0x180
	176
	177	/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
0a5dfc31	178	#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
cfe40fdb DT	179
	180	#define DBAM_MAX_VALUE 11
	181
cb328507 BP	182	#define DCLR0 0x90
cb328507 BP	183	#define DCLR1 0x190
cfe40fdb	184	#define REVE_WIDTH_128 BIT(16)
41d8bfab	185	#define WIDTH_128 BIT(11)
cfe40fdb	186
cb328507 BP	187	#define DCHR0 0x94
cb328507 BP	188	#define DCHR1 0x194
1433eb99	189	#define DDR3_MODE BIT(8)
cfe40fdb	190
78da121e	191	#define DCT_SEL_LO 0x110
78da121e BP	192	#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
78da121e BP	193	#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
cb328507	194
78da121e	195	#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
cb328507	196
78da121e	197	#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
78da121e	198	#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
cfe40fdb	199
95b0ef55 BP	200	#define SWAP_INTLV_REG 0x10c
95b0ef55 BP	201
78da121e	202	#define DCT_SEL_HI 0x114
cfe40fdb	203
da92110d AG	204	#define F15H_M60H_SCRCTRL 0x1C8
da92110d AG	205
cfe40fdb DT	206	/*
	207	* Function 3 - Misc Control
	208	*/
c9f4f26e	209	#define NBCTL 0x40
cfe40fdb	210
a97fa68e BP	211	#define NBCFG 0x44
	212	#define NBCFG_CHIPKILL BIT(23)
	213	#define NBCFG_ECC_ENABLE BIT(22)
cfe40fdb	214
5980bb9c	215	/* F3x48: NBSL */
cfe40fdb	216	#define F10_NBSL_EXT_ERR_ECC 0x8
5980bb9c	217	#define NBSL_PP_OBS 0x2
cfe40fdb	218
5980bb9c	219	#define SCRCTRL 0x58
cfe40fdb DT	220
cfe40fdb DT	221	#define F10_ONLINE_SPARE 0xB0
614ec9d8 BP	222	#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
614ec9d8 BP	223	#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
cfe40fdb DT	224
cfe40fdb DT	225	#define F10_NB_ARRAY_ADDR 0xB8
6e71a870	226	#define F10_NB_ARRAY_DRAM BIT(31)
cfe40fdb DT	227
cfe40fdb DT	228	/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
6e71a870	229	#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
cfe40fdb DT	230
cfe40fdb DT	231	#define F10_NB_ARRAY_DATA 0xBC
66fed2d4	232	#define F10_NB_ARR_ECC_WR_REQ BIT(17)
6e71a870 BP	233	#define SET_NB_DRAM_INJECTION_WRITE(inj) \
6e71a870 BP	234	(BIT(((inj.word) & 0xF) + 20) \| \
66fed2d4	235	F10_NB_ARR_ECC_WR_REQ \| inj.bit_map)
6e71a870 BP	236	#define SET_NB_DRAM_INJECTION_READ(inj) \
	237	(BIT(((inj.word) & 0xF) + 20) \| \
	238	BIT(16) \| inj.bit_map)
	239
cfe40fdb	240
5980bb9c BP	241	#define NBCAP 0xE8
	242	#define NBCAP_CHIPKILL BIT(4)
	243	#define NBCAP_SECDED BIT(3)
	244	#define NBCAP_DCT_DUAL BIT(0)
cfe40fdb	245
ad6a32e9 BP	246	#define EXT_NB_MCA_CFG 0x180
ad6a32e9 BP	247
f6d6ae96	248	/* MSRs */
5980bb9c	249	#define MSR_MCGCTL_NBE BIT(4)
cfe40fdb	250
b2b0c605	251	enum amd_families {
cfe40fdb DT	252	K8_CPUS = 0,
cfe40fdb DT	253	F10_CPUS,
b2b0c605	254	F15_CPUS,
18b94f66	255	F15_M30H_CPUS,
a597d2a5	256	F15_M60H_CPUS,
94c1acf2	257	F16_CPUS,
85a8885b	258	F16_M30H_CPUS,
b2b0c605	259	NUM_FAMILIES,
cfe40fdb DT	260	};
cfe40fdb DT	261
cfe40fdb DT	262	/* Error injection control structure */
cfe40fdb DT	263	struct error_injection {
66fed2d4 BP	264	u32 section;
	265	u32 word;
	266	u32 bit_map;
cfe40fdb DT	267	};
cfe40fdb DT	268
7f19bf75 BP	269	/* low and high part of PCI config space regs */
	270	struct reg_pair {
	271	u32 lo, hi;
	272	};
	273
	274	/*
	275	* See F1x[1, 0][7C:40] DRAM Base/Limit Registers
	276	*/
	277	struct dram_range {
	278	struct reg_pair base;
	279	struct reg_pair lim;
	280	};
	281
11c75ead BP	282	/* A DCT chip selects collection */
	283	struct chip_select {
	284	u32 csbases[NUM_CHIPSELECTS];
	285	u8 b_cnt;
	286
	287	u32 csmasks[NUM_CHIPSELECTS];
	288	u8 m_cnt;
	289	};
	290
cfe40fdb	291	struct amd64_pvt {
b8cfa02f BP	292	struct low_ops *ops;
b8cfa02f BP	293
cfe40fdb	294	/* pci_device handles which we utilize */
8d5b5d9c	295	struct pci_dev F1, F2, *F3;
cfe40fdb	296
c7e5301a	297	u16 mc_node_id; /* MC index of this MC node */
18b94f66	298	u8 fam; /* CPU family */
a4b4bedc BP	299	u8 model; /* ... model */
	300	u8 stepping; /* ... stepping */
	301
cfe40fdb	302	int ext_model; /* extended model value of this node */
cfe40fdb DT	303	int channel_count;
	304
	305	/* Raw registers */
	306	u32 dclr0; /* DRAM Configuration Low DCT0 reg */
	307	u32 dclr1; /* DRAM Configuration Low DCT1 reg */
	308	u32 dchr0; /* DRAM Configuration High DCT0 reg */
	309	u32 dchr1; /* DRAM Configuration High DCT1 reg */
	310	u32 nbcap; /* North Bridge Capabilities */
	311	u32 nbcfg; /* F10 North Bridge Configuration */
	312	u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
	313	u32 dhar; /* DRAM Hoist reg */
	314	u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
	315	u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
	316
11c75ead BP	317	/* one for each DCT */
11c75ead BP	318	struct chip_select csels[2];
cfe40fdb	319
7f19bf75 BP	320	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
7f19bf75 BP	321	struct dram_range ranges[DRAM_RANGES];
cfe40fdb	322
cfe40fdb DT	323	u64 top_mem; /* top of memory below 4GB */
	324	u64 top_mem2; /* top of memory above 4GB */
	325
78da121e BP	326	u32 dct_sel_lo; /* DRAM Controller Select Low */
78da121e BP	327	u32 dct_sel_hi; /* DRAM Controller Select High */
b2b0c605	328	u32 online_spare; /* On-Line spare Reg */
cfe40fdb	329
ad6a32e9	330	/* x4 or x8 syndromes in use */
a3b7db09	331	u8 ecc_sym_sz;
ad6a32e9	332
cfe40fdb DT	333	/* place to store error injection parameters prior to issue */
cfe40fdb DT	334	struct error_injection injection;
a597d2a5 AG	335
	336	/* cache the dram_type */
	337	enum mem_type dram_type;
ae7bb7c6 BP	338	};
ae7bb7c6 BP	339
33ca0643 BP	340	enum err_codes {
	341	DECODE_OK = 0,
	342	ERR_NODE = -1,
	343	ERR_CSROW = -2,
	344	ERR_CHANNEL = -3,
	345	};
	346
	347	struct err_info {
	348	int err_code;
	349	struct mem_ctl_info *src_mci;
	350	int csrow;
	351	int channel;
	352	u16 syndrome;
	353	u32 page;
	354	u32 offset;
	355	};
	356
c7e5301a	357	static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	358	{
	359	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
	360
	361	if (boot_cpu_data.x86 == 0xf)
	362	return addr;
	363
	364	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) \| addr;
	365	}
	366
c7e5301a	367	static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	368	{
	369	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) \| 0x00ffffff;
	370
	371	if (boot_cpu_data.x86 == 0xf)
	372	return lim;
	373
	374	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) \| lim;
	375	}
	376
f192c7b1 BP	377	static inline u16 extract_syndrome(u64 status)
	378	{
	379	return ((status >> 47) & 0xff) \| ((status >> 16) & 0xff00);
	380	}
	381
18b94f66 AG	382	static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
	383	{
	384	if (pvt->fam == 0x15 && pvt->model >= 0x30)
	385	return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) \|
	386	((pvt->dct_sel_lo >> 6) & 0x3);
	387
	388	return ((pvt)->dct_sel_lo >> 6) & 0x3;
	389	}
ae7bb7c6 BP	390	/*
	391	* per-node ECC settings descriptor
	392	*/
	393	struct ecc_settings {
	394	u32 old_nbctl;
	395	bool nbctl_valid;
	396
cfe40fdb	397	struct flags {
d95cf4de BP	398	unsigned long nb_mce_enable:1;
d95cf4de BP	399	unsigned long nb_ecc_prev:1;
cfe40fdb DT	400	} flags;
	401	};
	402
7d6034d3	403	#ifdef CONFIG_EDAC_DEBUG
e339f1ec	404	extern const struct attribute_group amd64_edac_dbg_group;
7d6034d3 DT	405	#endif
	406
	407	#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
e339f1ec	408	extern const struct attribute_group amd64_edac_inj_group;
7d6034d3 DT	409	#endif
7d6034d3 DT	410
cfe40fdb DT	411	/*
	412	* Each of the PCI Device IDs types have their own set of hardware accessor
	413	* functions and per device encoding/decoding logic.
	414	*/
	415	struct low_ops {
1433eb99	416	int (early_channel_count) (struct amd64_pvt pvt);
f192c7b1	417	void (map_sysaddr_to_csrow) (struct mem_ctl_info mci, u64 sys_addr,
33ca0643	418	struct err_info *);
a597d2a5 AG	419	int (dbam_to_cs) (struct amd64_pvt pvt, u8 dct,
a597d2a5 AG	420	unsigned cs_mode, int cs_mask_nr);
cfe40fdb DT	421	};
	422
	423	struct amd64_family_type {
	424	const char *ctl_name;
3f37a36b	425	u16 f1_id, f2_id;
cfe40fdb DT	426	struct low_ops ops;
	427	};
	428
66fed2d4 BP	429	int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
66fed2d4 BP	430	u32 val, const char func);
b2b0c605 BP	431	int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
b2b0c605 BP	432	u32 val, const char *func);
6ba5dcdc	433
b2b0c605 BP	434	#define amd64_read_pci_cfg(pdev, offset, val) \
b2b0c605 BP	435	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	436
b2b0c605 BP	437	#define amd64_write_pci_cfg(pdev, offset, val) \
b2b0c605 BP	438	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	439
cfe40fdb DT	440	int amd64_get_dram_hole_info(struct mem_ctl_info mci, u64 hole_base,
cfe40fdb DT	441	u64 hole_offset, u64 hole_size);
c5608759 MCC	442
c5608759 MCC	443	#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
66fed2d4 BP	444
	445	/* Injection helpers */
	446	static inline void disable_caches(void *dummy)
	447	{
	448	write_cr0(read_cr0() \| X86_CR0_CD);
	449	wbinvd();
	450	}
	451
	452	static inline void enable_caches(void *dummy)
	453	{
	454	write_cr0(read_cr0() & ~X86_CR0_CD);
	455	}
18b94f66 AG	456
	457	static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
	458	{
	459	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	460	u32 tmp;
	461	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
	462	return (u8) tmp & 0xF;
	463	}
	464	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
	465	}
	466
	467	static inline u8 dhar_valid(struct amd64_pvt *pvt)
	468	{
	469	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	470	u32 tmp;
	471	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	472	return (tmp >> 1) & BIT(0);
	473	}
	474	return (pvt)->dhar & BIT(0);
	475	}
	476
	477	static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
	478	{
	479	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	480	u32 tmp;
	481	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	482	return (tmp >> 11) & 0x1FFF;
	483	}
	484	return (pvt)->dct_sel_lo & 0xFFFFF800;
	485	}