Commit | Line | Data |
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3bfb1d20 HS |
1 | /* |
2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on | |
3 | * AVR32 systems.) | |
4 | * | |
5 | * Copyright (C) 2007-2008 Atmel Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/clk.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/dmaengine.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/slab.h> | |
22 | ||
23 | #include "dw_dmac_regs.h" | |
24 | ||
25 | /* | |
26 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
27 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
28 | * of which use ARM any more). See the "Databook" from Synopsys for | |
29 | * information beyond what licensees probably provide. | |
30 | * | |
31 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
32 | * which does not support descriptor writeback. | |
33 | */ | |
34 | ||
f301c062 JI |
35 | #define DWC_DEFAULT_CTLLO(private) ({ \ |
36 | struct dw_dma_slave *__slave = (private); \ | |
37 | int dms = __slave ? __slave->dst_master : 0; \ | |
38 | int sms = __slave ? __slave->src_master : 1; \ | |
39 | \ | |
40 | (DWC_CTLL_DST_MSIZE(0) \ | |
41 | | DWC_CTLL_SRC_MSIZE(0) \ | |
42 | | DWC_CTLL_LLP_D_EN \ | |
43 | | DWC_CTLL_LLP_S_EN \ | |
44 | | DWC_CTLL_DMS(dms) \ | |
45 | | DWC_CTLL_SMS(sms)); \ | |
46 | }) | |
3bfb1d20 HS |
47 | |
48 | /* | |
49 | * This is configuration-dependent and usually a funny size like 4095. | |
3bfb1d20 HS |
50 | * |
51 | * Note that this is a transfer count, i.e. if we transfer 32-bit | |
418e7407 | 52 | * words, we can do 16380 bytes per descriptor. |
3bfb1d20 HS |
53 | * |
54 | * This parameter is also system-specific. | |
55 | */ | |
418e7407 | 56 | #define DWC_MAX_COUNT 4095U |
3bfb1d20 HS |
57 | |
58 | /* | |
59 | * Number of descriptors to allocate for each channel. This should be | |
60 | * made configurable somehow; preferably, the clients (at least the | |
61 | * ones using slave transfers) should be able to give us a hint. | |
62 | */ | |
63 | #define NR_DESCS_PER_CHANNEL 64 | |
64 | ||
65 | /*----------------------------------------------------------------------*/ | |
66 | ||
67 | /* | |
68 | * Because we're not relying on writeback from the controller (it may not | |
69 | * even be configured into the core!) we don't need to use dma_pool. These | |
70 | * descriptors -- and associated data -- are cacheable. We do need to make | |
71 | * sure their dcache entries are written back before handing them off to | |
72 | * the controller, though. | |
73 | */ | |
74 | ||
41d5e59c DW |
75 | static struct device *chan2dev(struct dma_chan *chan) |
76 | { | |
77 | return &chan->dev->device; | |
78 | } | |
79 | static struct device *chan2parent(struct dma_chan *chan) | |
80 | { | |
81 | return chan->dev->device.parent; | |
82 | } | |
83 | ||
3bfb1d20 HS |
84 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
85 | { | |
86 | return list_entry(dwc->active_list.next, struct dw_desc, desc_node); | |
87 | } | |
88 | ||
3bfb1d20 HS |
89 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
90 | { | |
91 | struct dw_desc *desc, *_desc; | |
92 | struct dw_desc *ret = NULL; | |
93 | unsigned int i = 0; | |
94 | ||
95 | spin_lock_bh(&dwc->lock); | |
96 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { | |
97 | if (async_tx_test_ack(&desc->txd)) { | |
98 | list_del(&desc->desc_node); | |
99 | ret = desc; | |
100 | break; | |
101 | } | |
41d5e59c | 102 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 HS |
103 | i++; |
104 | } | |
105 | spin_unlock_bh(&dwc->lock); | |
106 | ||
41d5e59c | 107 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
108 | |
109 | return ret; | |
110 | } | |
111 | ||
112 | static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
113 | { | |
114 | struct dw_desc *child; | |
115 | ||
e0bd0f8c | 116 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 117 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
118 | child->txd.phys, sizeof(child->lli), |
119 | DMA_TO_DEVICE); | |
41d5e59c | 120 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
121 | desc->txd.phys, sizeof(desc->lli), |
122 | DMA_TO_DEVICE); | |
123 | } | |
124 | ||
125 | /* | |
126 | * Move a descriptor, including any children, to the free list. | |
127 | * `desc' must not be on any lists. | |
128 | */ | |
129 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
130 | { | |
131 | if (desc) { | |
132 | struct dw_desc *child; | |
133 | ||
134 | dwc_sync_desc_for_cpu(dwc, desc); | |
135 | ||
136 | spin_lock_bh(&dwc->lock); | |
e0bd0f8c | 137 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 138 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
139 | "moving child desc %p to freelist\n", |
140 | child); | |
e0bd0f8c | 141 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 142 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 HS |
143 | list_add(&desc->desc_node, &dwc->free_list); |
144 | spin_unlock_bh(&dwc->lock); | |
145 | } | |
146 | } | |
147 | ||
148 | /* Called with dwc->lock held and bh disabled */ | |
149 | static dma_cookie_t | |
150 | dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
151 | { | |
152 | dma_cookie_t cookie = dwc->chan.cookie; | |
153 | ||
154 | if (++cookie < 0) | |
155 | cookie = 1; | |
156 | ||
157 | dwc->chan.cookie = cookie; | |
158 | desc->txd.cookie = cookie; | |
159 | ||
160 | return cookie; | |
161 | } | |
162 | ||
163 | /*----------------------------------------------------------------------*/ | |
164 | ||
165 | /* Called with dwc->lock held and bh disabled */ | |
166 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
167 | { | |
168 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
169 | ||
170 | /* ASSERT: channel is idle */ | |
171 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 172 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 173 | "BUG: Attempted to start non-idle channel\n"); |
41d5e59c | 174 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
175 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", |
176 | channel_readl(dwc, SAR), | |
177 | channel_readl(dwc, DAR), | |
178 | channel_readl(dwc, LLP), | |
179 | channel_readl(dwc, CTL_HI), | |
180 | channel_readl(dwc, CTL_LO)); | |
181 | ||
182 | /* The tasklet will hopefully advance the queue... */ | |
183 | return; | |
184 | } | |
185 | ||
186 | channel_writel(dwc, LLP, first->txd.phys); | |
187 | channel_writel(dwc, CTL_LO, | |
188 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
189 | channel_writel(dwc, CTL_HI, 0); | |
190 | channel_set_bit(dw, CH_EN, dwc->mask); | |
191 | } | |
192 | ||
193 | /*----------------------------------------------------------------------*/ | |
194 | ||
195 | static void | |
196 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
197 | { | |
198 | dma_async_tx_callback callback; | |
199 | void *param; | |
200 | struct dma_async_tx_descriptor *txd = &desc->txd; | |
e518076e | 201 | struct dw_desc *child; |
3bfb1d20 | 202 | |
41d5e59c | 203 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 HS |
204 | |
205 | dwc->completed = txd->cookie; | |
206 | callback = txd->callback; | |
207 | param = txd->callback_param; | |
208 | ||
209 | dwc_sync_desc_for_cpu(dwc, desc); | |
e518076e VK |
210 | |
211 | /* async_tx_ack */ | |
212 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
213 | async_tx_ack(&child->txd); | |
214 | async_tx_ack(&desc->txd); | |
215 | ||
e0bd0f8c | 216 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
217 | list_move(&desc->desc_node, &dwc->free_list); |
218 | ||
657a77fa AN |
219 | if (!dwc->chan.private) { |
220 | struct device *parent = chan2parent(&dwc->chan); | |
221 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
222 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
223 | dma_unmap_single(parent, desc->lli.dar, | |
224 | desc->len, DMA_FROM_DEVICE); | |
225 | else | |
226 | dma_unmap_page(parent, desc->lli.dar, | |
227 | desc->len, DMA_FROM_DEVICE); | |
228 | } | |
229 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
230 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
231 | dma_unmap_single(parent, desc->lli.sar, | |
232 | desc->len, DMA_TO_DEVICE); | |
233 | else | |
234 | dma_unmap_page(parent, desc->lli.sar, | |
235 | desc->len, DMA_TO_DEVICE); | |
236 | } | |
237 | } | |
3bfb1d20 HS |
238 | |
239 | /* | |
240 | * The API requires that no submissions are done from a | |
241 | * callback, so we don't need to drop the lock here | |
242 | */ | |
243 | if (callback) | |
244 | callback(param); | |
245 | } | |
246 | ||
247 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
248 | { | |
249 | struct dw_desc *desc, *_desc; | |
250 | LIST_HEAD(list); | |
251 | ||
252 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 253 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
254 | "BUG: XFER bit set, but channel not idle!\n"); |
255 | ||
256 | /* Try to continue after resetting the channel... */ | |
257 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
258 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
259 | cpu_relax(); | |
260 | } | |
261 | ||
262 | /* | |
263 | * Submit queued descriptors ASAP, i.e. before we go through | |
264 | * the completed ones. | |
265 | */ | |
3bfb1d20 | 266 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
267 | if (!list_empty(&dwc->queue)) { |
268 | list_move(dwc->queue.next, &dwc->active_list); | |
269 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
270 | } | |
3bfb1d20 HS |
271 | |
272 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
273 | dwc_descriptor_complete(dwc, desc); | |
274 | } | |
275 | ||
276 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
277 | { | |
278 | dma_addr_t llp; | |
279 | struct dw_desc *desc, *_desc; | |
280 | struct dw_desc *child; | |
281 | u32 status_xfer; | |
282 | ||
283 | /* | |
284 | * Clear block interrupt flag before scanning so that we don't | |
285 | * miss any, and read LLP before RAW_XFER to ensure it is | |
286 | * valid if we decide to scan the list. | |
287 | */ | |
288 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
289 | llp = channel_readl(dwc, LLP); | |
290 | status_xfer = dma_readl(dw, RAW.XFER); | |
291 | ||
292 | if (status_xfer & dwc->mask) { | |
293 | /* Everything we've submitted is done */ | |
294 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
295 | dwc_complete_all(dw, dwc); | |
296 | return; | |
297 | } | |
298 | ||
087809fc JI |
299 | if (list_empty(&dwc->active_list)) |
300 | return; | |
301 | ||
41d5e59c | 302 | dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp); |
3bfb1d20 HS |
303 | |
304 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
305 | if (desc->lli.llp == llp) | |
306 | /* This one is currently in progress */ | |
307 | return; | |
308 | ||
e0bd0f8c | 309 | list_for_each_entry(child, &desc->tx_list, desc_node) |
3bfb1d20 HS |
310 | if (child->lli.llp == llp) |
311 | /* Currently in progress */ | |
312 | return; | |
313 | ||
314 | /* | |
315 | * No descriptors so far seem to be in progress, i.e. | |
316 | * this one must be done. | |
317 | */ | |
318 | dwc_descriptor_complete(dwc, desc); | |
319 | } | |
320 | ||
41d5e59c | 321 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
322 | "BUG: All descriptors done, but channel not idle!\n"); |
323 | ||
324 | /* Try to continue after resetting the channel... */ | |
325 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
326 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
327 | cpu_relax(); | |
328 | ||
329 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
330 | list_move(dwc->queue.next, &dwc->active_list); |
331 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 HS |
332 | } |
333 | } | |
334 | ||
335 | static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) | |
336 | { | |
41d5e59c | 337 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
338 | " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
339 | lli->sar, lli->dar, lli->llp, | |
340 | lli->ctlhi, lli->ctllo); | |
341 | } | |
342 | ||
343 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
344 | { | |
345 | struct dw_desc *bad_desc; | |
346 | struct dw_desc *child; | |
347 | ||
348 | dwc_scan_descriptors(dw, dwc); | |
349 | ||
350 | /* | |
351 | * The descriptor currently at the head of the active list is | |
352 | * borked. Since we don't have any way to report errors, we'll | |
353 | * just have to scream loudly and try to carry on. | |
354 | */ | |
355 | bad_desc = dwc_first_active(dwc); | |
356 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 357 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
358 | |
359 | /* Clear the error flag and try to restart the controller */ | |
360 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
361 | if (!list_empty(&dwc->active_list)) | |
362 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
363 | ||
364 | /* | |
365 | * KERN_CRITICAL may seem harsh, but since this only happens | |
366 | * when someone submits a bad physical address in a | |
367 | * descriptor, we should consider ourselves lucky that the | |
368 | * controller flagged an error instead of scribbling over | |
369 | * random memory locations. | |
370 | */ | |
41d5e59c | 371 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 | 372 | "Bad descriptor submitted for DMA!\n"); |
41d5e59c | 373 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
374 | " cookie: %d\n", bad_desc->txd.cookie); |
375 | dwc_dump_lli(dwc, &bad_desc->lli); | |
e0bd0f8c | 376 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
377 | dwc_dump_lli(dwc, &child->lli); |
378 | ||
379 | /* Pretend the descriptor completed successfully */ | |
380 | dwc_descriptor_complete(dwc, bad_desc); | |
381 | } | |
382 | ||
d9de4519 HCE |
383 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
384 | ||
385 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
386 | { | |
387 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
388 | return channel_readl(dwc, SAR); | |
389 | } | |
390 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
391 | ||
392 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
393 | { | |
394 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
395 | return channel_readl(dwc, DAR); | |
396 | } | |
397 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
398 | ||
399 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
400 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
401 | u32 status_block, u32 status_err, u32 status_xfer) | |
402 | { | |
403 | if (status_block & dwc->mask) { | |
404 | void (*callback)(void *param); | |
405 | void *callback_param; | |
406 | ||
407 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
408 | channel_readl(dwc, LLP)); | |
409 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
410 | ||
411 | callback = dwc->cdesc->period_callback; | |
412 | callback_param = dwc->cdesc->period_callback_param; | |
413 | if (callback) { | |
414 | spin_unlock(&dwc->lock); | |
415 | callback(callback_param); | |
416 | spin_lock(&dwc->lock); | |
417 | } | |
418 | } | |
419 | ||
420 | /* | |
421 | * Error and transfer complete are highly unlikely, and will most | |
422 | * likely be due to a configuration error by the user. | |
423 | */ | |
424 | if (unlikely(status_err & dwc->mask) || | |
425 | unlikely(status_xfer & dwc->mask)) { | |
426 | int i; | |
427 | ||
428 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
429 | "interrupt, stopping DMA transfer\n", | |
430 | status_xfer ? "xfer" : "error"); | |
431 | dev_err(chan2dev(&dwc->chan), | |
432 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
433 | channel_readl(dwc, SAR), | |
434 | channel_readl(dwc, DAR), | |
435 | channel_readl(dwc, LLP), | |
436 | channel_readl(dwc, CTL_HI), | |
437 | channel_readl(dwc, CTL_LO)); | |
438 | ||
439 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
440 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
441 | cpu_relax(); | |
442 | ||
443 | /* make sure DMA does not restart by loading a new list */ | |
444 | channel_writel(dwc, LLP, 0); | |
445 | channel_writel(dwc, CTL_LO, 0); | |
446 | channel_writel(dwc, CTL_HI, 0); | |
447 | ||
448 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
449 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
450 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
451 | ||
452 | for (i = 0; i < dwc->cdesc->periods; i++) | |
453 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
454 | } | |
455 | } | |
456 | ||
457 | /* ------------------------------------------------------------------------- */ | |
458 | ||
3bfb1d20 HS |
459 | static void dw_dma_tasklet(unsigned long data) |
460 | { | |
461 | struct dw_dma *dw = (struct dw_dma *)data; | |
462 | struct dw_dma_chan *dwc; | |
463 | u32 status_block; | |
464 | u32 status_xfer; | |
465 | u32 status_err; | |
466 | int i; | |
467 | ||
468 | status_block = dma_readl(dw, RAW.BLOCK); | |
7fe7b2f4 | 469 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
470 | status_err = dma_readl(dw, RAW.ERROR); |
471 | ||
472 | dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n", | |
473 | status_block, status_err); | |
474 | ||
475 | for (i = 0; i < dw->dma.chancnt; i++) { | |
476 | dwc = &dw->chan[i]; | |
477 | spin_lock(&dwc->lock); | |
d9de4519 HCE |
478 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
479 | dwc_handle_cyclic(dw, dwc, status_block, status_err, | |
480 | status_xfer); | |
481 | else if (status_err & (1 << i)) | |
3bfb1d20 HS |
482 | dwc_handle_error(dw, dwc); |
483 | else if ((status_block | status_xfer) & (1 << i)) | |
484 | dwc_scan_descriptors(dw, dwc); | |
485 | spin_unlock(&dwc->lock); | |
486 | } | |
487 | ||
488 | /* | |
489 | * Re-enable interrupts. Block Complete interrupts are only | |
490 | * enabled if the INT_EN bit in the descriptor is set. This | |
491 | * will trigger a scan before the whole list is done. | |
492 | */ | |
493 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
494 | channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
495 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
496 | } | |
497 | ||
498 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
499 | { | |
500 | struct dw_dma *dw = dev_id; | |
501 | u32 status; | |
502 | ||
503 | dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n", | |
504 | dma_readl(dw, STATUS_INT)); | |
505 | ||
506 | /* | |
507 | * Just disable the interrupts. We'll turn them back on in the | |
508 | * softirq handler. | |
509 | */ | |
510 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
511 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
512 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
513 | ||
514 | status = dma_readl(dw, STATUS_INT); | |
515 | if (status) { | |
516 | dev_err(dw->dma.dev, | |
517 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
518 | status); | |
519 | ||
520 | /* Try to recover */ | |
521 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
522 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); | |
523 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); | |
524 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
525 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
526 | } | |
527 | ||
528 | tasklet_schedule(&dw->tasklet); | |
529 | ||
530 | return IRQ_HANDLED; | |
531 | } | |
532 | ||
533 | /*----------------------------------------------------------------------*/ | |
534 | ||
535 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
536 | { | |
537 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
538 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
539 | dma_cookie_t cookie; | |
540 | ||
541 | spin_lock_bh(&dwc->lock); | |
542 | cookie = dwc_assign_cookie(dwc, desc); | |
543 | ||
544 | /* | |
545 | * REVISIT: We should attempt to chain as many descriptors as | |
546 | * possible, perhaps even appending to those already submitted | |
547 | * for DMA. But this is hard to do in a race-free manner. | |
548 | */ | |
549 | if (list_empty(&dwc->active_list)) { | |
41d5e59c | 550 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", |
3bfb1d20 | 551 | desc->txd.cookie); |
3bfb1d20 | 552 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 553 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 554 | } else { |
41d5e59c | 555 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", |
3bfb1d20 HS |
556 | desc->txd.cookie); |
557 | ||
558 | list_add_tail(&desc->desc_node, &dwc->queue); | |
559 | } | |
560 | ||
561 | spin_unlock_bh(&dwc->lock); | |
562 | ||
563 | return cookie; | |
564 | } | |
565 | ||
566 | static struct dma_async_tx_descriptor * | |
567 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
568 | size_t len, unsigned long flags) | |
569 | { | |
570 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
571 | struct dw_desc *desc; | |
572 | struct dw_desc *first; | |
573 | struct dw_desc *prev; | |
574 | size_t xfer_count; | |
575 | size_t offset; | |
576 | unsigned int src_width; | |
577 | unsigned int dst_width; | |
578 | u32 ctllo; | |
579 | ||
41d5e59c | 580 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n", |
3bfb1d20 HS |
581 | dest, src, len, flags); |
582 | ||
583 | if (unlikely(!len)) { | |
41d5e59c | 584 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); |
3bfb1d20 HS |
585 | return NULL; |
586 | } | |
587 | ||
588 | /* | |
589 | * We can be a lot more clever here, but this should take care | |
590 | * of the most common optimization. | |
591 | */ | |
a0227456 VK |
592 | if (!((src | dest | len) & 7)) |
593 | src_width = dst_width = 3; | |
594 | else if (!((src | dest | len) & 3)) | |
3bfb1d20 HS |
595 | src_width = dst_width = 2; |
596 | else if (!((src | dest | len) & 1)) | |
597 | src_width = dst_width = 1; | |
598 | else | |
599 | src_width = dst_width = 0; | |
600 | ||
f301c062 | 601 | ctllo = DWC_DEFAULT_CTLLO(chan->private) |
3bfb1d20 HS |
602 | | DWC_CTLL_DST_WIDTH(dst_width) |
603 | | DWC_CTLL_SRC_WIDTH(src_width) | |
604 | | DWC_CTLL_DST_INC | |
605 | | DWC_CTLL_SRC_INC | |
606 | | DWC_CTLL_FC_M2M; | |
607 | prev = first = NULL; | |
608 | ||
609 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
610 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
611 | DWC_MAX_COUNT); | |
612 | ||
613 | desc = dwc_desc_get(dwc); | |
614 | if (!desc) | |
615 | goto err_desc_get; | |
616 | ||
617 | desc->lli.sar = src + offset; | |
618 | desc->lli.dar = dest + offset; | |
619 | desc->lli.ctllo = ctllo; | |
620 | desc->lli.ctlhi = xfer_count; | |
621 | ||
622 | if (!first) { | |
623 | first = desc; | |
624 | } else { | |
625 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 626 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
627 | prev->txd.phys, sizeof(prev->lli), |
628 | DMA_TO_DEVICE); | |
629 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 630 | &first->tx_list); |
3bfb1d20 HS |
631 | } |
632 | prev = desc; | |
633 | } | |
634 | ||
635 | ||
636 | if (flags & DMA_PREP_INTERRUPT) | |
637 | /* Trigger interrupt after last block */ | |
638 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
639 | ||
640 | prev->lli.llp = 0; | |
41d5e59c | 641 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
642 | prev->txd.phys, sizeof(prev->lli), |
643 | DMA_TO_DEVICE); | |
644 | ||
645 | first->txd.flags = flags; | |
646 | first->len = len; | |
647 | ||
648 | return &first->txd; | |
649 | ||
650 | err_desc_get: | |
651 | dwc_desc_put(dwc, first); | |
652 | return NULL; | |
653 | } | |
654 | ||
655 | static struct dma_async_tx_descriptor * | |
656 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
657 | unsigned int sg_len, enum dma_data_direction direction, | |
658 | unsigned long flags) | |
659 | { | |
660 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
287d8592 | 661 | struct dw_dma_slave *dws = chan->private; |
3bfb1d20 HS |
662 | struct dw_desc *prev; |
663 | struct dw_desc *first; | |
664 | u32 ctllo; | |
665 | dma_addr_t reg; | |
666 | unsigned int reg_width; | |
667 | unsigned int mem_width; | |
668 | unsigned int i; | |
669 | struct scatterlist *sg; | |
670 | size_t total_len = 0; | |
671 | ||
41d5e59c | 672 | dev_vdbg(chan2dev(chan), "prep_dma_slave\n"); |
3bfb1d20 HS |
673 | |
674 | if (unlikely(!dws || !sg_len)) | |
675 | return NULL; | |
676 | ||
74465b4f | 677 | reg_width = dws->reg_width; |
3bfb1d20 HS |
678 | prev = first = NULL; |
679 | ||
3bfb1d20 HS |
680 | switch (direction) { |
681 | case DMA_TO_DEVICE: | |
f301c062 | 682 | ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
3bfb1d20 HS |
683 | | DWC_CTLL_DST_WIDTH(reg_width) |
684 | | DWC_CTLL_DST_FIX | |
685 | | DWC_CTLL_SRC_INC | |
686 | | DWC_CTLL_FC_M2P); | |
74465b4f | 687 | reg = dws->tx_reg; |
3bfb1d20 HS |
688 | for_each_sg(sgl, sg, sg_len, i) { |
689 | struct dw_desc *desc; | |
690 | u32 len; | |
691 | u32 mem; | |
692 | ||
693 | desc = dwc_desc_get(dwc); | |
694 | if (!desc) { | |
41d5e59c | 695 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
696 | "not enough descriptors available\n"); |
697 | goto err_desc_get; | |
698 | } | |
699 | ||
700 | mem = sg_phys(sg); | |
701 | len = sg_dma_len(sg); | |
702 | mem_width = 2; | |
703 | if (unlikely(mem & 3 || len & 3)) | |
704 | mem_width = 0; | |
705 | ||
706 | desc->lli.sar = mem; | |
707 | desc->lli.dar = reg; | |
708 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
709 | desc->lli.ctlhi = len >> mem_width; | |
710 | ||
711 | if (!first) { | |
712 | first = desc; | |
713 | } else { | |
714 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 715 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
716 | prev->txd.phys, |
717 | sizeof(prev->lli), | |
718 | DMA_TO_DEVICE); | |
719 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 720 | &first->tx_list); |
3bfb1d20 HS |
721 | } |
722 | prev = desc; | |
723 | total_len += len; | |
724 | } | |
725 | break; | |
726 | case DMA_FROM_DEVICE: | |
f301c062 | 727 | ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
3bfb1d20 HS |
728 | | DWC_CTLL_SRC_WIDTH(reg_width) |
729 | | DWC_CTLL_DST_INC | |
730 | | DWC_CTLL_SRC_FIX | |
731 | | DWC_CTLL_FC_P2M); | |
732 | ||
74465b4f | 733 | reg = dws->rx_reg; |
3bfb1d20 HS |
734 | for_each_sg(sgl, sg, sg_len, i) { |
735 | struct dw_desc *desc; | |
736 | u32 len; | |
737 | u32 mem; | |
738 | ||
739 | desc = dwc_desc_get(dwc); | |
740 | if (!desc) { | |
41d5e59c | 741 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
742 | "not enough descriptors available\n"); |
743 | goto err_desc_get; | |
744 | } | |
745 | ||
746 | mem = sg_phys(sg); | |
747 | len = sg_dma_len(sg); | |
748 | mem_width = 2; | |
749 | if (unlikely(mem & 3 || len & 3)) | |
750 | mem_width = 0; | |
751 | ||
752 | desc->lli.sar = reg; | |
753 | desc->lli.dar = mem; | |
754 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
755 | desc->lli.ctlhi = len >> reg_width; | |
756 | ||
757 | if (!first) { | |
758 | first = desc; | |
759 | } else { | |
760 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 761 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
762 | prev->txd.phys, |
763 | sizeof(prev->lli), | |
764 | DMA_TO_DEVICE); | |
765 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 766 | &first->tx_list); |
3bfb1d20 HS |
767 | } |
768 | prev = desc; | |
769 | total_len += len; | |
770 | } | |
771 | break; | |
772 | default: | |
773 | return NULL; | |
774 | } | |
775 | ||
776 | if (flags & DMA_PREP_INTERRUPT) | |
777 | /* Trigger interrupt after last block */ | |
778 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
779 | ||
780 | prev->lli.llp = 0; | |
41d5e59c | 781 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
782 | prev->txd.phys, sizeof(prev->lli), |
783 | DMA_TO_DEVICE); | |
784 | ||
785 | first->len = total_len; | |
786 | ||
787 | return &first->txd; | |
788 | ||
789 | err_desc_get: | |
790 | dwc_desc_put(dwc, first); | |
791 | return NULL; | |
792 | } | |
793 | ||
05827630 LW |
794 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
795 | unsigned long arg) | |
3bfb1d20 HS |
796 | { |
797 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
798 | struct dw_dma *dw = to_dw_dma(chan->device); | |
799 | struct dw_desc *desc, *_desc; | |
800 | LIST_HEAD(list); | |
801 | ||
c3635c78 LW |
802 | /* Only supports DMA_TERMINATE_ALL */ |
803 | if (cmd != DMA_TERMINATE_ALL) | |
804 | return -ENXIO; | |
805 | ||
3bfb1d20 HS |
806 | /* |
807 | * This is only called when something went wrong elsewhere, so | |
808 | * we don't really care about the data. Just disable the | |
809 | * channel. We still have to poll the channel enable bit due | |
810 | * to AHB/HSB limitations. | |
811 | */ | |
812 | spin_lock_bh(&dwc->lock); | |
813 | ||
814 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
815 | ||
816 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
817 | cpu_relax(); | |
818 | ||
819 | /* active_list entries will end up before queued entries */ | |
820 | list_splice_init(&dwc->queue, &list); | |
821 | list_splice_init(&dwc->active_list, &list); | |
822 | ||
823 | spin_unlock_bh(&dwc->lock); | |
824 | ||
825 | /* Flush all pending and queued descriptors */ | |
826 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
827 | dwc_descriptor_complete(dwc, desc); | |
c3635c78 LW |
828 | |
829 | return 0; | |
3bfb1d20 HS |
830 | } |
831 | ||
832 | static enum dma_status | |
07934481 LW |
833 | dwc_tx_status(struct dma_chan *chan, |
834 | dma_cookie_t cookie, | |
835 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
836 | { |
837 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
838 | dma_cookie_t last_used; | |
839 | dma_cookie_t last_complete; | |
840 | int ret; | |
841 | ||
842 | last_complete = dwc->completed; | |
843 | last_used = chan->cookie; | |
844 | ||
845 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
846 | if (ret != DMA_SUCCESS) { | |
569432ef | 847 | spin_lock_bh(&dwc->lock); |
3bfb1d20 | 848 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
569432ef | 849 | spin_unlock_bh(&dwc->lock); |
3bfb1d20 HS |
850 | |
851 | last_complete = dwc->completed; | |
852 | last_used = chan->cookie; | |
853 | ||
854 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
855 | } | |
856 | ||
bca34692 | 857 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
3bfb1d20 HS |
858 | |
859 | return ret; | |
860 | } | |
861 | ||
862 | static void dwc_issue_pending(struct dma_chan *chan) | |
863 | { | |
864 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
865 | ||
866 | spin_lock_bh(&dwc->lock); | |
867 | if (!list_empty(&dwc->queue)) | |
868 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
869 | spin_unlock_bh(&dwc->lock); | |
870 | } | |
871 | ||
aa1e6f1a | 872 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
873 | { |
874 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
875 | struct dw_dma *dw = to_dw_dma(chan->device); | |
876 | struct dw_desc *desc; | |
3bfb1d20 HS |
877 | struct dw_dma_slave *dws; |
878 | int i; | |
879 | u32 cfghi; | |
880 | u32 cfglo; | |
881 | ||
41d5e59c | 882 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); |
3bfb1d20 | 883 | |
3bfb1d20 HS |
884 | /* ASSERT: channel is idle */ |
885 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 886 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
887 | return -EIO; |
888 | } | |
889 | ||
890 | dwc->completed = chan->cookie = 1; | |
891 | ||
892 | cfghi = DWC_CFGH_FIFO_MODE; | |
893 | cfglo = 0; | |
894 | ||
287d8592 | 895 | dws = chan->private; |
74465b4f | 896 | if (dws) { |
3bfb1d20 HS |
897 | /* |
898 | * We need controller-specific data to set up slave | |
899 | * transfers. | |
900 | */ | |
74465b4f | 901 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); |
3bfb1d20 | 902 | |
3bfb1d20 HS |
903 | cfghi = dws->cfg_hi; |
904 | cfglo = dws->cfg_lo; | |
3bfb1d20 | 905 | } |
3bfb1d20 HS |
906 | channel_writel(dwc, CFG_LO, cfglo); |
907 | channel_writel(dwc, CFG_HI, cfghi); | |
908 | ||
909 | /* | |
910 | * NOTE: some controllers may have additional features that we | |
911 | * need to initialize here, like "scatter-gather" (which | |
912 | * doesn't mean what you think it means), and status writeback. | |
913 | */ | |
914 | ||
915 | spin_lock_bh(&dwc->lock); | |
916 | i = dwc->descs_allocated; | |
917 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
918 | spin_unlock_bh(&dwc->lock); | |
919 | ||
920 | desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL); | |
921 | if (!desc) { | |
41d5e59c | 922 | dev_info(chan2dev(chan), |
3bfb1d20 HS |
923 | "only allocated %d descriptors\n", i); |
924 | spin_lock_bh(&dwc->lock); | |
925 | break; | |
926 | } | |
927 | ||
e0bd0f8c | 928 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
929 | dma_async_tx_descriptor_init(&desc->txd, chan); |
930 | desc->txd.tx_submit = dwc_tx_submit; | |
931 | desc->txd.flags = DMA_CTRL_ACK; | |
41d5e59c | 932 | desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli, |
3bfb1d20 HS |
933 | sizeof(desc->lli), DMA_TO_DEVICE); |
934 | dwc_desc_put(dwc, desc); | |
935 | ||
936 | spin_lock_bh(&dwc->lock); | |
937 | i = ++dwc->descs_allocated; | |
938 | } | |
939 | ||
940 | /* Enable interrupts */ | |
941 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
942 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
943 | channel_set_bit(dw, MASK.ERROR, dwc->mask); | |
944 | ||
945 | spin_unlock_bh(&dwc->lock); | |
946 | ||
41d5e59c | 947 | dev_dbg(chan2dev(chan), |
3bfb1d20 HS |
948 | "alloc_chan_resources allocated %d descriptors\n", i); |
949 | ||
950 | return i; | |
951 | } | |
952 | ||
953 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
954 | { | |
955 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
956 | struct dw_dma *dw = to_dw_dma(chan->device); | |
957 | struct dw_desc *desc, *_desc; | |
958 | LIST_HEAD(list); | |
959 | ||
41d5e59c | 960 | dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n", |
3bfb1d20 HS |
961 | dwc->descs_allocated); |
962 | ||
963 | /* ASSERT: channel is idle */ | |
964 | BUG_ON(!list_empty(&dwc->active_list)); | |
965 | BUG_ON(!list_empty(&dwc->queue)); | |
966 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
967 | ||
968 | spin_lock_bh(&dwc->lock); | |
969 | list_splice_init(&dwc->free_list, &list); | |
970 | dwc->descs_allocated = 0; | |
3bfb1d20 HS |
971 | |
972 | /* Disable interrupts */ | |
973 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
974 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); | |
975 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); | |
976 | ||
977 | spin_unlock_bh(&dwc->lock); | |
978 | ||
979 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c DW |
980 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
981 | dma_unmap_single(chan2parent(chan), desc->txd.phys, | |
3bfb1d20 HS |
982 | sizeof(desc->lli), DMA_TO_DEVICE); |
983 | kfree(desc); | |
984 | } | |
985 | ||
41d5e59c | 986 | dev_vdbg(chan2dev(chan), "free_chan_resources done\n"); |
3bfb1d20 HS |
987 | } |
988 | ||
d9de4519 HCE |
989 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
990 | ||
991 | /** | |
992 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
993 | * @chan: the DMA channel to start | |
994 | * | |
995 | * Must be called with soft interrupts disabled. Returns zero on success or | |
996 | * -errno on failure. | |
997 | */ | |
998 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
999 | { | |
1000 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1001 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1002 | ||
1003 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1004 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1005 | return -ENODEV; | |
1006 | } | |
1007 | ||
1008 | spin_lock(&dwc->lock); | |
1009 | ||
1010 | /* assert channel is idle */ | |
1011 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1012 | dev_err(chan2dev(&dwc->chan), | |
1013 | "BUG: Attempted to start non-idle channel\n"); | |
1014 | dev_err(chan2dev(&dwc->chan), | |
1015 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
1016 | channel_readl(dwc, SAR), | |
1017 | channel_readl(dwc, DAR), | |
1018 | channel_readl(dwc, LLP), | |
1019 | channel_readl(dwc, CTL_HI), | |
1020 | channel_readl(dwc, CTL_LO)); | |
1021 | spin_unlock(&dwc->lock); | |
1022 | return -EBUSY; | |
1023 | } | |
1024 | ||
1025 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
1026 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
1027 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1028 | ||
1029 | /* setup DMAC channel registers */ | |
1030 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1031 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1032 | channel_writel(dwc, CTL_HI, 0); | |
1033 | ||
1034 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1035 | ||
1036 | spin_unlock(&dwc->lock); | |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1041 | ||
1042 | /** | |
1043 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1044 | * @chan: the DMA channel to stop | |
1045 | * | |
1046 | * Must be called with soft interrupts disabled. | |
1047 | */ | |
1048 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1049 | { | |
1050 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1051 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1052 | ||
1053 | spin_lock(&dwc->lock); | |
1054 | ||
1055 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1056 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
1057 | cpu_relax(); | |
1058 | ||
1059 | spin_unlock(&dwc->lock); | |
1060 | } | |
1061 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1062 | ||
1063 | /** | |
1064 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1065 | * @chan: the DMA channel to prepare | |
1066 | * @buf_addr: physical DMA address where the buffer starts | |
1067 | * @buf_len: total number of bytes for the entire buffer | |
1068 | * @period_len: number of bytes for each period | |
1069 | * @direction: transfer direction, to or from device | |
1070 | * | |
1071 | * Must be called before trying to start the transfer. Returns a valid struct | |
1072 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1073 | */ | |
1074 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1075 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
1076 | enum dma_data_direction direction) | |
1077 | { | |
1078 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1079 | struct dw_cyclic_desc *cdesc; | |
1080 | struct dw_cyclic_desc *retval = NULL; | |
1081 | struct dw_desc *desc; | |
1082 | struct dw_desc *last = NULL; | |
1083 | struct dw_dma_slave *dws = chan->private; | |
1084 | unsigned long was_cyclic; | |
1085 | unsigned int reg_width; | |
1086 | unsigned int periods; | |
1087 | unsigned int i; | |
1088 | ||
1089 | spin_lock_bh(&dwc->lock); | |
1090 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { | |
1091 | spin_unlock_bh(&dwc->lock); | |
1092 | dev_dbg(chan2dev(&dwc->chan), | |
1093 | "queue and/or active list are not empty\n"); | |
1094 | return ERR_PTR(-EBUSY); | |
1095 | } | |
1096 | ||
1097 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1098 | spin_unlock_bh(&dwc->lock); | |
1099 | if (was_cyclic) { | |
1100 | dev_dbg(chan2dev(&dwc->chan), | |
1101 | "channel already prepared for cyclic DMA\n"); | |
1102 | return ERR_PTR(-EBUSY); | |
1103 | } | |
1104 | ||
1105 | retval = ERR_PTR(-EINVAL); | |
1106 | reg_width = dws->reg_width; | |
1107 | periods = buf_len / period_len; | |
1108 | ||
1109 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
1110 | if (period_len > (DWC_MAX_COUNT << reg_width)) | |
1111 | goto out_err; | |
1112 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1113 | goto out_err; | |
1114 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1115 | goto out_err; | |
1116 | if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) | |
1117 | goto out_err; | |
1118 | ||
1119 | retval = ERR_PTR(-ENOMEM); | |
1120 | ||
1121 | if (periods > NR_DESCS_PER_CHANNEL) | |
1122 | goto out_err; | |
1123 | ||
1124 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1125 | if (!cdesc) | |
1126 | goto out_err; | |
1127 | ||
1128 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1129 | if (!cdesc->desc) | |
1130 | goto out_err_alloc; | |
1131 | ||
1132 | for (i = 0; i < periods; i++) { | |
1133 | desc = dwc_desc_get(dwc); | |
1134 | if (!desc) | |
1135 | goto out_err_desc_get; | |
1136 | ||
1137 | switch (direction) { | |
1138 | case DMA_TO_DEVICE: | |
1139 | desc->lli.dar = dws->tx_reg; | |
1140 | desc->lli.sar = buf_addr + (period_len * i); | |
f301c062 | 1141 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
d9de4519 HCE |
1142 | | DWC_CTLL_DST_WIDTH(reg_width) |
1143 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1144 | | DWC_CTLL_DST_FIX | |
1145 | | DWC_CTLL_SRC_INC | |
1146 | | DWC_CTLL_FC_M2P | |
1147 | | DWC_CTLL_INT_EN); | |
1148 | break; | |
1149 | case DMA_FROM_DEVICE: | |
1150 | desc->lli.dar = buf_addr + (period_len * i); | |
1151 | desc->lli.sar = dws->rx_reg; | |
f301c062 | 1152 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
d9de4519 HCE |
1153 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1154 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1155 | | DWC_CTLL_DST_INC | |
1156 | | DWC_CTLL_SRC_FIX | |
1157 | | DWC_CTLL_FC_P2M | |
1158 | | DWC_CTLL_INT_EN); | |
1159 | break; | |
1160 | default: | |
1161 | break; | |
1162 | } | |
1163 | ||
1164 | desc->lli.ctlhi = (period_len >> reg_width); | |
1165 | cdesc->desc[i] = desc; | |
1166 | ||
1167 | if (last) { | |
1168 | last->lli.llp = desc->txd.phys; | |
1169 | dma_sync_single_for_device(chan2parent(chan), | |
1170 | last->txd.phys, sizeof(last->lli), | |
1171 | DMA_TO_DEVICE); | |
1172 | } | |
1173 | ||
1174 | last = desc; | |
1175 | } | |
1176 | ||
1177 | /* lets make a cyclic list */ | |
1178 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
1179 | dma_sync_single_for_device(chan2parent(chan), last->txd.phys, | |
1180 | sizeof(last->lli), DMA_TO_DEVICE); | |
1181 | ||
1182 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu " | |
1183 | "period %zu periods %d\n", buf_addr, buf_len, | |
1184 | period_len, periods); | |
1185 | ||
1186 | cdesc->periods = periods; | |
1187 | dwc->cdesc = cdesc; | |
1188 | ||
1189 | return cdesc; | |
1190 | ||
1191 | out_err_desc_get: | |
1192 | while (i--) | |
1193 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1194 | out_err_alloc: | |
1195 | kfree(cdesc); | |
1196 | out_err: | |
1197 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1198 | return (struct dw_cyclic_desc *)retval; | |
1199 | } | |
1200 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1201 | ||
1202 | /** | |
1203 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1204 | * @chan: the DMA channel to free | |
1205 | */ | |
1206 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1207 | { | |
1208 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1209 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1210 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1211 | int i; | |
1212 | ||
1213 | dev_dbg(chan2dev(&dwc->chan), "cyclic free\n"); | |
1214 | ||
1215 | if (!cdesc) | |
1216 | return; | |
1217 | ||
1218 | spin_lock_bh(&dwc->lock); | |
1219 | ||
1220 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1221 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
1222 | cpu_relax(); | |
1223 | ||
1224 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
1225 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
1226 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1227 | ||
1228 | spin_unlock_bh(&dwc->lock); | |
1229 | ||
1230 | for (i = 0; i < cdesc->periods; i++) | |
1231 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1232 | ||
1233 | kfree(cdesc->desc); | |
1234 | kfree(cdesc); | |
1235 | ||
1236 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1237 | } | |
1238 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1239 | ||
3bfb1d20 HS |
1240 | /*----------------------------------------------------------------------*/ |
1241 | ||
1242 | static void dw_dma_off(struct dw_dma *dw) | |
1243 | { | |
1244 | dma_writel(dw, CFG, 0); | |
1245 | ||
1246 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
1247 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1248 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); | |
1249 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1250 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1251 | ||
1252 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1253 | cpu_relax(); | |
1254 | } | |
1255 | ||
1256 | static int __init dw_probe(struct platform_device *pdev) | |
1257 | { | |
1258 | struct dw_dma_platform_data *pdata; | |
1259 | struct resource *io; | |
1260 | struct dw_dma *dw; | |
1261 | size_t size; | |
1262 | int irq; | |
1263 | int err; | |
1264 | int i; | |
1265 | ||
1266 | pdata = pdev->dev.platform_data; | |
1267 | if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1268 | return -EINVAL; | |
1269 | ||
1270 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1271 | if (!io) | |
1272 | return -EINVAL; | |
1273 | ||
1274 | irq = platform_get_irq(pdev, 0); | |
1275 | if (irq < 0) | |
1276 | return irq; | |
1277 | ||
1278 | size = sizeof(struct dw_dma); | |
1279 | size += pdata->nr_channels * sizeof(struct dw_dma_chan); | |
1280 | dw = kzalloc(size, GFP_KERNEL); | |
1281 | if (!dw) | |
1282 | return -ENOMEM; | |
1283 | ||
1284 | if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) { | |
1285 | err = -EBUSY; | |
1286 | goto err_kfree; | |
1287 | } | |
1288 | ||
3bfb1d20 HS |
1289 | dw->regs = ioremap(io->start, DW_REGLEN); |
1290 | if (!dw->regs) { | |
1291 | err = -ENOMEM; | |
1292 | goto err_release_r; | |
1293 | } | |
1294 | ||
1295 | dw->clk = clk_get(&pdev->dev, "hclk"); | |
1296 | if (IS_ERR(dw->clk)) { | |
1297 | err = PTR_ERR(dw->clk); | |
1298 | goto err_clk; | |
1299 | } | |
1300 | clk_enable(dw->clk); | |
1301 | ||
1302 | /* force dma off, just in case */ | |
1303 | dw_dma_off(dw); | |
1304 | ||
1305 | err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw); | |
1306 | if (err) | |
1307 | goto err_irq; | |
1308 | ||
1309 | platform_set_drvdata(pdev, dw); | |
1310 | ||
1311 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); | |
1312 | ||
1313 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; | |
1314 | ||
1315 | INIT_LIST_HEAD(&dw->dma.channels); | |
1316 | for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) { | |
1317 | struct dw_dma_chan *dwc = &dw->chan[i]; | |
1318 | ||
1319 | dwc->chan.device = &dw->dma; | |
1320 | dwc->chan.cookie = dwc->completed = 1; | |
1321 | dwc->chan.chan_id = i; | |
b0c3130d VK |
1322 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1323 | list_add_tail(&dwc->chan.device_node, | |
1324 | &dw->dma.channels); | |
1325 | else | |
1326 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 HS |
1327 | |
1328 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; | |
1329 | spin_lock_init(&dwc->lock); | |
1330 | dwc->mask = 1 << i; | |
1331 | ||
1332 | INIT_LIST_HEAD(&dwc->active_list); | |
1333 | INIT_LIST_HEAD(&dwc->queue); | |
1334 | INIT_LIST_HEAD(&dwc->free_list); | |
1335 | ||
1336 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1337 | } | |
1338 | ||
1339 | /* Clear/disable all interrupts on all channels. */ | |
1340 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); | |
1341 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); | |
1342 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); | |
1343 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1344 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1345 | ||
1346 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
1347 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1348 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); | |
1349 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1350 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1351 | ||
1352 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | |
1353 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1354 | if (pdata->is_private) |
1355 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1356 | dw->dma.dev = &pdev->dev; |
1357 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1358 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1359 | ||
1360 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1361 | ||
1362 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1363 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1364 | |
07934481 | 1365 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1366 | dw->dma.device_issue_pending = dwc_issue_pending; |
1367 | ||
1368 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1369 | ||
1370 | printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n", | |
dfbc9019 | 1371 | dev_name(&pdev->dev), dw->dma.chancnt); |
3bfb1d20 HS |
1372 | |
1373 | dma_async_device_register(&dw->dma); | |
1374 | ||
1375 | return 0; | |
1376 | ||
1377 | err_irq: | |
1378 | clk_disable(dw->clk); | |
1379 | clk_put(dw->clk); | |
1380 | err_clk: | |
1381 | iounmap(dw->regs); | |
1382 | dw->regs = NULL; | |
1383 | err_release_r: | |
1384 | release_resource(io); | |
1385 | err_kfree: | |
1386 | kfree(dw); | |
1387 | return err; | |
1388 | } | |
1389 | ||
1390 | static int __exit dw_remove(struct platform_device *pdev) | |
1391 | { | |
1392 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1393 | struct dw_dma_chan *dwc, *_dwc; | |
1394 | struct resource *io; | |
1395 | ||
1396 | dw_dma_off(dw); | |
1397 | dma_async_device_unregister(&dw->dma); | |
1398 | ||
1399 | free_irq(platform_get_irq(pdev, 0), dw); | |
1400 | tasklet_kill(&dw->tasklet); | |
1401 | ||
1402 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1403 | chan.device_node) { | |
1404 | list_del(&dwc->chan.device_node); | |
1405 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1406 | } | |
1407 | ||
1408 | clk_disable(dw->clk); | |
1409 | clk_put(dw->clk); | |
1410 | ||
1411 | iounmap(dw->regs); | |
1412 | dw->regs = NULL; | |
1413 | ||
1414 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1415 | release_mem_region(io->start, DW_REGLEN); | |
1416 | ||
1417 | kfree(dw); | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | static void dw_shutdown(struct platform_device *pdev) | |
1423 | { | |
1424 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1425 | ||
1426 | dw_dma_off(platform_get_drvdata(pdev)); | |
1427 | clk_disable(dw->clk); | |
1428 | } | |
1429 | ||
4a256b5f | 1430 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1431 | { |
4a256b5f | 1432 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1433 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1434 | ||
1435 | dw_dma_off(platform_get_drvdata(pdev)); | |
1436 | clk_disable(dw->clk); | |
1437 | return 0; | |
1438 | } | |
1439 | ||
4a256b5f | 1440 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1441 | { |
4a256b5f | 1442 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1443 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1444 | ||
1445 | clk_enable(dw->clk); | |
1446 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1447 | return 0; | |
3bfb1d20 HS |
1448 | } |
1449 | ||
47145210 | 1450 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1451 | .suspend_noirq = dw_suspend_noirq, |
1452 | .resume_noirq = dw_resume_noirq, | |
1453 | }; | |
1454 | ||
3bfb1d20 HS |
1455 | static struct platform_driver dw_driver = { |
1456 | .remove = __exit_p(dw_remove), | |
1457 | .shutdown = dw_shutdown, | |
3bfb1d20 HS |
1458 | .driver = { |
1459 | .name = "dw_dmac", | |
4a256b5f | 1460 | .pm = &dw_dev_pm_ops, |
3bfb1d20 HS |
1461 | }, |
1462 | }; | |
1463 | ||
1464 | static int __init dw_init(void) | |
1465 | { | |
1466 | return platform_driver_probe(&dw_driver, dw_probe); | |
1467 | } | |
cb689a70 | 1468 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1469 | |
1470 | static void __exit dw_exit(void) | |
1471 | { | |
1472 | platform_driver_unregister(&dw_driver); | |
1473 | } | |
1474 | module_exit(dw_exit); | |
1475 | ||
1476 | MODULE_LICENSE("GPL v2"); | |
1477 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
1478 | MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>"); |