Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/clk.h> |
15 | #include <linux/delay.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
f8122a82 | 18 | #include <linux/dmapool.h> |
7331205a | 19 | #include <linux/err.h> |
3bfb1d20 HS |
20 | #include <linux/init.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/module.h> | |
3bfb1d20 HS |
25 | #include <linux/slab.h> |
26 | ||
61a76496 | 27 | #include "../dmaengine.h" |
9cade1a4 | 28 | #include "internal.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
dd5720b3 AS |
36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
37 | * support descriptor writeback. | |
3bfb1d20 HS |
38 | */ |
39 | ||
78f3c9d2 AS |
40 | static inline bool is_request_line_unset(struct dw_dma_chan *dwc) |
41 | { | |
42 | return dwc->request_line == (typeof(dwc->request_line))~0; | |
43 | } | |
44 | ||
f776076b | 45 | static inline void dwc_set_masters(struct dw_dma_chan *dwc) |
5be10f34 | 46 | { |
f776076b AB |
47 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
48 | struct dw_dma_slave *dws = dwc->chan.private; | |
49 | unsigned char mmax = dw->nr_masters - 1; | |
5be10f34 | 50 | |
78f3c9d2 AS |
51 | if (!is_request_line_unset(dwc)) |
52 | return; | |
53 | ||
54 | dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws)); | |
55 | dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws)); | |
5be10f34 AS |
56 | } |
57 | ||
327e6970 | 58 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
59 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
60 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 61 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 62 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 63 | DW_DMA_MSIZE_16; \ |
495aea4b | 64 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 65 | DW_DMA_MSIZE_16; \ |
f301c062 | 66 | \ |
327e6970 VK |
67 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
68 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
69 | | DWC_CTLL_LLP_D_EN \ |
70 | | DWC_CTLL_LLP_S_EN \ | |
f776076b AB |
71 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
72 | | DWC_CTLL_SMS(_dwc->src_master)); \ | |
f301c062 | 73 | }) |
3bfb1d20 | 74 | |
3bfb1d20 HS |
75 | /* |
76 | * Number of descriptors to allocate for each channel. This should be | |
77 | * made configurable somehow; preferably, the clients (at least the | |
78 | * ones using slave transfers) should be able to give us a hint. | |
79 | */ | |
80 | #define NR_DESCS_PER_CHANNEL 64 | |
81 | ||
82 | /*----------------------------------------------------------------------*/ | |
3bfb1d20 | 83 | |
41d5e59c DW |
84 | static struct device *chan2dev(struct dma_chan *chan) |
85 | { | |
86 | return &chan->dev->device; | |
87 | } | |
41d5e59c | 88 | |
3bfb1d20 HS |
89 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
90 | { | |
e63a47a3 | 91 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
92 | } |
93 | ||
3bfb1d20 HS |
94 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
95 | { | |
96 | struct dw_desc *desc, *_desc; | |
97 | struct dw_desc *ret = NULL; | |
98 | unsigned int i = 0; | |
69cea5a0 | 99 | unsigned long flags; |
3bfb1d20 | 100 | |
69cea5a0 | 101 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 102 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 103 | i++; |
3bfb1d20 HS |
104 | if (async_tx_test_ack(&desc->txd)) { |
105 | list_del(&desc->desc_node); | |
106 | ret = desc; | |
107 | break; | |
108 | } | |
41d5e59c | 109 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 110 | } |
69cea5a0 | 111 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 112 | |
41d5e59c | 113 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
114 | |
115 | return ret; | |
116 | } | |
117 | ||
3bfb1d20 HS |
118 | /* |
119 | * Move a descriptor, including any children, to the free list. | |
120 | * `desc' must not be on any lists. | |
121 | */ | |
122 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
123 | { | |
69cea5a0 VK |
124 | unsigned long flags; |
125 | ||
3bfb1d20 HS |
126 | if (desc) { |
127 | struct dw_desc *child; | |
128 | ||
69cea5a0 | 129 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 130 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 131 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
132 | "moving child desc %p to freelist\n", |
133 | child); | |
e0bd0f8c | 134 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 135 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 136 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 137 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
138 | } |
139 | } | |
140 | ||
61e183f8 VK |
141 | static void dwc_initialize(struct dw_dma_chan *dwc) |
142 | { | |
143 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
144 | struct dw_dma_slave *dws = dwc->chan.private; | |
145 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
146 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
147 | ||
148 | if (dwc->initialized == true) | |
149 | return; | |
150 | ||
f776076b | 151 | if (dws) { |
61e183f8 VK |
152 | /* |
153 | * We need controller-specific data to set up slave | |
154 | * transfers. | |
155 | */ | |
156 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
157 | ||
158 | cfghi = dws->cfg_hi; | |
159 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf | 160 | } else { |
0fdb567f | 161 | if (dwc->direction == DMA_MEM_TO_DEV) |
f776076b | 162 | cfghi = DWC_CFGH_DST_PER(dwc->request_line); |
0fdb567f | 163 | else if (dwc->direction == DMA_DEV_TO_MEM) |
f776076b | 164 | cfghi = DWC_CFGH_SRC_PER(dwc->request_line); |
61e183f8 VK |
165 | } |
166 | ||
167 | channel_writel(dwc, CFG_LO, cfglo); | |
168 | channel_writel(dwc, CFG_HI, cfghi); | |
169 | ||
170 | /* Enable interrupts */ | |
171 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
172 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
173 | ||
174 | dwc->initialized = true; | |
175 | } | |
176 | ||
3bfb1d20 HS |
177 | /*----------------------------------------------------------------------*/ |
178 | ||
4c2d56c5 AS |
179 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
180 | { | |
181 | /* | |
182 | * We can be a lot more clever here, but this should take care | |
183 | * of the most common optimization. | |
184 | */ | |
185 | if (!(v & 7)) | |
186 | return 3; | |
187 | else if (!(v & 3)) | |
188 | return 2; | |
189 | else if (!(v & 1)) | |
190 | return 1; | |
191 | return 0; | |
192 | } | |
193 | ||
f52b36d2 | 194 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
195 | { |
196 | dev_err(chan2dev(&dwc->chan), | |
197 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
198 | channel_readl(dwc, SAR), | |
199 | channel_readl(dwc, DAR), | |
200 | channel_readl(dwc, LLP), | |
201 | channel_readl(dwc, CTL_HI), | |
202 | channel_readl(dwc, CTL_LO)); | |
203 | } | |
204 | ||
3f936207 AS |
205 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
206 | { | |
207 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
208 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
209 | cpu_relax(); | |
210 | } | |
211 | ||
1d455437 AS |
212 | /*----------------------------------------------------------------------*/ |
213 | ||
fed2574b AS |
214 | /* Perform single block transfer */ |
215 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
216 | struct dw_desc *desc) | |
217 | { | |
218 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
219 | u32 ctllo; | |
220 | ||
1d566f11 AS |
221 | /* |
222 | * Software emulation of LLP mode relies on interrupts to continue | |
223 | * multi block transfer. | |
224 | */ | |
fed2574b AS |
225 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; |
226 | ||
227 | channel_writel(dwc, SAR, desc->lli.sar); | |
228 | channel_writel(dwc, DAR, desc->lli.dar); | |
229 | channel_writel(dwc, CTL_LO, ctllo); | |
230 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
231 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
232 | |
233 | /* Move pointer to next descriptor */ | |
234 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
235 | } |
236 | ||
3bfb1d20 HS |
237 | /* Called with dwc->lock held and bh disabled */ |
238 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
239 | { | |
240 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 241 | unsigned long was_soft_llp; |
3bfb1d20 HS |
242 | |
243 | /* ASSERT: channel is idle */ | |
244 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 245 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 246 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 247 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
248 | |
249 | /* The tasklet will hopefully advance the queue... */ | |
250 | return; | |
251 | } | |
252 | ||
fed2574b AS |
253 | if (dwc->nollp) { |
254 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
255 | &dwc->flags); | |
256 | if (was_soft_llp) { | |
257 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 258 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
259 | return; |
260 | } | |
261 | ||
262 | dwc_initialize(dwc); | |
263 | ||
4702d524 | 264 | dwc->residue = first->total_len; |
f5c6a7df | 265 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 266 | |
fdf475fa | 267 | /* Submit first block */ |
fed2574b AS |
268 | dwc_do_single_block(dwc, first); |
269 | ||
270 | return; | |
271 | } | |
272 | ||
61e183f8 VK |
273 | dwc_initialize(dwc); |
274 | ||
3bfb1d20 HS |
275 | channel_writel(dwc, LLP, first->txd.phys); |
276 | channel_writel(dwc, CTL_LO, | |
277 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
278 | channel_writel(dwc, CTL_HI, 0); | |
279 | channel_set_bit(dw, CH_EN, dwc->mask); | |
280 | } | |
281 | ||
e7637c6c AS |
282 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
283 | { | |
284 | if (list_empty(&dwc->queue)) | |
285 | return; | |
286 | ||
287 | list_move(dwc->queue.next, &dwc->active_list); | |
288 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
289 | } | |
290 | ||
3bfb1d20 HS |
291 | /*----------------------------------------------------------------------*/ |
292 | ||
293 | static void | |
5fedefb8 VK |
294 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
295 | bool callback_required) | |
3bfb1d20 | 296 | { |
5fedefb8 VK |
297 | dma_async_tx_callback callback = NULL; |
298 | void *param = NULL; | |
3bfb1d20 | 299 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 300 | struct dw_desc *child; |
69cea5a0 | 301 | unsigned long flags; |
3bfb1d20 | 302 | |
41d5e59c | 303 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 304 | |
69cea5a0 | 305 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 306 | dma_cookie_complete(txd); |
5fedefb8 VK |
307 | if (callback_required) { |
308 | callback = txd->callback; | |
309 | param = txd->callback_param; | |
310 | } | |
3bfb1d20 | 311 | |
e518076e VK |
312 | /* async_tx_ack */ |
313 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
314 | async_tx_ack(&child->txd); | |
315 | async_tx_ack(&desc->txd); | |
316 | ||
e0bd0f8c | 317 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
318 | list_move(&desc->desc_node, &dwc->free_list); |
319 | ||
d38a8c62 | 320 | dma_descriptor_unmap(txd); |
69cea5a0 VK |
321 | spin_unlock_irqrestore(&dwc->lock, flags); |
322 | ||
21e93c1e | 323 | if (callback) |
3bfb1d20 HS |
324 | callback(param); |
325 | } | |
326 | ||
327 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
328 | { | |
329 | struct dw_desc *desc, *_desc; | |
330 | LIST_HEAD(list); | |
69cea5a0 | 331 | unsigned long flags; |
3bfb1d20 | 332 | |
69cea5a0 | 333 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 334 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 335 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
336 | "BUG: XFER bit set, but channel not idle!\n"); |
337 | ||
338 | /* Try to continue after resetting the channel... */ | |
3f936207 | 339 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
340 | } |
341 | ||
342 | /* | |
343 | * Submit queued descriptors ASAP, i.e. before we go through | |
344 | * the completed ones. | |
345 | */ | |
3bfb1d20 | 346 | list_splice_init(&dwc->active_list, &list); |
e7637c6c | 347 | dwc_dostart_first_queued(dwc); |
3bfb1d20 | 348 | |
69cea5a0 VK |
349 | spin_unlock_irqrestore(&dwc->lock, flags); |
350 | ||
3bfb1d20 | 351 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 352 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
353 | } |
354 | ||
4702d524 AS |
355 | /* Returns how many bytes were already received from source */ |
356 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
357 | { | |
358 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
359 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
360 | ||
361 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
362 | } | |
363 | ||
3bfb1d20 HS |
364 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
365 | { | |
366 | dma_addr_t llp; | |
367 | struct dw_desc *desc, *_desc; | |
368 | struct dw_desc *child; | |
369 | u32 status_xfer; | |
69cea5a0 | 370 | unsigned long flags; |
3bfb1d20 | 371 | |
69cea5a0 | 372 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
373 | llp = channel_readl(dwc, LLP); |
374 | status_xfer = dma_readl(dw, RAW.XFER); | |
375 | ||
376 | if (status_xfer & dwc->mask) { | |
377 | /* Everything we've submitted is done */ | |
378 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
379 | |
380 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
381 | struct list_head *head, *active = dwc->tx_node_active; |
382 | ||
383 | /* | |
384 | * We are inside first active descriptor. | |
385 | * Otherwise something is really wrong. | |
386 | */ | |
387 | desc = dwc_first_active(dwc); | |
388 | ||
389 | head = &desc->tx_list; | |
390 | if (active != head) { | |
4702d524 AS |
391 | /* Update desc to reflect last sent one */ |
392 | if (active != head->next) | |
393 | desc = to_dw_desc(active->prev); | |
394 | ||
395 | dwc->residue -= desc->len; | |
396 | ||
fdf475fa | 397 | child = to_dw_desc(active); |
77bcc497 AS |
398 | |
399 | /* Submit next block */ | |
fdf475fa | 400 | dwc_do_single_block(dwc, child); |
77bcc497 | 401 | |
fdf475fa | 402 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
403 | return; |
404 | } | |
fdf475fa | 405 | |
77bcc497 AS |
406 | /* We are done here */ |
407 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
408 | } | |
4702d524 AS |
409 | |
410 | dwc->residue = 0; | |
411 | ||
69cea5a0 VK |
412 | spin_unlock_irqrestore(&dwc->lock, flags); |
413 | ||
3bfb1d20 HS |
414 | dwc_complete_all(dw, dwc); |
415 | return; | |
416 | } | |
417 | ||
69cea5a0 | 418 | if (list_empty(&dwc->active_list)) { |
4702d524 | 419 | dwc->residue = 0; |
69cea5a0 | 420 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 421 | return; |
69cea5a0 | 422 | } |
087809fc | 423 | |
77bcc497 AS |
424 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
425 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 426 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 427 | return; |
69cea5a0 | 428 | } |
087809fc | 429 | |
5a87f0e6 | 430 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
3bfb1d20 HS |
431 | |
432 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 433 | /* Initial residue value */ |
4702d524 AS |
434 | dwc->residue = desc->total_len; |
435 | ||
75c61225 | 436 | /* Check first descriptors addr */ |
69cea5a0 VK |
437 | if (desc->txd.phys == llp) { |
438 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 439 | return; |
69cea5a0 | 440 | } |
84adccfb | 441 | |
75c61225 | 442 | /* Check first descriptors llp */ |
69cea5a0 | 443 | if (desc->lli.llp == llp) { |
3bfb1d20 | 444 | /* This one is currently in progress */ |
4702d524 | 445 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 446 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 447 | return; |
69cea5a0 | 448 | } |
3bfb1d20 | 449 | |
4702d524 AS |
450 | dwc->residue -= desc->len; |
451 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 452 | if (child->lli.llp == llp) { |
3bfb1d20 | 453 | /* Currently in progress */ |
4702d524 | 454 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 455 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 456 | return; |
69cea5a0 | 457 | } |
4702d524 AS |
458 | dwc->residue -= child->len; |
459 | } | |
3bfb1d20 HS |
460 | |
461 | /* | |
462 | * No descriptors so far seem to be in progress, i.e. | |
463 | * this one must be done. | |
464 | */ | |
69cea5a0 | 465 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 466 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 467 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
468 | } |
469 | ||
41d5e59c | 470 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
471 | "BUG: All descriptors done, but channel not idle!\n"); |
472 | ||
473 | /* Try to continue after resetting the channel... */ | |
3f936207 | 474 | dwc_chan_disable(dw, dwc); |
3bfb1d20 | 475 | |
e7637c6c | 476 | dwc_dostart_first_queued(dwc); |
69cea5a0 | 477 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
478 | } |
479 | ||
93aad1bc | 480 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 481 | { |
21d43f49 AS |
482 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
483 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
484 | } |
485 | ||
486 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
487 | { | |
488 | struct dw_desc *bad_desc; | |
489 | struct dw_desc *child; | |
69cea5a0 | 490 | unsigned long flags; |
3bfb1d20 HS |
491 | |
492 | dwc_scan_descriptors(dw, dwc); | |
493 | ||
69cea5a0 VK |
494 | spin_lock_irqsave(&dwc->lock, flags); |
495 | ||
3bfb1d20 HS |
496 | /* |
497 | * The descriptor currently at the head of the active list is | |
498 | * borked. Since we don't have any way to report errors, we'll | |
499 | * just have to scream loudly and try to carry on. | |
500 | */ | |
501 | bad_desc = dwc_first_active(dwc); | |
502 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 503 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
504 | |
505 | /* Clear the error flag and try to restart the controller */ | |
506 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
507 | if (!list_empty(&dwc->active_list)) | |
508 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
509 | ||
510 | /* | |
ba84bd71 | 511 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
512 | * when someone submits a bad physical address in a |
513 | * descriptor, we should consider ourselves lucky that the | |
514 | * controller flagged an error instead of scribbling over | |
515 | * random memory locations. | |
516 | */ | |
ba84bd71 AS |
517 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
518 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 519 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 520 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
521 | dwc_dump_lli(dwc, &child->lli); |
522 | ||
69cea5a0 VK |
523 | spin_unlock_irqrestore(&dwc->lock, flags); |
524 | ||
3bfb1d20 | 525 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 526 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
527 | } |
528 | ||
d9de4519 HCE |
529 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
530 | ||
8004cbb4 | 531 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
532 | { |
533 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
534 | return channel_readl(dwc, SAR); | |
535 | } | |
536 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
537 | ||
8004cbb4 | 538 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
539 | { |
540 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
541 | return channel_readl(dwc, DAR); | |
542 | } | |
543 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
544 | ||
75c61225 | 545 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 546 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
ff7b05f2 | 547 | u32 status_err, u32 status_xfer) |
d9de4519 | 548 | { |
69cea5a0 VK |
549 | unsigned long flags; |
550 | ||
ff7b05f2 | 551 | if (dwc->mask) { |
d9de4519 HCE |
552 | void (*callback)(void *param); |
553 | void *callback_param; | |
554 | ||
555 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
556 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
557 | |
558 | callback = dwc->cdesc->period_callback; | |
559 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
560 | |
561 | if (callback) | |
d9de4519 | 562 | callback(callback_param); |
d9de4519 HCE |
563 | } |
564 | ||
565 | /* | |
566 | * Error and transfer complete are highly unlikely, and will most | |
567 | * likely be due to a configuration error by the user. | |
568 | */ | |
569 | if (unlikely(status_err & dwc->mask) || | |
570 | unlikely(status_xfer & dwc->mask)) { | |
571 | int i; | |
572 | ||
fc61f6b4 AS |
573 | dev_err(chan2dev(&dwc->chan), |
574 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", | |
575 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
576 | |
577 | spin_lock_irqsave(&dwc->lock, flags); | |
578 | ||
1d455437 | 579 | dwc_dump_chan_regs(dwc); |
d9de4519 | 580 | |
3f936207 | 581 | dwc_chan_disable(dw, dwc); |
d9de4519 | 582 | |
75c61225 | 583 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
584 | channel_writel(dwc, LLP, 0); |
585 | channel_writel(dwc, CTL_LO, 0); | |
586 | channel_writel(dwc, CTL_HI, 0); | |
587 | ||
d9de4519 HCE |
588 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
589 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
590 | ||
591 | for (i = 0; i < dwc->cdesc->periods; i++) | |
592 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
593 | |
594 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
595 | } |
596 | } | |
597 | ||
598 | /* ------------------------------------------------------------------------- */ | |
599 | ||
3bfb1d20 HS |
600 | static void dw_dma_tasklet(unsigned long data) |
601 | { | |
602 | struct dw_dma *dw = (struct dw_dma *)data; | |
603 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
604 | u32 status_xfer; |
605 | u32 status_err; | |
606 | int i; | |
607 | ||
7fe7b2f4 | 608 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
609 | status_err = dma_readl(dw, RAW.ERROR); |
610 | ||
2e4c364e | 611 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
612 | |
613 | for (i = 0; i < dw->dma.chancnt; i++) { | |
614 | dwc = &dw->chan[i]; | |
d9de4519 | 615 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 616 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 617 | else if (status_err & (1 << i)) |
3bfb1d20 | 618 | dwc_handle_error(dw, dwc); |
77bcc497 | 619 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 620 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
621 | } |
622 | ||
623 | /* | |
ff7b05f2 | 624 | * Re-enable interrupts. |
3bfb1d20 HS |
625 | */ |
626 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
627 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
628 | } | |
629 | ||
630 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
631 | { | |
632 | struct dw_dma *dw = dev_id; | |
3783cef8 | 633 | u32 status = dma_readl(dw, STATUS_INT); |
3bfb1d20 | 634 | |
3783cef8 AS |
635 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
636 | ||
637 | /* Check if we have any interrupt from the DMAC */ | |
638 | if (!status) | |
639 | return IRQ_NONE; | |
3bfb1d20 HS |
640 | |
641 | /* | |
642 | * Just disable the interrupts. We'll turn them back on in the | |
643 | * softirq handler. | |
644 | */ | |
645 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
646 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
647 | ||
648 | status = dma_readl(dw, STATUS_INT); | |
649 | if (status) { | |
650 | dev_err(dw->dma.dev, | |
651 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
652 | status); | |
653 | ||
654 | /* Try to recover */ | |
655 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
656 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
657 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
658 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
659 | } | |
660 | ||
661 | tasklet_schedule(&dw->tasklet); | |
662 | ||
663 | return IRQ_HANDLED; | |
664 | } | |
665 | ||
666 | /*----------------------------------------------------------------------*/ | |
667 | ||
668 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
669 | { | |
670 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
671 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
672 | dma_cookie_t cookie; | |
69cea5a0 | 673 | unsigned long flags; |
3bfb1d20 | 674 | |
69cea5a0 | 675 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 676 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
677 | |
678 | /* | |
679 | * REVISIT: We should attempt to chain as many descriptors as | |
680 | * possible, perhaps even appending to those already submitted | |
681 | * for DMA. But this is hard to do in a race-free manner. | |
682 | */ | |
683 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 684 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 685 | desc->txd.cookie); |
3bfb1d20 | 686 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 687 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 688 | } else { |
2e4c364e | 689 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
690 | desc->txd.cookie); |
691 | ||
692 | list_add_tail(&desc->desc_node, &dwc->queue); | |
693 | } | |
694 | ||
69cea5a0 | 695 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
696 | |
697 | return cookie; | |
698 | } | |
699 | ||
700 | static struct dma_async_tx_descriptor * | |
701 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
702 | size_t len, unsigned long flags) | |
703 | { | |
704 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 705 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
706 | struct dw_desc *desc; |
707 | struct dw_desc *first; | |
708 | struct dw_desc *prev; | |
709 | size_t xfer_count; | |
710 | size_t offset; | |
711 | unsigned int src_width; | |
712 | unsigned int dst_width; | |
3d4f8605 | 713 | unsigned int data_width; |
3bfb1d20 HS |
714 | u32 ctllo; |
715 | ||
2f45d613 | 716 | dev_vdbg(chan2dev(chan), |
5a87f0e6 AS |
717 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
718 | &dest, &src, len, flags); | |
3bfb1d20 HS |
719 | |
720 | if (unlikely(!len)) { | |
2e4c364e | 721 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
722 | return NULL; |
723 | } | |
724 | ||
0fdb567f AS |
725 | dwc->direction = DMA_MEM_TO_MEM; |
726 | ||
f776076b AB |
727 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
728 | dw->data_width[dwc->dst_master]); | |
a0982004 | 729 | |
3d4f8605 AS |
730 | src_width = dst_width = min_t(unsigned int, data_width, |
731 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 732 | |
327e6970 | 733 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
734 | | DWC_CTLL_DST_WIDTH(dst_width) |
735 | | DWC_CTLL_SRC_WIDTH(src_width) | |
736 | | DWC_CTLL_DST_INC | |
737 | | DWC_CTLL_SRC_INC | |
738 | | DWC_CTLL_FC_M2M; | |
739 | prev = first = NULL; | |
740 | ||
741 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
742 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 743 | dwc->block_size); |
3bfb1d20 HS |
744 | |
745 | desc = dwc_desc_get(dwc); | |
746 | if (!desc) | |
747 | goto err_desc_get; | |
748 | ||
749 | desc->lli.sar = src + offset; | |
750 | desc->lli.dar = dest + offset; | |
751 | desc->lli.ctllo = ctllo; | |
752 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 753 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
754 | |
755 | if (!first) { | |
756 | first = desc; | |
757 | } else { | |
758 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 759 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 760 | &first->tx_list); |
3bfb1d20 HS |
761 | } |
762 | prev = desc; | |
763 | } | |
764 | ||
3bfb1d20 HS |
765 | if (flags & DMA_PREP_INTERRUPT) |
766 | /* Trigger interrupt after last block */ | |
767 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
768 | ||
769 | prev->lli.llp = 0; | |
3bfb1d20 | 770 | first->txd.flags = flags; |
30d38a32 | 771 | first->total_len = len; |
3bfb1d20 HS |
772 | |
773 | return &first->txd; | |
774 | ||
775 | err_desc_get: | |
776 | dwc_desc_put(dwc, first); | |
777 | return NULL; | |
778 | } | |
779 | ||
780 | static struct dma_async_tx_descriptor * | |
781 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 782 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 783 | unsigned long flags, void *context) |
3bfb1d20 HS |
784 | { |
785 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 786 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 787 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
788 | struct dw_desc *prev; |
789 | struct dw_desc *first; | |
790 | u32 ctllo; | |
791 | dma_addr_t reg; | |
792 | unsigned int reg_width; | |
793 | unsigned int mem_width; | |
a0982004 | 794 | unsigned int data_width; |
3bfb1d20 HS |
795 | unsigned int i; |
796 | struct scatterlist *sg; | |
797 | size_t total_len = 0; | |
798 | ||
2e4c364e | 799 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 800 | |
495aea4b | 801 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
802 | return NULL; |
803 | ||
0fdb567f AS |
804 | dwc->direction = direction; |
805 | ||
3bfb1d20 HS |
806 | prev = first = NULL; |
807 | ||
3bfb1d20 | 808 | switch (direction) { |
db8196df | 809 | case DMA_MEM_TO_DEV: |
327e6970 VK |
810 | reg_width = __fls(sconfig->dst_addr_width); |
811 | reg = sconfig->dst_addr; | |
812 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
813 | | DWC_CTLL_DST_WIDTH(reg_width) |
814 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
815 | | DWC_CTLL_SRC_INC); |
816 | ||
817 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
818 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
819 | ||
f776076b | 820 | data_width = dw->data_width[dwc->src_master]; |
a0982004 | 821 | |
3bfb1d20 HS |
822 | for_each_sg(sgl, sg, sg_len, i) { |
823 | struct dw_desc *desc; | |
69dc14b5 | 824 | u32 len, dlen, mem; |
3bfb1d20 | 825 | |
cbb796cc | 826 | mem = sg_dma_address(sg); |
69dc14b5 | 827 | len = sg_dma_len(sg); |
6bc711f6 | 828 | |
a0982004 AS |
829 | mem_width = min_t(unsigned int, |
830 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 831 | |
69dc14b5 | 832 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
833 | desc = dwc_desc_get(dwc); |
834 | if (!desc) { | |
41d5e59c | 835 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
836 | "not enough descriptors available\n"); |
837 | goto err_desc_get; | |
838 | } | |
839 | ||
3bfb1d20 HS |
840 | desc->lli.sar = mem; |
841 | desc->lli.dar = reg; | |
842 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
843 | if ((len >> mem_width) > dwc->block_size) { |
844 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
845 | mem += dlen; |
846 | len -= dlen; | |
847 | } else { | |
848 | dlen = len; | |
849 | len = 0; | |
850 | } | |
851 | ||
852 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 853 | desc->len = dlen; |
3bfb1d20 HS |
854 | |
855 | if (!first) { | |
856 | first = desc; | |
857 | } else { | |
858 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 859 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 860 | &first->tx_list); |
3bfb1d20 HS |
861 | } |
862 | prev = desc; | |
69dc14b5 VK |
863 | total_len += dlen; |
864 | ||
865 | if (len) | |
866 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
867 | } |
868 | break; | |
db8196df | 869 | case DMA_DEV_TO_MEM: |
327e6970 VK |
870 | reg_width = __fls(sconfig->src_addr_width); |
871 | reg = sconfig->src_addr; | |
872 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
873 | | DWC_CTLL_SRC_WIDTH(reg_width) |
874 | | DWC_CTLL_DST_INC | |
327e6970 VK |
875 | | DWC_CTLL_SRC_FIX); |
876 | ||
877 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
878 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 879 | |
f776076b | 880 | data_width = dw->data_width[dwc->dst_master]; |
a0982004 | 881 | |
3bfb1d20 HS |
882 | for_each_sg(sgl, sg, sg_len, i) { |
883 | struct dw_desc *desc; | |
69dc14b5 | 884 | u32 len, dlen, mem; |
3bfb1d20 | 885 | |
cbb796cc | 886 | mem = sg_dma_address(sg); |
3bfb1d20 | 887 | len = sg_dma_len(sg); |
6bc711f6 | 888 | |
a0982004 AS |
889 | mem_width = min_t(unsigned int, |
890 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 891 | |
69dc14b5 VK |
892 | slave_sg_fromdev_fill_desc: |
893 | desc = dwc_desc_get(dwc); | |
894 | if (!desc) { | |
895 | dev_err(chan2dev(chan), | |
896 | "not enough descriptors available\n"); | |
897 | goto err_desc_get; | |
898 | } | |
899 | ||
3bfb1d20 HS |
900 | desc->lli.sar = reg; |
901 | desc->lli.dar = mem; | |
902 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
903 | if ((len >> reg_width) > dwc->block_size) { |
904 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
905 | mem += dlen; |
906 | len -= dlen; | |
907 | } else { | |
908 | dlen = len; | |
909 | len = 0; | |
910 | } | |
911 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 912 | desc->len = dlen; |
3bfb1d20 HS |
913 | |
914 | if (!first) { | |
915 | first = desc; | |
916 | } else { | |
917 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 918 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 919 | &first->tx_list); |
3bfb1d20 HS |
920 | } |
921 | prev = desc; | |
69dc14b5 VK |
922 | total_len += dlen; |
923 | ||
924 | if (len) | |
925 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
926 | } |
927 | break; | |
928 | default: | |
929 | return NULL; | |
930 | } | |
931 | ||
932 | if (flags & DMA_PREP_INTERRUPT) | |
933 | /* Trigger interrupt after last block */ | |
934 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
935 | ||
936 | prev->lli.llp = 0; | |
30d38a32 | 937 | first->total_len = total_len; |
3bfb1d20 HS |
938 | |
939 | return &first->txd; | |
940 | ||
941 | err_desc_get: | |
942 | dwc_desc_put(dwc, first); | |
943 | return NULL; | |
944 | } | |
945 | ||
327e6970 VK |
946 | /* |
947 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
948 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
949 | * | |
950 | * NOTE: burst size 2 is not supported by controller. | |
951 | * | |
952 | * This can be done by finding least significant bit set: n & (n - 1) | |
953 | */ | |
954 | static inline void convert_burst(u32 *maxburst) | |
955 | { | |
956 | if (*maxburst > 1) | |
957 | *maxburst = fls(*maxburst) - 2; | |
958 | else | |
959 | *maxburst = 0; | |
960 | } | |
961 | ||
962 | static int | |
963 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
964 | { | |
965 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
966 | ||
495aea4b AS |
967 | /* Check if chan will be configured for slave transfers */ |
968 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
969 | return -EINVAL; |
970 | ||
971 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 972 | dwc->direction = sconfig->direction; |
327e6970 | 973 | |
f776076b | 974 | /* Take the request line from slave_id member */ |
78f3c9d2 | 975 | if (is_request_line_unset(dwc)) |
f776076b AB |
976 | dwc->request_line = sconfig->slave_id; |
977 | ||
327e6970 VK |
978 | convert_burst(&dwc->dma_sconfig.src_maxburst); |
979 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
21fe3c52 AS |
984 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
985 | { | |
986 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
123b69ab | 987 | unsigned int count = 20; /* timeout iterations */ |
21fe3c52 AS |
988 | |
989 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
123b69ab AS |
990 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
991 | udelay(2); | |
21fe3c52 AS |
992 | |
993 | dwc->paused = true; | |
994 | } | |
995 | ||
996 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
997 | { | |
998 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
999 | ||
1000 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1001 | ||
1002 | dwc->paused = false; | |
1003 | } | |
1004 | ||
05827630 LW |
1005 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1006 | unsigned long arg) | |
3bfb1d20 HS |
1007 | { |
1008 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1009 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1010 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1011 | unsigned long flags; |
3bfb1d20 HS |
1012 | LIST_HEAD(list); |
1013 | ||
a7c57cf7 LW |
1014 | if (cmd == DMA_PAUSE) { |
1015 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1016 | |
21fe3c52 | 1017 | dwc_chan_pause(dwc); |
3bfb1d20 | 1018 | |
a7c57cf7 LW |
1019 | spin_unlock_irqrestore(&dwc->lock, flags); |
1020 | } else if (cmd == DMA_RESUME) { | |
1021 | if (!dwc->paused) | |
1022 | return 0; | |
3bfb1d20 | 1023 | |
a7c57cf7 | 1024 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1025 | |
21fe3c52 | 1026 | dwc_chan_resume(dwc); |
3bfb1d20 | 1027 | |
a7c57cf7 LW |
1028 | spin_unlock_irqrestore(&dwc->lock, flags); |
1029 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1030 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1031 | |
fed2574b AS |
1032 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1033 | ||
3f936207 | 1034 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1035 | |
a5dbff11 | 1036 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1037 | |
1038 | /* active_list entries will end up before queued entries */ | |
1039 | list_splice_init(&dwc->queue, &list); | |
1040 | list_splice_init(&dwc->active_list, &list); | |
1041 | ||
1042 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1043 | ||
1044 | /* Flush all pending and queued descriptors */ | |
1045 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1046 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1047 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1048 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1049 | } else { | |
a7c57cf7 | 1050 | return -ENXIO; |
327e6970 | 1051 | } |
c3635c78 LW |
1052 | |
1053 | return 0; | |
3bfb1d20 HS |
1054 | } |
1055 | ||
4702d524 AS |
1056 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1057 | { | |
1058 | unsigned long flags; | |
1059 | u32 residue; | |
1060 | ||
1061 | spin_lock_irqsave(&dwc->lock, flags); | |
1062 | ||
1063 | residue = dwc->residue; | |
1064 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1065 | residue -= dwc_get_sent(dwc); | |
1066 | ||
1067 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1068 | return residue; | |
1069 | } | |
1070 | ||
3bfb1d20 | 1071 | static enum dma_status |
07934481 LW |
1072 | dwc_tx_status(struct dma_chan *chan, |
1073 | dma_cookie_t cookie, | |
1074 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1075 | { |
1076 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1077 | enum dma_status ret; |
3bfb1d20 | 1078 | |
96a2af41 | 1079 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1080 | if (ret == DMA_COMPLETE) |
12381dc0 | 1081 | return ret; |
3bfb1d20 | 1082 | |
12381dc0 | 1083 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 1084 | |
12381dc0 | 1085 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1086 | if (ret != DMA_COMPLETE) |
4702d524 | 1087 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1088 | |
effd5cf6 | 1089 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 1090 | return DMA_PAUSED; |
3bfb1d20 HS |
1091 | |
1092 | return ret; | |
1093 | } | |
1094 | ||
1095 | static void dwc_issue_pending(struct dma_chan *chan) | |
1096 | { | |
1097 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1098 | ||
3bfb1d20 HS |
1099 | if (!list_empty(&dwc->queue)) |
1100 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1101 | } |
1102 | ||
aa1e6f1a | 1103 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1104 | { |
1105 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1106 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1107 | struct dw_desc *desc; | |
3bfb1d20 | 1108 | int i; |
69cea5a0 | 1109 | unsigned long flags; |
3bfb1d20 | 1110 | |
2e4c364e | 1111 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1112 | |
3bfb1d20 HS |
1113 | /* ASSERT: channel is idle */ |
1114 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1115 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1116 | return -EIO; |
1117 | } | |
1118 | ||
d3ee98cd | 1119 | dma_cookie_init(chan); |
3bfb1d20 | 1120 | |
3bfb1d20 HS |
1121 | /* |
1122 | * NOTE: some controllers may have additional features that we | |
1123 | * need to initialize here, like "scatter-gather" (which | |
1124 | * doesn't mean what you think it means), and status writeback. | |
1125 | */ | |
1126 | ||
f776076b AB |
1127 | dwc_set_masters(dwc); |
1128 | ||
69cea5a0 | 1129 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1130 | i = dwc->descs_allocated; |
1131 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1132 | dma_addr_t phys; |
1133 | ||
69cea5a0 | 1134 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1135 | |
f8122a82 | 1136 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1137 | if (!desc) |
1138 | goto err_desc_alloc; | |
3bfb1d20 | 1139 | |
f8122a82 | 1140 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1141 | |
e0bd0f8c | 1142 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1143 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1144 | desc->txd.tx_submit = dwc_tx_submit; | |
1145 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1146 | desc->txd.phys = phys; |
cbd65312 | 1147 | |
3bfb1d20 HS |
1148 | dwc_desc_put(dwc, desc); |
1149 | ||
69cea5a0 | 1150 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1151 | i = ++dwc->descs_allocated; |
1152 | } | |
1153 | ||
69cea5a0 | 1154 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1155 | |
2e4c364e | 1156 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1157 | |
cbd65312 AS |
1158 | return i; |
1159 | ||
1160 | err_desc_alloc: | |
cbd65312 AS |
1161 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1162 | ||
3bfb1d20 HS |
1163 | return i; |
1164 | } | |
1165 | ||
1166 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1167 | { | |
1168 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1169 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1170 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1171 | unsigned long flags; |
3bfb1d20 HS |
1172 | LIST_HEAD(list); |
1173 | ||
2e4c364e | 1174 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1175 | dwc->descs_allocated); |
1176 | ||
1177 | /* ASSERT: channel is idle */ | |
1178 | BUG_ON(!list_empty(&dwc->active_list)); | |
1179 | BUG_ON(!list_empty(&dwc->queue)); | |
1180 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1181 | ||
69cea5a0 | 1182 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1183 | list_splice_init(&dwc->free_list, &list); |
1184 | dwc->descs_allocated = 0; | |
61e183f8 | 1185 | dwc->initialized = false; |
f776076b | 1186 | dwc->request_line = ~0; |
3bfb1d20 HS |
1187 | |
1188 | /* Disable interrupts */ | |
1189 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1190 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1191 | ||
69cea5a0 | 1192 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1193 | |
1194 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1195 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1196 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1197 | } |
1198 | ||
2e4c364e | 1199 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1200 | } |
1201 | ||
d9de4519 HCE |
1202 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1203 | ||
1204 | /** | |
1205 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1206 | * @chan: the DMA channel to start | |
1207 | * | |
1208 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1209 | * -errno on failure. | |
1210 | */ | |
1211 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1212 | { | |
1213 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1214 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1215 | unsigned long flags; |
d9de4519 HCE |
1216 | |
1217 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1218 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1219 | return -ENODEV; | |
1220 | } | |
1221 | ||
69cea5a0 | 1222 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1223 | |
75c61225 | 1224 | /* Assert channel is idle */ |
d9de4519 HCE |
1225 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
1226 | dev_err(chan2dev(&dwc->chan), | |
1227 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1228 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1229 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1230 | return -EBUSY; |
1231 | } | |
1232 | ||
d9de4519 HCE |
1233 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1234 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1235 | ||
75c61225 | 1236 | /* Setup DMAC channel registers */ |
d9de4519 HCE |
1237 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); |
1238 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1239 | channel_writel(dwc, CTL_HI, 0); | |
1240 | ||
1241 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1242 | ||
69cea5a0 | 1243 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1244 | |
1245 | return 0; | |
1246 | } | |
1247 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1248 | ||
1249 | /** | |
1250 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1251 | * @chan: the DMA channel to stop | |
1252 | * | |
1253 | * Must be called with soft interrupts disabled. | |
1254 | */ | |
1255 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1256 | { | |
1257 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1258 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1259 | unsigned long flags; |
d9de4519 | 1260 | |
69cea5a0 | 1261 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1262 | |
3f936207 | 1263 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1264 | |
69cea5a0 | 1265 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1266 | } |
1267 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1268 | ||
1269 | /** | |
1270 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1271 | * @chan: the DMA channel to prepare | |
1272 | * @buf_addr: physical DMA address where the buffer starts | |
1273 | * @buf_len: total number of bytes for the entire buffer | |
1274 | * @period_len: number of bytes for each period | |
1275 | * @direction: transfer direction, to or from device | |
1276 | * | |
1277 | * Must be called before trying to start the transfer. Returns a valid struct | |
1278 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1279 | */ | |
1280 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1281 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1282 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1283 | { |
1284 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1285 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1286 | struct dw_cyclic_desc *cdesc; |
1287 | struct dw_cyclic_desc *retval = NULL; | |
1288 | struct dw_desc *desc; | |
1289 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1290 | unsigned long was_cyclic; |
1291 | unsigned int reg_width; | |
1292 | unsigned int periods; | |
1293 | unsigned int i; | |
69cea5a0 | 1294 | unsigned long flags; |
d9de4519 | 1295 | |
69cea5a0 | 1296 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1297 | if (dwc->nollp) { |
1298 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1299 | dev_dbg(chan2dev(&dwc->chan), | |
1300 | "channel doesn't support LLP transfers\n"); | |
1301 | return ERR_PTR(-EINVAL); | |
1302 | } | |
1303 | ||
d9de4519 | 1304 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1305 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1306 | dev_dbg(chan2dev(&dwc->chan), |
1307 | "queue and/or active list are not empty\n"); | |
1308 | return ERR_PTR(-EBUSY); | |
1309 | } | |
1310 | ||
1311 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1312 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1313 | if (was_cyclic) { |
1314 | dev_dbg(chan2dev(&dwc->chan), | |
1315 | "channel already prepared for cyclic DMA\n"); | |
1316 | return ERR_PTR(-EBUSY); | |
1317 | } | |
1318 | ||
1319 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1320 | |
f44b92f4 AS |
1321 | if (unlikely(!is_slave_direction(direction))) |
1322 | goto out_err; | |
1323 | ||
0fdb567f AS |
1324 | dwc->direction = direction; |
1325 | ||
327e6970 VK |
1326 | if (direction == DMA_MEM_TO_DEV) |
1327 | reg_width = __ffs(sconfig->dst_addr_width); | |
1328 | else | |
1329 | reg_width = __ffs(sconfig->src_addr_width); | |
1330 | ||
d9de4519 HCE |
1331 | periods = buf_len / period_len; |
1332 | ||
1333 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1334 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1335 | goto out_err; |
1336 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1337 | goto out_err; | |
1338 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1339 | goto out_err; | |
d9de4519 HCE |
1340 | |
1341 | retval = ERR_PTR(-ENOMEM); | |
1342 | ||
1343 | if (periods > NR_DESCS_PER_CHANNEL) | |
1344 | goto out_err; | |
1345 | ||
1346 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1347 | if (!cdesc) | |
1348 | goto out_err; | |
1349 | ||
1350 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1351 | if (!cdesc->desc) | |
1352 | goto out_err_alloc; | |
1353 | ||
1354 | for (i = 0; i < periods; i++) { | |
1355 | desc = dwc_desc_get(dwc); | |
1356 | if (!desc) | |
1357 | goto out_err_desc_get; | |
1358 | ||
1359 | switch (direction) { | |
db8196df | 1360 | case DMA_MEM_TO_DEV: |
327e6970 | 1361 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1362 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1363 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1364 | | DWC_CTLL_DST_WIDTH(reg_width) |
1365 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1366 | | DWC_CTLL_DST_FIX | |
1367 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1368 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1369 | |
1370 | desc->lli.ctllo |= sconfig->device_fc ? | |
1371 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1372 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1373 | ||
d9de4519 | 1374 | break; |
db8196df | 1375 | case DMA_DEV_TO_MEM: |
d9de4519 | 1376 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1377 | desc->lli.sar = sconfig->src_addr; |
1378 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1379 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1380 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1381 | | DWC_CTLL_DST_INC | |
1382 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1383 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1384 | |
1385 | desc->lli.ctllo |= sconfig->device_fc ? | |
1386 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1387 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1388 | ||
d9de4519 HCE |
1389 | break; |
1390 | default: | |
1391 | break; | |
1392 | } | |
1393 | ||
1394 | desc->lli.ctlhi = (period_len >> reg_width); | |
1395 | cdesc->desc[i] = desc; | |
1396 | ||
f8122a82 | 1397 | if (last) |
d9de4519 | 1398 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1399 | |
1400 | last = desc; | |
1401 | } | |
1402 | ||
75c61225 | 1403 | /* Let's make a cyclic list */ |
d9de4519 | 1404 | last->lli.llp = cdesc->desc[0]->txd.phys; |
d9de4519 | 1405 | |
5a87f0e6 AS |
1406 | dev_dbg(chan2dev(&dwc->chan), |
1407 | "cyclic prepared buf %pad len %zu period %zu periods %d\n", | |
1408 | &buf_addr, buf_len, period_len, periods); | |
d9de4519 HCE |
1409 | |
1410 | cdesc->periods = periods; | |
1411 | dwc->cdesc = cdesc; | |
1412 | ||
1413 | return cdesc; | |
1414 | ||
1415 | out_err_desc_get: | |
1416 | while (i--) | |
1417 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1418 | out_err_alloc: | |
1419 | kfree(cdesc); | |
1420 | out_err: | |
1421 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1422 | return (struct dw_cyclic_desc *)retval; | |
1423 | } | |
1424 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1425 | ||
1426 | /** | |
1427 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1428 | * @chan: the DMA channel to free | |
1429 | */ | |
1430 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1431 | { | |
1432 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1433 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1434 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1435 | int i; | |
69cea5a0 | 1436 | unsigned long flags; |
d9de4519 | 1437 | |
2e4c364e | 1438 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1439 | |
1440 | if (!cdesc) | |
1441 | return; | |
1442 | ||
69cea5a0 | 1443 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1444 | |
3f936207 | 1445 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1446 | |
d9de4519 HCE |
1447 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1448 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1449 | ||
69cea5a0 | 1450 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1451 | |
1452 | for (i = 0; i < cdesc->periods; i++) | |
1453 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1454 | ||
1455 | kfree(cdesc->desc); | |
1456 | kfree(cdesc); | |
1457 | ||
1458 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1459 | } | |
1460 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1461 | ||
3bfb1d20 HS |
1462 | /*----------------------------------------------------------------------*/ |
1463 | ||
1464 | static void dw_dma_off(struct dw_dma *dw) | |
1465 | { | |
61e183f8 VK |
1466 | int i; |
1467 | ||
3bfb1d20 HS |
1468 | dma_writel(dw, CFG, 0); |
1469 | ||
1470 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1471 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1472 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1473 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1474 | ||
1475 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1476 | cpu_relax(); | |
61e183f8 VK |
1477 | |
1478 | for (i = 0; i < dw->dma.chancnt; i++) | |
1479 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1480 | } |
1481 | ||
9cade1a4 | 1482 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
a9ddb575 | 1483 | { |
3bfb1d20 | 1484 | struct dw_dma *dw; |
482c67ea AS |
1485 | bool autocfg; |
1486 | unsigned int dw_params; | |
1487 | unsigned int nr_channels; | |
4a63a8b3 | 1488 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1489 | int err; |
1490 | int i; | |
1491 | ||
000871ce AS |
1492 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
1493 | if (!dw) | |
1494 | return -ENOMEM; | |
1495 | ||
1496 | dw->regs = chip->regs; | |
1497 | chip->dw = dw; | |
1498 | ||
d2f78e95 AS |
1499 | dw->clk = devm_clk_get(chip->dev, "hclk"); |
1500 | if (IS_ERR(dw->clk)) | |
1501 | return PTR_ERR(dw->clk); | |
8be4f523 AS |
1502 | err = clk_prepare_enable(dw->clk); |
1503 | if (err) | |
1504 | return err; | |
d2f78e95 | 1505 | |
9cade1a4 | 1506 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); |
482c67ea AS |
1507 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; |
1508 | ||
9cade1a4 | 1509 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
123de543 AS |
1510 | |
1511 | if (!pdata && autocfg) { | |
9cade1a4 | 1512 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
8be4f523 AS |
1513 | if (!pdata) { |
1514 | err = -ENOMEM; | |
1515 | goto err_pdata; | |
1516 | } | |
123de543 AS |
1517 | |
1518 | /* Fill platform data with the default values */ | |
1519 | pdata->is_private = true; | |
1520 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1521 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
8be4f523 AS |
1522 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
1523 | err = -EINVAL; | |
1524 | goto err_pdata; | |
1525 | } | |
123de543 | 1526 | |
482c67ea AS |
1527 | if (autocfg) |
1528 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1529 | else | |
1530 | nr_channels = pdata->nr_channels; | |
1531 | ||
000871ce AS |
1532 | dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan), |
1533 | GFP_KERNEL); | |
8be4f523 AS |
1534 | if (!dw->chan) { |
1535 | err = -ENOMEM; | |
1536 | goto err_pdata; | |
1537 | } | |
3bfb1d20 | 1538 | |
75c61225 | 1539 | /* Get hardware configuration parameters */ |
a0982004 | 1540 | if (autocfg) { |
4a63a8b3 AS |
1541 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1542 | ||
a0982004 AS |
1543 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1544 | for (i = 0; i < dw->nr_masters; i++) { | |
1545 | dw->data_width[i] = | |
1546 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1547 | } | |
1548 | } else { | |
1549 | dw->nr_masters = pdata->nr_masters; | |
1550 | memcpy(dw->data_width, pdata->data_width, 4); | |
1551 | } | |
1552 | ||
11f932ec | 1553 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1554 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1555 | |
75c61225 | 1556 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1557 | dw_dma_off(dw); |
1558 | ||
75c61225 | 1559 | /* Disable BLOCK interrupts as well */ |
236b106f AS |
1560 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
1561 | ||
75c61225 | 1562 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
9cade1a4 | 1563 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
f8122a82 AS |
1564 | sizeof(struct dw_desc), 4, 0); |
1565 | if (!dw->desc_pool) { | |
9cade1a4 | 1566 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
8be4f523 AS |
1567 | err = -ENOMEM; |
1568 | goto err_pdata; | |
f8122a82 AS |
1569 | } |
1570 | ||
3bfb1d20 HS |
1571 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1572 | ||
97977f75 AS |
1573 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
1574 | "dw_dmac", dw); | |
1575 | if (err) | |
8be4f523 | 1576 | goto err_pdata; |
97977f75 | 1577 | |
3bfb1d20 | 1578 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1579 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1580 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1581 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1582 | |
1583 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1584 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1585 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1586 | list_add_tail(&dwc->chan.device_node, | |
1587 | &dw->dma.channels); | |
1588 | else | |
1589 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1590 | |
93317e8e VK |
1591 | /* 7 is highest priority & 0 is lowest. */ |
1592 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1593 | dwc->priority = r; |
93317e8e VK |
1594 | else |
1595 | dwc->priority = i; | |
1596 | ||
3bfb1d20 HS |
1597 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1598 | spin_lock_init(&dwc->lock); | |
1599 | dwc->mask = 1 << i; | |
1600 | ||
1601 | INIT_LIST_HEAD(&dwc->active_list); | |
1602 | INIT_LIST_HEAD(&dwc->queue); | |
1603 | INIT_LIST_HEAD(&dwc->free_list); | |
1604 | ||
1605 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1606 | |
0fdb567f | 1607 | dwc->direction = DMA_TRANS_NONE; |
f776076b | 1608 | dwc->request_line = ~0; |
a0982004 | 1609 | |
75c61225 | 1610 | /* Hardware configuration */ |
fed2574b AS |
1611 | if (autocfg) { |
1612 | unsigned int dwc_params; | |
9cade1a4 | 1613 | void __iomem *addr = chip->regs + r * sizeof(u32); |
fed2574b | 1614 | |
9cade1a4 | 1615 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
fed2574b | 1616 | |
9cade1a4 AS |
1617 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1618 | dwc_params); | |
985a6c7d | 1619 | |
1d566f11 AS |
1620 | /* |
1621 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1622 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1623 | * up to 0x0a for 4095. |
1624 | */ | |
4a63a8b3 AS |
1625 | dwc->block_size = |
1626 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1627 | dwc->nollp = |
1628 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1629 | } else { | |
4a63a8b3 | 1630 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1631 | |
1632 | /* Check if channel supports multi block transfer */ | |
1633 | channel_writel(dwc, LLP, 0xfffffffc); | |
1634 | dwc->nollp = | |
1635 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1636 | channel_writel(dwc, LLP, 0); | |
1637 | } | |
3bfb1d20 HS |
1638 | } |
1639 | ||
11f932ec | 1640 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1641 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1642 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1643 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1644 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1645 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1646 | ||
3bfb1d20 HS |
1647 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1648 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1649 | if (pdata->is_private) |
1650 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
9cade1a4 | 1651 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1652 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1653 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1654 | ||
1655 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1656 | ||
1657 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1658 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1659 | |
07934481 | 1660 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1661 | dw->dma.device_issue_pending = dwc_issue_pending; |
1662 | ||
1663 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1664 | ||
1222934e AS |
1665 | err = dma_async_device_register(&dw->dma); |
1666 | if (err) | |
1667 | goto err_dma_register; | |
1668 | ||
9cade1a4 | 1669 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
21d43f49 | 1670 | nr_channels); |
3bfb1d20 | 1671 | |
3bfb1d20 | 1672 | return 0; |
8be4f523 | 1673 | |
1222934e AS |
1674 | err_dma_register: |
1675 | free_irq(chip->irq, dw); | |
8be4f523 AS |
1676 | err_pdata: |
1677 | clk_disable_unprepare(dw->clk); | |
1678 | return err; | |
3bfb1d20 | 1679 | } |
9cade1a4 | 1680 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1681 | |
9cade1a4 | 1682 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1683 | { |
9cade1a4 | 1684 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1685 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 HS |
1686 | |
1687 | dw_dma_off(dw); | |
1688 | dma_async_device_unregister(&dw->dma); | |
1689 | ||
97977f75 | 1690 | free_irq(chip->irq, dw); |
3bfb1d20 HS |
1691 | tasklet_kill(&dw->tasklet); |
1692 | ||
1693 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1694 | chan.device_node) { | |
1695 | list_del(&dwc->chan.device_node); | |
1696 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1697 | } | |
1698 | ||
8be4f523 AS |
1699 | clk_disable_unprepare(dw->clk); |
1700 | ||
3bfb1d20 HS |
1701 | return 0; |
1702 | } | |
9cade1a4 | 1703 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1704 | |
9cade1a4 | 1705 | void dw_dma_shutdown(struct dw_dma_chip *chip) |
3bfb1d20 | 1706 | { |
9cade1a4 | 1707 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1708 | |
6168d567 | 1709 | dw_dma_off(dw); |
3075528d | 1710 | clk_disable_unprepare(dw->clk); |
3bfb1d20 | 1711 | } |
9cade1a4 | 1712 | EXPORT_SYMBOL_GPL(dw_dma_shutdown); |
3bfb1d20 | 1713 | |
9cade1a4 AS |
1714 | #ifdef CONFIG_PM_SLEEP |
1715 | ||
1716 | int dw_dma_suspend(struct dw_dma_chip *chip) | |
3bfb1d20 | 1717 | { |
9cade1a4 | 1718 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1719 | |
6168d567 | 1720 | dw_dma_off(dw); |
3075528d | 1721 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1722 | |
3bfb1d20 HS |
1723 | return 0; |
1724 | } | |
9cade1a4 | 1725 | EXPORT_SYMBOL_GPL(dw_dma_suspend); |
3bfb1d20 | 1726 | |
9cade1a4 | 1727 | int dw_dma_resume(struct dw_dma_chip *chip) |
3bfb1d20 | 1728 | { |
9cade1a4 | 1729 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1730 | |
3075528d | 1731 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1732 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1733 | |
3bfb1d20 | 1734 | return 0; |
3bfb1d20 | 1735 | } |
9cade1a4 | 1736 | EXPORT_SYMBOL_GPL(dw_dma_resume); |
3bfb1d20 | 1737 | |
9cade1a4 | 1738 | #endif /* CONFIG_PM_SLEEP */ |
3bfb1d20 HS |
1739 | |
1740 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1741 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1742 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1743 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |