Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/clk.h> |
15 | #include <linux/delay.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
f8122a82 | 18 | #include <linux/dmapool.h> |
7331205a | 19 | #include <linux/err.h> |
3bfb1d20 HS |
20 | #include <linux/init.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/module.h> | |
3bfb1d20 HS |
25 | #include <linux/slab.h> |
26 | ||
61a76496 | 27 | #include "../dmaengine.h" |
9cade1a4 | 28 | #include "internal.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
dd5720b3 AS |
36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
37 | * support descriptor writeback. | |
3bfb1d20 HS |
38 | */ |
39 | ||
78f3c9d2 AS |
40 | static inline bool is_request_line_unset(struct dw_dma_chan *dwc) |
41 | { | |
42 | return dwc->request_line == (typeof(dwc->request_line))~0; | |
43 | } | |
44 | ||
f776076b | 45 | static inline void dwc_set_masters(struct dw_dma_chan *dwc) |
5be10f34 | 46 | { |
f776076b AB |
47 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
48 | struct dw_dma_slave *dws = dwc->chan.private; | |
49 | unsigned char mmax = dw->nr_masters - 1; | |
5be10f34 | 50 | |
78f3c9d2 AS |
51 | if (!is_request_line_unset(dwc)) |
52 | return; | |
53 | ||
54 | dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws)); | |
55 | dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws)); | |
5be10f34 AS |
56 | } |
57 | ||
327e6970 | 58 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
59 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
60 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 61 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 62 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 63 | DW_DMA_MSIZE_16; \ |
495aea4b | 64 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 65 | DW_DMA_MSIZE_16; \ |
f301c062 | 66 | \ |
327e6970 VK |
67 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
68 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
69 | | DWC_CTLL_LLP_D_EN \ |
70 | | DWC_CTLL_LLP_S_EN \ | |
f776076b AB |
71 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
72 | | DWC_CTLL_SMS(_dwc->src_master)); \ | |
f301c062 | 73 | }) |
3bfb1d20 | 74 | |
3bfb1d20 HS |
75 | /* |
76 | * Number of descriptors to allocate for each channel. This should be | |
77 | * made configurable somehow; preferably, the clients (at least the | |
78 | * ones using slave transfers) should be able to give us a hint. | |
79 | */ | |
80 | #define NR_DESCS_PER_CHANNEL 64 | |
81 | ||
82 | /*----------------------------------------------------------------------*/ | |
3bfb1d20 | 83 | |
41d5e59c DW |
84 | static struct device *chan2dev(struct dma_chan *chan) |
85 | { | |
86 | return &chan->dev->device; | |
87 | } | |
41d5e59c | 88 | |
3bfb1d20 HS |
89 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
90 | { | |
e63a47a3 | 91 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
92 | } |
93 | ||
3bfb1d20 HS |
94 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
95 | { | |
96 | struct dw_desc *desc, *_desc; | |
97 | struct dw_desc *ret = NULL; | |
98 | unsigned int i = 0; | |
69cea5a0 | 99 | unsigned long flags; |
3bfb1d20 | 100 | |
69cea5a0 | 101 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 102 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 103 | i++; |
3bfb1d20 HS |
104 | if (async_tx_test_ack(&desc->txd)) { |
105 | list_del(&desc->desc_node); | |
106 | ret = desc; | |
107 | break; | |
108 | } | |
41d5e59c | 109 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 110 | } |
69cea5a0 | 111 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 112 | |
41d5e59c | 113 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
114 | |
115 | return ret; | |
116 | } | |
117 | ||
3bfb1d20 HS |
118 | /* |
119 | * Move a descriptor, including any children, to the free list. | |
120 | * `desc' must not be on any lists. | |
121 | */ | |
122 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
123 | { | |
69cea5a0 VK |
124 | unsigned long flags; |
125 | ||
3bfb1d20 HS |
126 | if (desc) { |
127 | struct dw_desc *child; | |
128 | ||
69cea5a0 | 129 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 130 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 131 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
132 | "moving child desc %p to freelist\n", |
133 | child); | |
e0bd0f8c | 134 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 135 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 136 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 137 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
138 | } |
139 | } | |
140 | ||
61e183f8 VK |
141 | static void dwc_initialize(struct dw_dma_chan *dwc) |
142 | { | |
143 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
144 | struct dw_dma_slave *dws = dwc->chan.private; | |
145 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
146 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
147 | ||
148 | if (dwc->initialized == true) | |
149 | return; | |
150 | ||
f776076b | 151 | if (dws) { |
61e183f8 VK |
152 | /* |
153 | * We need controller-specific data to set up slave | |
154 | * transfers. | |
155 | */ | |
156 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
157 | ||
158 | cfghi = dws->cfg_hi; | |
159 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf | 160 | } else { |
0fdb567f | 161 | if (dwc->direction == DMA_MEM_TO_DEV) |
f776076b | 162 | cfghi = DWC_CFGH_DST_PER(dwc->request_line); |
0fdb567f | 163 | else if (dwc->direction == DMA_DEV_TO_MEM) |
f776076b | 164 | cfghi = DWC_CFGH_SRC_PER(dwc->request_line); |
61e183f8 VK |
165 | } |
166 | ||
167 | channel_writel(dwc, CFG_LO, cfglo); | |
168 | channel_writel(dwc, CFG_HI, cfghi); | |
169 | ||
170 | /* Enable interrupts */ | |
171 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
172 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
173 | ||
174 | dwc->initialized = true; | |
175 | } | |
176 | ||
3bfb1d20 HS |
177 | /*----------------------------------------------------------------------*/ |
178 | ||
4c2d56c5 AS |
179 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
180 | { | |
181 | /* | |
182 | * We can be a lot more clever here, but this should take care | |
183 | * of the most common optimization. | |
184 | */ | |
185 | if (!(v & 7)) | |
186 | return 3; | |
187 | else if (!(v & 3)) | |
188 | return 2; | |
189 | else if (!(v & 1)) | |
190 | return 1; | |
191 | return 0; | |
192 | } | |
193 | ||
f52b36d2 | 194 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
195 | { |
196 | dev_err(chan2dev(&dwc->chan), | |
197 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
198 | channel_readl(dwc, SAR), | |
199 | channel_readl(dwc, DAR), | |
200 | channel_readl(dwc, LLP), | |
201 | channel_readl(dwc, CTL_HI), | |
202 | channel_readl(dwc, CTL_LO)); | |
203 | } | |
204 | ||
3f936207 AS |
205 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
206 | { | |
207 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
208 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
209 | cpu_relax(); | |
210 | } | |
211 | ||
1d455437 AS |
212 | /*----------------------------------------------------------------------*/ |
213 | ||
fed2574b AS |
214 | /* Perform single block transfer */ |
215 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
216 | struct dw_desc *desc) | |
217 | { | |
218 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
219 | u32 ctllo; | |
220 | ||
1d566f11 AS |
221 | /* |
222 | * Software emulation of LLP mode relies on interrupts to continue | |
223 | * multi block transfer. | |
224 | */ | |
fed2574b AS |
225 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; |
226 | ||
227 | channel_writel(dwc, SAR, desc->lli.sar); | |
228 | channel_writel(dwc, DAR, desc->lli.dar); | |
229 | channel_writel(dwc, CTL_LO, ctllo); | |
230 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
231 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
232 | |
233 | /* Move pointer to next descriptor */ | |
234 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
235 | } |
236 | ||
3bfb1d20 HS |
237 | /* Called with dwc->lock held and bh disabled */ |
238 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
239 | { | |
240 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 241 | unsigned long was_soft_llp; |
3bfb1d20 HS |
242 | |
243 | /* ASSERT: channel is idle */ | |
244 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 245 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 246 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 247 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
248 | |
249 | /* The tasklet will hopefully advance the queue... */ | |
250 | return; | |
251 | } | |
252 | ||
fed2574b AS |
253 | if (dwc->nollp) { |
254 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
255 | &dwc->flags); | |
256 | if (was_soft_llp) { | |
257 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 258 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
259 | return; |
260 | } | |
261 | ||
262 | dwc_initialize(dwc); | |
263 | ||
4702d524 | 264 | dwc->residue = first->total_len; |
f5c6a7df | 265 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 266 | |
fdf475fa | 267 | /* Submit first block */ |
fed2574b AS |
268 | dwc_do_single_block(dwc, first); |
269 | ||
270 | return; | |
271 | } | |
272 | ||
61e183f8 VK |
273 | dwc_initialize(dwc); |
274 | ||
3bfb1d20 HS |
275 | channel_writel(dwc, LLP, first->txd.phys); |
276 | channel_writel(dwc, CTL_LO, | |
277 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
278 | channel_writel(dwc, CTL_HI, 0); | |
279 | channel_set_bit(dw, CH_EN, dwc->mask); | |
280 | } | |
281 | ||
282 | /*----------------------------------------------------------------------*/ | |
283 | ||
284 | static void | |
5fedefb8 VK |
285 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
286 | bool callback_required) | |
3bfb1d20 | 287 | { |
5fedefb8 VK |
288 | dma_async_tx_callback callback = NULL; |
289 | void *param = NULL; | |
3bfb1d20 | 290 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 291 | struct dw_desc *child; |
69cea5a0 | 292 | unsigned long flags; |
3bfb1d20 | 293 | |
41d5e59c | 294 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 295 | |
69cea5a0 | 296 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 297 | dma_cookie_complete(txd); |
5fedefb8 VK |
298 | if (callback_required) { |
299 | callback = txd->callback; | |
300 | param = txd->callback_param; | |
301 | } | |
3bfb1d20 | 302 | |
e518076e VK |
303 | /* async_tx_ack */ |
304 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
305 | async_tx_ack(&child->txd); | |
306 | async_tx_ack(&desc->txd); | |
307 | ||
e0bd0f8c | 308 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
309 | list_move(&desc->desc_node, &dwc->free_list); |
310 | ||
d38a8c62 | 311 | dma_descriptor_unmap(txd); |
69cea5a0 VK |
312 | spin_unlock_irqrestore(&dwc->lock, flags); |
313 | ||
21e93c1e | 314 | if (callback) |
3bfb1d20 HS |
315 | callback(param); |
316 | } | |
317 | ||
318 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
319 | { | |
320 | struct dw_desc *desc, *_desc; | |
321 | LIST_HEAD(list); | |
69cea5a0 | 322 | unsigned long flags; |
3bfb1d20 | 323 | |
69cea5a0 | 324 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 325 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 326 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
327 | "BUG: XFER bit set, but channel not idle!\n"); |
328 | ||
329 | /* Try to continue after resetting the channel... */ | |
3f936207 | 330 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
331 | } |
332 | ||
333 | /* | |
334 | * Submit queued descriptors ASAP, i.e. before we go through | |
335 | * the completed ones. | |
336 | */ | |
3bfb1d20 | 337 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
338 | if (!list_empty(&dwc->queue)) { |
339 | list_move(dwc->queue.next, &dwc->active_list); | |
340 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
341 | } | |
3bfb1d20 | 342 | |
69cea5a0 VK |
343 | spin_unlock_irqrestore(&dwc->lock, flags); |
344 | ||
3bfb1d20 | 345 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 346 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
347 | } |
348 | ||
4702d524 AS |
349 | /* Returns how many bytes were already received from source */ |
350 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
351 | { | |
352 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
353 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
354 | ||
355 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
356 | } | |
357 | ||
3bfb1d20 HS |
358 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
359 | { | |
360 | dma_addr_t llp; | |
361 | struct dw_desc *desc, *_desc; | |
362 | struct dw_desc *child; | |
363 | u32 status_xfer; | |
69cea5a0 | 364 | unsigned long flags; |
3bfb1d20 | 365 | |
69cea5a0 | 366 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
367 | llp = channel_readl(dwc, LLP); |
368 | status_xfer = dma_readl(dw, RAW.XFER); | |
369 | ||
370 | if (status_xfer & dwc->mask) { | |
371 | /* Everything we've submitted is done */ | |
372 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
373 | |
374 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
375 | struct list_head *head, *active = dwc->tx_node_active; |
376 | ||
377 | /* | |
378 | * We are inside first active descriptor. | |
379 | * Otherwise something is really wrong. | |
380 | */ | |
381 | desc = dwc_first_active(dwc); | |
382 | ||
383 | head = &desc->tx_list; | |
384 | if (active != head) { | |
4702d524 AS |
385 | /* Update desc to reflect last sent one */ |
386 | if (active != head->next) | |
387 | desc = to_dw_desc(active->prev); | |
388 | ||
389 | dwc->residue -= desc->len; | |
390 | ||
fdf475fa | 391 | child = to_dw_desc(active); |
77bcc497 AS |
392 | |
393 | /* Submit next block */ | |
fdf475fa | 394 | dwc_do_single_block(dwc, child); |
77bcc497 | 395 | |
fdf475fa | 396 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
397 | return; |
398 | } | |
fdf475fa | 399 | |
77bcc497 AS |
400 | /* We are done here */ |
401 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
402 | } | |
4702d524 AS |
403 | |
404 | dwc->residue = 0; | |
405 | ||
69cea5a0 VK |
406 | spin_unlock_irqrestore(&dwc->lock, flags); |
407 | ||
3bfb1d20 HS |
408 | dwc_complete_all(dw, dwc); |
409 | return; | |
410 | } | |
411 | ||
69cea5a0 | 412 | if (list_empty(&dwc->active_list)) { |
4702d524 | 413 | dwc->residue = 0; |
69cea5a0 | 414 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 415 | return; |
69cea5a0 | 416 | } |
087809fc | 417 | |
77bcc497 AS |
418 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
419 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 420 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 421 | return; |
69cea5a0 | 422 | } |
087809fc | 423 | |
5a87f0e6 | 424 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
3bfb1d20 HS |
425 | |
426 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 427 | /* Initial residue value */ |
4702d524 AS |
428 | dwc->residue = desc->total_len; |
429 | ||
75c61225 | 430 | /* Check first descriptors addr */ |
69cea5a0 VK |
431 | if (desc->txd.phys == llp) { |
432 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 433 | return; |
69cea5a0 | 434 | } |
84adccfb | 435 | |
75c61225 | 436 | /* Check first descriptors llp */ |
69cea5a0 | 437 | if (desc->lli.llp == llp) { |
3bfb1d20 | 438 | /* This one is currently in progress */ |
4702d524 | 439 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 440 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 441 | return; |
69cea5a0 | 442 | } |
3bfb1d20 | 443 | |
4702d524 AS |
444 | dwc->residue -= desc->len; |
445 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 446 | if (child->lli.llp == llp) { |
3bfb1d20 | 447 | /* Currently in progress */ |
4702d524 | 448 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 449 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 450 | return; |
69cea5a0 | 451 | } |
4702d524 AS |
452 | dwc->residue -= child->len; |
453 | } | |
3bfb1d20 HS |
454 | |
455 | /* | |
456 | * No descriptors so far seem to be in progress, i.e. | |
457 | * this one must be done. | |
458 | */ | |
69cea5a0 | 459 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 460 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 461 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
462 | } |
463 | ||
41d5e59c | 464 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
465 | "BUG: All descriptors done, but channel not idle!\n"); |
466 | ||
467 | /* Try to continue after resetting the channel... */ | |
3f936207 | 468 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
469 | |
470 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
471 | list_move(dwc->queue.next, &dwc->active_list); |
472 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 473 | } |
69cea5a0 | 474 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
475 | } |
476 | ||
93aad1bc | 477 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 478 | { |
21d43f49 AS |
479 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
480 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
481 | } |
482 | ||
483 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
484 | { | |
485 | struct dw_desc *bad_desc; | |
486 | struct dw_desc *child; | |
69cea5a0 | 487 | unsigned long flags; |
3bfb1d20 HS |
488 | |
489 | dwc_scan_descriptors(dw, dwc); | |
490 | ||
69cea5a0 VK |
491 | spin_lock_irqsave(&dwc->lock, flags); |
492 | ||
3bfb1d20 HS |
493 | /* |
494 | * The descriptor currently at the head of the active list is | |
495 | * borked. Since we don't have any way to report errors, we'll | |
496 | * just have to scream loudly and try to carry on. | |
497 | */ | |
498 | bad_desc = dwc_first_active(dwc); | |
499 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 500 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
501 | |
502 | /* Clear the error flag and try to restart the controller */ | |
503 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
504 | if (!list_empty(&dwc->active_list)) | |
505 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
506 | ||
507 | /* | |
ba84bd71 | 508 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
509 | * when someone submits a bad physical address in a |
510 | * descriptor, we should consider ourselves lucky that the | |
511 | * controller flagged an error instead of scribbling over | |
512 | * random memory locations. | |
513 | */ | |
ba84bd71 AS |
514 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
515 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 516 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 517 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
518 | dwc_dump_lli(dwc, &child->lli); |
519 | ||
69cea5a0 VK |
520 | spin_unlock_irqrestore(&dwc->lock, flags); |
521 | ||
3bfb1d20 | 522 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 523 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
524 | } |
525 | ||
d9de4519 HCE |
526 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
527 | ||
8004cbb4 | 528 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
529 | { |
530 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
531 | return channel_readl(dwc, SAR); | |
532 | } | |
533 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
534 | ||
8004cbb4 | 535 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
536 | { |
537 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
538 | return channel_readl(dwc, DAR); | |
539 | } | |
540 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
541 | ||
75c61225 | 542 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 543 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
ff7b05f2 | 544 | u32 status_err, u32 status_xfer) |
d9de4519 | 545 | { |
69cea5a0 VK |
546 | unsigned long flags; |
547 | ||
ff7b05f2 | 548 | if (dwc->mask) { |
d9de4519 HCE |
549 | void (*callback)(void *param); |
550 | void *callback_param; | |
551 | ||
552 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
553 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
554 | |
555 | callback = dwc->cdesc->period_callback; | |
556 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
557 | |
558 | if (callback) | |
d9de4519 | 559 | callback(callback_param); |
d9de4519 HCE |
560 | } |
561 | ||
562 | /* | |
563 | * Error and transfer complete are highly unlikely, and will most | |
564 | * likely be due to a configuration error by the user. | |
565 | */ | |
566 | if (unlikely(status_err & dwc->mask) || | |
567 | unlikely(status_xfer & dwc->mask)) { | |
568 | int i; | |
569 | ||
fc61f6b4 AS |
570 | dev_err(chan2dev(&dwc->chan), |
571 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", | |
572 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
573 | |
574 | spin_lock_irqsave(&dwc->lock, flags); | |
575 | ||
1d455437 | 576 | dwc_dump_chan_regs(dwc); |
d9de4519 | 577 | |
3f936207 | 578 | dwc_chan_disable(dw, dwc); |
d9de4519 | 579 | |
75c61225 | 580 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
581 | channel_writel(dwc, LLP, 0); |
582 | channel_writel(dwc, CTL_LO, 0); | |
583 | channel_writel(dwc, CTL_HI, 0); | |
584 | ||
d9de4519 HCE |
585 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
586 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
587 | ||
588 | for (i = 0; i < dwc->cdesc->periods; i++) | |
589 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
590 | |
591 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
592 | } |
593 | } | |
594 | ||
595 | /* ------------------------------------------------------------------------- */ | |
596 | ||
3bfb1d20 HS |
597 | static void dw_dma_tasklet(unsigned long data) |
598 | { | |
599 | struct dw_dma *dw = (struct dw_dma *)data; | |
600 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
601 | u32 status_xfer; |
602 | u32 status_err; | |
603 | int i; | |
604 | ||
7fe7b2f4 | 605 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
606 | status_err = dma_readl(dw, RAW.ERROR); |
607 | ||
2e4c364e | 608 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
609 | |
610 | for (i = 0; i < dw->dma.chancnt; i++) { | |
611 | dwc = &dw->chan[i]; | |
d9de4519 | 612 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 613 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 614 | else if (status_err & (1 << i)) |
3bfb1d20 | 615 | dwc_handle_error(dw, dwc); |
77bcc497 | 616 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 617 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
618 | } |
619 | ||
620 | /* | |
ff7b05f2 | 621 | * Re-enable interrupts. |
3bfb1d20 HS |
622 | */ |
623 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
624 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
625 | } | |
626 | ||
627 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
628 | { | |
629 | struct dw_dma *dw = dev_id; | |
3783cef8 | 630 | u32 status = dma_readl(dw, STATUS_INT); |
3bfb1d20 | 631 | |
3783cef8 AS |
632 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
633 | ||
634 | /* Check if we have any interrupt from the DMAC */ | |
635 | if (!status) | |
636 | return IRQ_NONE; | |
3bfb1d20 HS |
637 | |
638 | /* | |
639 | * Just disable the interrupts. We'll turn them back on in the | |
640 | * softirq handler. | |
641 | */ | |
642 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
643 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
644 | ||
645 | status = dma_readl(dw, STATUS_INT); | |
646 | if (status) { | |
647 | dev_err(dw->dma.dev, | |
648 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
649 | status); | |
650 | ||
651 | /* Try to recover */ | |
652 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
653 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
654 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
655 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
656 | } | |
657 | ||
658 | tasklet_schedule(&dw->tasklet); | |
659 | ||
660 | return IRQ_HANDLED; | |
661 | } | |
662 | ||
663 | /*----------------------------------------------------------------------*/ | |
664 | ||
665 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
666 | { | |
667 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
668 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
669 | dma_cookie_t cookie; | |
69cea5a0 | 670 | unsigned long flags; |
3bfb1d20 | 671 | |
69cea5a0 | 672 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 673 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
674 | |
675 | /* | |
676 | * REVISIT: We should attempt to chain as many descriptors as | |
677 | * possible, perhaps even appending to those already submitted | |
678 | * for DMA. But this is hard to do in a race-free manner. | |
679 | */ | |
680 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 681 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 682 | desc->txd.cookie); |
3bfb1d20 | 683 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 684 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 685 | } else { |
2e4c364e | 686 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
687 | desc->txd.cookie); |
688 | ||
689 | list_add_tail(&desc->desc_node, &dwc->queue); | |
690 | } | |
691 | ||
69cea5a0 | 692 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
693 | |
694 | return cookie; | |
695 | } | |
696 | ||
697 | static struct dma_async_tx_descriptor * | |
698 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
699 | size_t len, unsigned long flags) | |
700 | { | |
701 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 702 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
703 | struct dw_desc *desc; |
704 | struct dw_desc *first; | |
705 | struct dw_desc *prev; | |
706 | size_t xfer_count; | |
707 | size_t offset; | |
708 | unsigned int src_width; | |
709 | unsigned int dst_width; | |
3d4f8605 | 710 | unsigned int data_width; |
3bfb1d20 HS |
711 | u32 ctllo; |
712 | ||
2f45d613 | 713 | dev_vdbg(chan2dev(chan), |
5a87f0e6 AS |
714 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
715 | &dest, &src, len, flags); | |
3bfb1d20 HS |
716 | |
717 | if (unlikely(!len)) { | |
2e4c364e | 718 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
719 | return NULL; |
720 | } | |
721 | ||
0fdb567f AS |
722 | dwc->direction = DMA_MEM_TO_MEM; |
723 | ||
f776076b AB |
724 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
725 | dw->data_width[dwc->dst_master]); | |
a0982004 | 726 | |
3d4f8605 AS |
727 | src_width = dst_width = min_t(unsigned int, data_width, |
728 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 729 | |
327e6970 | 730 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
731 | | DWC_CTLL_DST_WIDTH(dst_width) |
732 | | DWC_CTLL_SRC_WIDTH(src_width) | |
733 | | DWC_CTLL_DST_INC | |
734 | | DWC_CTLL_SRC_INC | |
735 | | DWC_CTLL_FC_M2M; | |
736 | prev = first = NULL; | |
737 | ||
738 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
739 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 740 | dwc->block_size); |
3bfb1d20 HS |
741 | |
742 | desc = dwc_desc_get(dwc); | |
743 | if (!desc) | |
744 | goto err_desc_get; | |
745 | ||
746 | desc->lli.sar = src + offset; | |
747 | desc->lli.dar = dest + offset; | |
748 | desc->lli.ctllo = ctllo; | |
749 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 750 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
751 | |
752 | if (!first) { | |
753 | first = desc; | |
754 | } else { | |
755 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 756 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 757 | &first->tx_list); |
3bfb1d20 HS |
758 | } |
759 | prev = desc; | |
760 | } | |
761 | ||
3bfb1d20 HS |
762 | if (flags & DMA_PREP_INTERRUPT) |
763 | /* Trigger interrupt after last block */ | |
764 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
765 | ||
766 | prev->lli.llp = 0; | |
3bfb1d20 | 767 | first->txd.flags = flags; |
30d38a32 | 768 | first->total_len = len; |
3bfb1d20 HS |
769 | |
770 | return &first->txd; | |
771 | ||
772 | err_desc_get: | |
773 | dwc_desc_put(dwc, first); | |
774 | return NULL; | |
775 | } | |
776 | ||
777 | static struct dma_async_tx_descriptor * | |
778 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 779 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 780 | unsigned long flags, void *context) |
3bfb1d20 HS |
781 | { |
782 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 783 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 784 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
785 | struct dw_desc *prev; |
786 | struct dw_desc *first; | |
787 | u32 ctllo; | |
788 | dma_addr_t reg; | |
789 | unsigned int reg_width; | |
790 | unsigned int mem_width; | |
a0982004 | 791 | unsigned int data_width; |
3bfb1d20 HS |
792 | unsigned int i; |
793 | struct scatterlist *sg; | |
794 | size_t total_len = 0; | |
795 | ||
2e4c364e | 796 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 797 | |
495aea4b | 798 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
799 | return NULL; |
800 | ||
0fdb567f AS |
801 | dwc->direction = direction; |
802 | ||
3bfb1d20 HS |
803 | prev = first = NULL; |
804 | ||
3bfb1d20 | 805 | switch (direction) { |
db8196df | 806 | case DMA_MEM_TO_DEV: |
327e6970 VK |
807 | reg_width = __fls(sconfig->dst_addr_width); |
808 | reg = sconfig->dst_addr; | |
809 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
810 | | DWC_CTLL_DST_WIDTH(reg_width) |
811 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
812 | | DWC_CTLL_SRC_INC); |
813 | ||
814 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
815 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
816 | ||
f776076b | 817 | data_width = dw->data_width[dwc->src_master]; |
a0982004 | 818 | |
3bfb1d20 HS |
819 | for_each_sg(sgl, sg, sg_len, i) { |
820 | struct dw_desc *desc; | |
69dc14b5 | 821 | u32 len, dlen, mem; |
3bfb1d20 | 822 | |
cbb796cc | 823 | mem = sg_dma_address(sg); |
69dc14b5 | 824 | len = sg_dma_len(sg); |
6bc711f6 | 825 | |
a0982004 AS |
826 | mem_width = min_t(unsigned int, |
827 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 828 | |
69dc14b5 | 829 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
830 | desc = dwc_desc_get(dwc); |
831 | if (!desc) { | |
41d5e59c | 832 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
833 | "not enough descriptors available\n"); |
834 | goto err_desc_get; | |
835 | } | |
836 | ||
3bfb1d20 HS |
837 | desc->lli.sar = mem; |
838 | desc->lli.dar = reg; | |
839 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
840 | if ((len >> mem_width) > dwc->block_size) { |
841 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
842 | mem += dlen; |
843 | len -= dlen; | |
844 | } else { | |
845 | dlen = len; | |
846 | len = 0; | |
847 | } | |
848 | ||
849 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 850 | desc->len = dlen; |
3bfb1d20 HS |
851 | |
852 | if (!first) { | |
853 | first = desc; | |
854 | } else { | |
855 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 856 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 857 | &first->tx_list); |
3bfb1d20 HS |
858 | } |
859 | prev = desc; | |
69dc14b5 VK |
860 | total_len += dlen; |
861 | ||
862 | if (len) | |
863 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
864 | } |
865 | break; | |
db8196df | 866 | case DMA_DEV_TO_MEM: |
327e6970 VK |
867 | reg_width = __fls(sconfig->src_addr_width); |
868 | reg = sconfig->src_addr; | |
869 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
870 | | DWC_CTLL_SRC_WIDTH(reg_width) |
871 | | DWC_CTLL_DST_INC | |
327e6970 VK |
872 | | DWC_CTLL_SRC_FIX); |
873 | ||
874 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
875 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 876 | |
f776076b | 877 | data_width = dw->data_width[dwc->dst_master]; |
a0982004 | 878 | |
3bfb1d20 HS |
879 | for_each_sg(sgl, sg, sg_len, i) { |
880 | struct dw_desc *desc; | |
69dc14b5 | 881 | u32 len, dlen, mem; |
3bfb1d20 | 882 | |
cbb796cc | 883 | mem = sg_dma_address(sg); |
3bfb1d20 | 884 | len = sg_dma_len(sg); |
6bc711f6 | 885 | |
a0982004 AS |
886 | mem_width = min_t(unsigned int, |
887 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 888 | |
69dc14b5 VK |
889 | slave_sg_fromdev_fill_desc: |
890 | desc = dwc_desc_get(dwc); | |
891 | if (!desc) { | |
892 | dev_err(chan2dev(chan), | |
893 | "not enough descriptors available\n"); | |
894 | goto err_desc_get; | |
895 | } | |
896 | ||
3bfb1d20 HS |
897 | desc->lli.sar = reg; |
898 | desc->lli.dar = mem; | |
899 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
900 | if ((len >> reg_width) > dwc->block_size) { |
901 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
902 | mem += dlen; |
903 | len -= dlen; | |
904 | } else { | |
905 | dlen = len; | |
906 | len = 0; | |
907 | } | |
908 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 909 | desc->len = dlen; |
3bfb1d20 HS |
910 | |
911 | if (!first) { | |
912 | first = desc; | |
913 | } else { | |
914 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 915 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 916 | &first->tx_list); |
3bfb1d20 HS |
917 | } |
918 | prev = desc; | |
69dc14b5 VK |
919 | total_len += dlen; |
920 | ||
921 | if (len) | |
922 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
923 | } |
924 | break; | |
925 | default: | |
926 | return NULL; | |
927 | } | |
928 | ||
929 | if (flags & DMA_PREP_INTERRUPT) | |
930 | /* Trigger interrupt after last block */ | |
931 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
932 | ||
933 | prev->lli.llp = 0; | |
30d38a32 | 934 | first->total_len = total_len; |
3bfb1d20 HS |
935 | |
936 | return &first->txd; | |
937 | ||
938 | err_desc_get: | |
939 | dwc_desc_put(dwc, first); | |
940 | return NULL; | |
941 | } | |
942 | ||
327e6970 VK |
943 | /* |
944 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
945 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
946 | * | |
947 | * NOTE: burst size 2 is not supported by controller. | |
948 | * | |
949 | * This can be done by finding least significant bit set: n & (n - 1) | |
950 | */ | |
951 | static inline void convert_burst(u32 *maxburst) | |
952 | { | |
953 | if (*maxburst > 1) | |
954 | *maxburst = fls(*maxburst) - 2; | |
955 | else | |
956 | *maxburst = 0; | |
957 | } | |
958 | ||
959 | static int | |
960 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
961 | { | |
962 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
963 | ||
495aea4b AS |
964 | /* Check if chan will be configured for slave transfers */ |
965 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
966 | return -EINVAL; |
967 | ||
968 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 969 | dwc->direction = sconfig->direction; |
327e6970 | 970 | |
f776076b | 971 | /* Take the request line from slave_id member */ |
78f3c9d2 | 972 | if (is_request_line_unset(dwc)) |
f776076b AB |
973 | dwc->request_line = sconfig->slave_id; |
974 | ||
327e6970 VK |
975 | convert_burst(&dwc->dma_sconfig.src_maxburst); |
976 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
21fe3c52 AS |
981 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
982 | { | |
983 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
123b69ab | 984 | unsigned int count = 20; /* timeout iterations */ |
21fe3c52 AS |
985 | |
986 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
123b69ab AS |
987 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
988 | udelay(2); | |
21fe3c52 AS |
989 | |
990 | dwc->paused = true; | |
991 | } | |
992 | ||
993 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
994 | { | |
995 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
996 | ||
997 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
998 | ||
999 | dwc->paused = false; | |
1000 | } | |
1001 | ||
05827630 LW |
1002 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1003 | unsigned long arg) | |
3bfb1d20 HS |
1004 | { |
1005 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1006 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1007 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1008 | unsigned long flags; |
3bfb1d20 HS |
1009 | LIST_HEAD(list); |
1010 | ||
a7c57cf7 LW |
1011 | if (cmd == DMA_PAUSE) { |
1012 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1013 | |
21fe3c52 | 1014 | dwc_chan_pause(dwc); |
3bfb1d20 | 1015 | |
a7c57cf7 LW |
1016 | spin_unlock_irqrestore(&dwc->lock, flags); |
1017 | } else if (cmd == DMA_RESUME) { | |
1018 | if (!dwc->paused) | |
1019 | return 0; | |
3bfb1d20 | 1020 | |
a7c57cf7 | 1021 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1022 | |
21fe3c52 | 1023 | dwc_chan_resume(dwc); |
3bfb1d20 | 1024 | |
a7c57cf7 LW |
1025 | spin_unlock_irqrestore(&dwc->lock, flags); |
1026 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1027 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1028 | |
fed2574b AS |
1029 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1030 | ||
3f936207 | 1031 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1032 | |
a5dbff11 | 1033 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1034 | |
1035 | /* active_list entries will end up before queued entries */ | |
1036 | list_splice_init(&dwc->queue, &list); | |
1037 | list_splice_init(&dwc->active_list, &list); | |
1038 | ||
1039 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1040 | ||
1041 | /* Flush all pending and queued descriptors */ | |
1042 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1043 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1044 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1045 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1046 | } else { | |
a7c57cf7 | 1047 | return -ENXIO; |
327e6970 | 1048 | } |
c3635c78 LW |
1049 | |
1050 | return 0; | |
3bfb1d20 HS |
1051 | } |
1052 | ||
4702d524 AS |
1053 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1054 | { | |
1055 | unsigned long flags; | |
1056 | u32 residue; | |
1057 | ||
1058 | spin_lock_irqsave(&dwc->lock, flags); | |
1059 | ||
1060 | residue = dwc->residue; | |
1061 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1062 | residue -= dwc_get_sent(dwc); | |
1063 | ||
1064 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1065 | return residue; | |
1066 | } | |
1067 | ||
3bfb1d20 | 1068 | static enum dma_status |
07934481 LW |
1069 | dwc_tx_status(struct dma_chan *chan, |
1070 | dma_cookie_t cookie, | |
1071 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1072 | { |
1073 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1074 | enum dma_status ret; |
3bfb1d20 | 1075 | |
96a2af41 | 1076 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1077 | if (ret == DMA_COMPLETE) |
12381dc0 | 1078 | return ret; |
3bfb1d20 | 1079 | |
12381dc0 | 1080 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 1081 | |
12381dc0 | 1082 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1083 | if (ret != DMA_COMPLETE) |
4702d524 | 1084 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1085 | |
effd5cf6 | 1086 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 1087 | return DMA_PAUSED; |
3bfb1d20 HS |
1088 | |
1089 | return ret; | |
1090 | } | |
1091 | ||
1092 | static void dwc_issue_pending(struct dma_chan *chan) | |
1093 | { | |
1094 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1095 | ||
3bfb1d20 HS |
1096 | if (!list_empty(&dwc->queue)) |
1097 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1098 | } |
1099 | ||
aa1e6f1a | 1100 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1101 | { |
1102 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1103 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1104 | struct dw_desc *desc; | |
3bfb1d20 | 1105 | int i; |
69cea5a0 | 1106 | unsigned long flags; |
3bfb1d20 | 1107 | |
2e4c364e | 1108 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1109 | |
3bfb1d20 HS |
1110 | /* ASSERT: channel is idle */ |
1111 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1112 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1113 | return -EIO; |
1114 | } | |
1115 | ||
d3ee98cd | 1116 | dma_cookie_init(chan); |
3bfb1d20 | 1117 | |
3bfb1d20 HS |
1118 | /* |
1119 | * NOTE: some controllers may have additional features that we | |
1120 | * need to initialize here, like "scatter-gather" (which | |
1121 | * doesn't mean what you think it means), and status writeback. | |
1122 | */ | |
1123 | ||
f776076b AB |
1124 | dwc_set_masters(dwc); |
1125 | ||
69cea5a0 | 1126 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1127 | i = dwc->descs_allocated; |
1128 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1129 | dma_addr_t phys; |
1130 | ||
69cea5a0 | 1131 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1132 | |
f8122a82 | 1133 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1134 | if (!desc) |
1135 | goto err_desc_alloc; | |
3bfb1d20 | 1136 | |
f8122a82 | 1137 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1138 | |
e0bd0f8c | 1139 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1140 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1141 | desc->txd.tx_submit = dwc_tx_submit; | |
1142 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1143 | desc->txd.phys = phys; |
cbd65312 | 1144 | |
3bfb1d20 HS |
1145 | dwc_desc_put(dwc, desc); |
1146 | ||
69cea5a0 | 1147 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1148 | i = ++dwc->descs_allocated; |
1149 | } | |
1150 | ||
69cea5a0 | 1151 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1152 | |
2e4c364e | 1153 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1154 | |
cbd65312 AS |
1155 | return i; |
1156 | ||
1157 | err_desc_alloc: | |
cbd65312 AS |
1158 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1159 | ||
3bfb1d20 HS |
1160 | return i; |
1161 | } | |
1162 | ||
1163 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1164 | { | |
1165 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1166 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1167 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1168 | unsigned long flags; |
3bfb1d20 HS |
1169 | LIST_HEAD(list); |
1170 | ||
2e4c364e | 1171 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1172 | dwc->descs_allocated); |
1173 | ||
1174 | /* ASSERT: channel is idle */ | |
1175 | BUG_ON(!list_empty(&dwc->active_list)); | |
1176 | BUG_ON(!list_empty(&dwc->queue)); | |
1177 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1178 | ||
69cea5a0 | 1179 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1180 | list_splice_init(&dwc->free_list, &list); |
1181 | dwc->descs_allocated = 0; | |
61e183f8 | 1182 | dwc->initialized = false; |
f776076b | 1183 | dwc->request_line = ~0; |
3bfb1d20 HS |
1184 | |
1185 | /* Disable interrupts */ | |
1186 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1187 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1188 | ||
69cea5a0 | 1189 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1190 | |
1191 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1192 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1193 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1194 | } |
1195 | ||
2e4c364e | 1196 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1197 | } |
1198 | ||
d9de4519 HCE |
1199 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1200 | ||
1201 | /** | |
1202 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1203 | * @chan: the DMA channel to start | |
1204 | * | |
1205 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1206 | * -errno on failure. | |
1207 | */ | |
1208 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1209 | { | |
1210 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1211 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1212 | unsigned long flags; |
d9de4519 HCE |
1213 | |
1214 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1215 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1216 | return -ENODEV; | |
1217 | } | |
1218 | ||
69cea5a0 | 1219 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1220 | |
75c61225 | 1221 | /* Assert channel is idle */ |
d9de4519 HCE |
1222 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
1223 | dev_err(chan2dev(&dwc->chan), | |
1224 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1225 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1226 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1227 | return -EBUSY; |
1228 | } | |
1229 | ||
d9de4519 HCE |
1230 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1231 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1232 | ||
75c61225 | 1233 | /* Setup DMAC channel registers */ |
d9de4519 HCE |
1234 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); |
1235 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1236 | channel_writel(dwc, CTL_HI, 0); | |
1237 | ||
1238 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1239 | ||
69cea5a0 | 1240 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1241 | |
1242 | return 0; | |
1243 | } | |
1244 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1245 | ||
1246 | /** | |
1247 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1248 | * @chan: the DMA channel to stop | |
1249 | * | |
1250 | * Must be called with soft interrupts disabled. | |
1251 | */ | |
1252 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1253 | { | |
1254 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1255 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1256 | unsigned long flags; |
d9de4519 | 1257 | |
69cea5a0 | 1258 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1259 | |
3f936207 | 1260 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1261 | |
69cea5a0 | 1262 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1263 | } |
1264 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1265 | ||
1266 | /** | |
1267 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1268 | * @chan: the DMA channel to prepare | |
1269 | * @buf_addr: physical DMA address where the buffer starts | |
1270 | * @buf_len: total number of bytes for the entire buffer | |
1271 | * @period_len: number of bytes for each period | |
1272 | * @direction: transfer direction, to or from device | |
1273 | * | |
1274 | * Must be called before trying to start the transfer. Returns a valid struct | |
1275 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1276 | */ | |
1277 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1278 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1279 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1280 | { |
1281 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1282 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1283 | struct dw_cyclic_desc *cdesc; |
1284 | struct dw_cyclic_desc *retval = NULL; | |
1285 | struct dw_desc *desc; | |
1286 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1287 | unsigned long was_cyclic; |
1288 | unsigned int reg_width; | |
1289 | unsigned int periods; | |
1290 | unsigned int i; | |
69cea5a0 | 1291 | unsigned long flags; |
d9de4519 | 1292 | |
69cea5a0 | 1293 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1294 | if (dwc->nollp) { |
1295 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1296 | dev_dbg(chan2dev(&dwc->chan), | |
1297 | "channel doesn't support LLP transfers\n"); | |
1298 | return ERR_PTR(-EINVAL); | |
1299 | } | |
1300 | ||
d9de4519 | 1301 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1302 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1303 | dev_dbg(chan2dev(&dwc->chan), |
1304 | "queue and/or active list are not empty\n"); | |
1305 | return ERR_PTR(-EBUSY); | |
1306 | } | |
1307 | ||
1308 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1309 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1310 | if (was_cyclic) { |
1311 | dev_dbg(chan2dev(&dwc->chan), | |
1312 | "channel already prepared for cyclic DMA\n"); | |
1313 | return ERR_PTR(-EBUSY); | |
1314 | } | |
1315 | ||
1316 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1317 | |
f44b92f4 AS |
1318 | if (unlikely(!is_slave_direction(direction))) |
1319 | goto out_err; | |
1320 | ||
0fdb567f AS |
1321 | dwc->direction = direction; |
1322 | ||
327e6970 VK |
1323 | if (direction == DMA_MEM_TO_DEV) |
1324 | reg_width = __ffs(sconfig->dst_addr_width); | |
1325 | else | |
1326 | reg_width = __ffs(sconfig->src_addr_width); | |
1327 | ||
d9de4519 HCE |
1328 | periods = buf_len / period_len; |
1329 | ||
1330 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1331 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1332 | goto out_err; |
1333 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1334 | goto out_err; | |
1335 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1336 | goto out_err; | |
d9de4519 HCE |
1337 | |
1338 | retval = ERR_PTR(-ENOMEM); | |
1339 | ||
1340 | if (periods > NR_DESCS_PER_CHANNEL) | |
1341 | goto out_err; | |
1342 | ||
1343 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1344 | if (!cdesc) | |
1345 | goto out_err; | |
1346 | ||
1347 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1348 | if (!cdesc->desc) | |
1349 | goto out_err_alloc; | |
1350 | ||
1351 | for (i = 0; i < periods; i++) { | |
1352 | desc = dwc_desc_get(dwc); | |
1353 | if (!desc) | |
1354 | goto out_err_desc_get; | |
1355 | ||
1356 | switch (direction) { | |
db8196df | 1357 | case DMA_MEM_TO_DEV: |
327e6970 | 1358 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1359 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1360 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1361 | | DWC_CTLL_DST_WIDTH(reg_width) |
1362 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1363 | | DWC_CTLL_DST_FIX | |
1364 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1365 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1366 | |
1367 | desc->lli.ctllo |= sconfig->device_fc ? | |
1368 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1369 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1370 | ||
d9de4519 | 1371 | break; |
db8196df | 1372 | case DMA_DEV_TO_MEM: |
d9de4519 | 1373 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1374 | desc->lli.sar = sconfig->src_addr; |
1375 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1376 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1377 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1378 | | DWC_CTLL_DST_INC | |
1379 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1380 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1381 | |
1382 | desc->lli.ctllo |= sconfig->device_fc ? | |
1383 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1384 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1385 | ||
d9de4519 HCE |
1386 | break; |
1387 | default: | |
1388 | break; | |
1389 | } | |
1390 | ||
1391 | desc->lli.ctlhi = (period_len >> reg_width); | |
1392 | cdesc->desc[i] = desc; | |
1393 | ||
f8122a82 | 1394 | if (last) |
d9de4519 | 1395 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1396 | |
1397 | last = desc; | |
1398 | } | |
1399 | ||
75c61225 | 1400 | /* Let's make a cyclic list */ |
d9de4519 | 1401 | last->lli.llp = cdesc->desc[0]->txd.phys; |
d9de4519 | 1402 | |
5a87f0e6 AS |
1403 | dev_dbg(chan2dev(&dwc->chan), |
1404 | "cyclic prepared buf %pad len %zu period %zu periods %d\n", | |
1405 | &buf_addr, buf_len, period_len, periods); | |
d9de4519 HCE |
1406 | |
1407 | cdesc->periods = periods; | |
1408 | dwc->cdesc = cdesc; | |
1409 | ||
1410 | return cdesc; | |
1411 | ||
1412 | out_err_desc_get: | |
1413 | while (i--) | |
1414 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1415 | out_err_alloc: | |
1416 | kfree(cdesc); | |
1417 | out_err: | |
1418 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1419 | return (struct dw_cyclic_desc *)retval; | |
1420 | } | |
1421 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1422 | ||
1423 | /** | |
1424 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1425 | * @chan: the DMA channel to free | |
1426 | */ | |
1427 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1428 | { | |
1429 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1430 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1431 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1432 | int i; | |
69cea5a0 | 1433 | unsigned long flags; |
d9de4519 | 1434 | |
2e4c364e | 1435 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1436 | |
1437 | if (!cdesc) | |
1438 | return; | |
1439 | ||
69cea5a0 | 1440 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1441 | |
3f936207 | 1442 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1443 | |
d9de4519 HCE |
1444 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1445 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1446 | ||
69cea5a0 | 1447 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1448 | |
1449 | for (i = 0; i < cdesc->periods; i++) | |
1450 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1451 | ||
1452 | kfree(cdesc->desc); | |
1453 | kfree(cdesc); | |
1454 | ||
1455 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1456 | } | |
1457 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1458 | ||
3bfb1d20 HS |
1459 | /*----------------------------------------------------------------------*/ |
1460 | ||
1461 | static void dw_dma_off(struct dw_dma *dw) | |
1462 | { | |
61e183f8 VK |
1463 | int i; |
1464 | ||
3bfb1d20 HS |
1465 | dma_writel(dw, CFG, 0); |
1466 | ||
1467 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1468 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1469 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1470 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1471 | ||
1472 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1473 | cpu_relax(); | |
61e183f8 VK |
1474 | |
1475 | for (i = 0; i < dw->dma.chancnt; i++) | |
1476 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1477 | } |
1478 | ||
9cade1a4 | 1479 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
a9ddb575 | 1480 | { |
3bfb1d20 | 1481 | struct dw_dma *dw; |
482c67ea AS |
1482 | bool autocfg; |
1483 | unsigned int dw_params; | |
1484 | unsigned int nr_channels; | |
4a63a8b3 | 1485 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1486 | int err; |
1487 | int i; | |
1488 | ||
000871ce AS |
1489 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
1490 | if (!dw) | |
1491 | return -ENOMEM; | |
1492 | ||
1493 | dw->regs = chip->regs; | |
1494 | chip->dw = dw; | |
1495 | ||
d2f78e95 AS |
1496 | dw->clk = devm_clk_get(chip->dev, "hclk"); |
1497 | if (IS_ERR(dw->clk)) | |
1498 | return PTR_ERR(dw->clk); | |
8be4f523 AS |
1499 | err = clk_prepare_enable(dw->clk); |
1500 | if (err) | |
1501 | return err; | |
d2f78e95 | 1502 | |
9cade1a4 | 1503 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); |
482c67ea AS |
1504 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; |
1505 | ||
9cade1a4 | 1506 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
123de543 AS |
1507 | |
1508 | if (!pdata && autocfg) { | |
9cade1a4 | 1509 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
8be4f523 AS |
1510 | if (!pdata) { |
1511 | err = -ENOMEM; | |
1512 | goto err_pdata; | |
1513 | } | |
123de543 AS |
1514 | |
1515 | /* Fill platform data with the default values */ | |
1516 | pdata->is_private = true; | |
1517 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1518 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
8be4f523 AS |
1519 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
1520 | err = -EINVAL; | |
1521 | goto err_pdata; | |
1522 | } | |
123de543 | 1523 | |
482c67ea AS |
1524 | if (autocfg) |
1525 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1526 | else | |
1527 | nr_channels = pdata->nr_channels; | |
1528 | ||
000871ce AS |
1529 | dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan), |
1530 | GFP_KERNEL); | |
8be4f523 AS |
1531 | if (!dw->chan) { |
1532 | err = -ENOMEM; | |
1533 | goto err_pdata; | |
1534 | } | |
3bfb1d20 | 1535 | |
75c61225 | 1536 | /* Get hardware configuration parameters */ |
a0982004 | 1537 | if (autocfg) { |
4a63a8b3 AS |
1538 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1539 | ||
a0982004 AS |
1540 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1541 | for (i = 0; i < dw->nr_masters; i++) { | |
1542 | dw->data_width[i] = | |
1543 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1544 | } | |
1545 | } else { | |
1546 | dw->nr_masters = pdata->nr_masters; | |
1547 | memcpy(dw->data_width, pdata->data_width, 4); | |
1548 | } | |
1549 | ||
11f932ec | 1550 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1551 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1552 | |
75c61225 | 1553 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1554 | dw_dma_off(dw); |
1555 | ||
75c61225 | 1556 | /* Disable BLOCK interrupts as well */ |
236b106f AS |
1557 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
1558 | ||
75c61225 | 1559 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
9cade1a4 | 1560 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
f8122a82 AS |
1561 | sizeof(struct dw_desc), 4, 0); |
1562 | if (!dw->desc_pool) { | |
9cade1a4 | 1563 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
8be4f523 AS |
1564 | err = -ENOMEM; |
1565 | goto err_pdata; | |
f8122a82 AS |
1566 | } |
1567 | ||
3bfb1d20 HS |
1568 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1569 | ||
97977f75 AS |
1570 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
1571 | "dw_dmac", dw); | |
1572 | if (err) | |
8be4f523 | 1573 | goto err_pdata; |
97977f75 | 1574 | |
3bfb1d20 | 1575 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1576 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1577 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1578 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1579 | |
1580 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1581 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1582 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1583 | list_add_tail(&dwc->chan.device_node, | |
1584 | &dw->dma.channels); | |
1585 | else | |
1586 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1587 | |
93317e8e VK |
1588 | /* 7 is highest priority & 0 is lowest. */ |
1589 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1590 | dwc->priority = r; |
93317e8e VK |
1591 | else |
1592 | dwc->priority = i; | |
1593 | ||
3bfb1d20 HS |
1594 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1595 | spin_lock_init(&dwc->lock); | |
1596 | dwc->mask = 1 << i; | |
1597 | ||
1598 | INIT_LIST_HEAD(&dwc->active_list); | |
1599 | INIT_LIST_HEAD(&dwc->queue); | |
1600 | INIT_LIST_HEAD(&dwc->free_list); | |
1601 | ||
1602 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1603 | |
0fdb567f | 1604 | dwc->direction = DMA_TRANS_NONE; |
f776076b | 1605 | dwc->request_line = ~0; |
a0982004 | 1606 | |
75c61225 | 1607 | /* Hardware configuration */ |
fed2574b AS |
1608 | if (autocfg) { |
1609 | unsigned int dwc_params; | |
9cade1a4 | 1610 | void __iomem *addr = chip->regs + r * sizeof(u32); |
fed2574b | 1611 | |
9cade1a4 | 1612 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
fed2574b | 1613 | |
9cade1a4 AS |
1614 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1615 | dwc_params); | |
985a6c7d | 1616 | |
1d566f11 AS |
1617 | /* |
1618 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1619 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1620 | * up to 0x0a for 4095. |
1621 | */ | |
4a63a8b3 AS |
1622 | dwc->block_size = |
1623 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1624 | dwc->nollp = |
1625 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1626 | } else { | |
4a63a8b3 | 1627 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1628 | |
1629 | /* Check if channel supports multi block transfer */ | |
1630 | channel_writel(dwc, LLP, 0xfffffffc); | |
1631 | dwc->nollp = | |
1632 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1633 | channel_writel(dwc, LLP, 0); | |
1634 | } | |
3bfb1d20 HS |
1635 | } |
1636 | ||
11f932ec | 1637 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1638 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1639 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1640 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1641 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1642 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1643 | ||
3bfb1d20 HS |
1644 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1645 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1646 | if (pdata->is_private) |
1647 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
9cade1a4 | 1648 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1649 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1650 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1651 | ||
1652 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1653 | ||
1654 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1655 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1656 | |
07934481 | 1657 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1658 | dw->dma.device_issue_pending = dwc_issue_pending; |
1659 | ||
1660 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1661 | ||
9cade1a4 | 1662 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
21d43f49 | 1663 | nr_channels); |
3bfb1d20 HS |
1664 | |
1665 | dma_async_device_register(&dw->dma); | |
1666 | ||
1667 | return 0; | |
8be4f523 AS |
1668 | |
1669 | err_pdata: | |
1670 | clk_disable_unprepare(dw->clk); | |
1671 | return err; | |
3bfb1d20 | 1672 | } |
9cade1a4 | 1673 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1674 | |
9cade1a4 | 1675 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1676 | { |
9cade1a4 | 1677 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1678 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 HS |
1679 | |
1680 | dw_dma_off(dw); | |
1681 | dma_async_device_unregister(&dw->dma); | |
1682 | ||
97977f75 | 1683 | free_irq(chip->irq, dw); |
3bfb1d20 HS |
1684 | tasklet_kill(&dw->tasklet); |
1685 | ||
1686 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1687 | chan.device_node) { | |
1688 | list_del(&dwc->chan.device_node); | |
1689 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1690 | } | |
1691 | ||
8be4f523 AS |
1692 | clk_disable_unprepare(dw->clk); |
1693 | ||
3bfb1d20 HS |
1694 | return 0; |
1695 | } | |
9cade1a4 | 1696 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1697 | |
9cade1a4 | 1698 | void dw_dma_shutdown(struct dw_dma_chip *chip) |
3bfb1d20 | 1699 | { |
9cade1a4 | 1700 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1701 | |
6168d567 | 1702 | dw_dma_off(dw); |
3075528d | 1703 | clk_disable_unprepare(dw->clk); |
3bfb1d20 | 1704 | } |
9cade1a4 | 1705 | EXPORT_SYMBOL_GPL(dw_dma_shutdown); |
3bfb1d20 | 1706 | |
9cade1a4 AS |
1707 | #ifdef CONFIG_PM_SLEEP |
1708 | ||
1709 | int dw_dma_suspend(struct dw_dma_chip *chip) | |
3bfb1d20 | 1710 | { |
9cade1a4 | 1711 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1712 | |
6168d567 | 1713 | dw_dma_off(dw); |
3075528d | 1714 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1715 | |
3bfb1d20 HS |
1716 | return 0; |
1717 | } | |
9cade1a4 | 1718 | EXPORT_SYMBOL_GPL(dw_dma_suspend); |
3bfb1d20 | 1719 | |
9cade1a4 | 1720 | int dw_dma_resume(struct dw_dma_chip *chip) |
3bfb1d20 | 1721 | { |
9cade1a4 | 1722 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1723 | |
3075528d | 1724 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1725 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1726 | |
3bfb1d20 | 1727 | return 0; |
3bfb1d20 | 1728 | } |
9cade1a4 | 1729 | EXPORT_SYMBOL_GPL(dw_dma_resume); |
3bfb1d20 | 1730 | |
9cade1a4 | 1731 | #endif /* CONFIG_PM_SLEEP */ |
3bfb1d20 HS |
1732 | |
1733 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1734 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1735 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1736 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |