Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/clk.h> |
15 | #include <linux/delay.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
f8122a82 | 18 | #include <linux/dmapool.h> |
7331205a | 19 | #include <linux/err.h> |
3bfb1d20 HS |
20 | #include <linux/init.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/module.h> | |
3bfb1d20 HS |
25 | #include <linux/slab.h> |
26 | ||
61a76496 | 27 | #include "../dmaengine.h" |
9cade1a4 | 28 | #include "internal.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
36 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
37 | * which does not support descriptor writeback. | |
38 | */ | |
39 | ||
78f3c9d2 AS |
40 | static inline bool is_request_line_unset(struct dw_dma_chan *dwc) |
41 | { | |
42 | return dwc->request_line == (typeof(dwc->request_line))~0; | |
43 | } | |
44 | ||
f776076b | 45 | static inline void dwc_set_masters(struct dw_dma_chan *dwc) |
5be10f34 | 46 | { |
f776076b AB |
47 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
48 | struct dw_dma_slave *dws = dwc->chan.private; | |
49 | unsigned char mmax = dw->nr_masters - 1; | |
5be10f34 | 50 | |
78f3c9d2 AS |
51 | if (!is_request_line_unset(dwc)) |
52 | return; | |
53 | ||
54 | dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws)); | |
55 | dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws)); | |
5be10f34 AS |
56 | } |
57 | ||
327e6970 | 58 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
59 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
60 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 61 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 62 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 63 | DW_DMA_MSIZE_16; \ |
495aea4b | 64 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 65 | DW_DMA_MSIZE_16; \ |
f301c062 | 66 | \ |
327e6970 VK |
67 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
68 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
69 | | DWC_CTLL_LLP_D_EN \ |
70 | | DWC_CTLL_LLP_S_EN \ | |
f776076b AB |
71 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
72 | | DWC_CTLL_SMS(_dwc->src_master)); \ | |
f301c062 | 73 | }) |
3bfb1d20 | 74 | |
3bfb1d20 HS |
75 | /* |
76 | * Number of descriptors to allocate for each channel. This should be | |
77 | * made configurable somehow; preferably, the clients (at least the | |
78 | * ones using slave transfers) should be able to give us a hint. | |
79 | */ | |
80 | #define NR_DESCS_PER_CHANNEL 64 | |
81 | ||
82 | /*----------------------------------------------------------------------*/ | |
3bfb1d20 | 83 | |
41d5e59c DW |
84 | static struct device *chan2dev(struct dma_chan *chan) |
85 | { | |
86 | return &chan->dev->device; | |
87 | } | |
88 | static struct device *chan2parent(struct dma_chan *chan) | |
89 | { | |
90 | return chan->dev->device.parent; | |
91 | } | |
92 | ||
3bfb1d20 HS |
93 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
94 | { | |
e63a47a3 | 95 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
96 | } |
97 | ||
3bfb1d20 HS |
98 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
99 | { | |
100 | struct dw_desc *desc, *_desc; | |
101 | struct dw_desc *ret = NULL; | |
102 | unsigned int i = 0; | |
69cea5a0 | 103 | unsigned long flags; |
3bfb1d20 | 104 | |
69cea5a0 | 105 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 106 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 107 | i++; |
3bfb1d20 HS |
108 | if (async_tx_test_ack(&desc->txd)) { |
109 | list_del(&desc->desc_node); | |
110 | ret = desc; | |
111 | break; | |
112 | } | |
41d5e59c | 113 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 114 | } |
69cea5a0 | 115 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 116 | |
41d5e59c | 117 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
118 | |
119 | return ret; | |
120 | } | |
121 | ||
3bfb1d20 HS |
122 | /* |
123 | * Move a descriptor, including any children, to the free list. | |
124 | * `desc' must not be on any lists. | |
125 | */ | |
126 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
127 | { | |
69cea5a0 VK |
128 | unsigned long flags; |
129 | ||
3bfb1d20 HS |
130 | if (desc) { |
131 | struct dw_desc *child; | |
132 | ||
69cea5a0 | 133 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 134 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 135 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
136 | "moving child desc %p to freelist\n", |
137 | child); | |
e0bd0f8c | 138 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 139 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 140 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 141 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
142 | } |
143 | } | |
144 | ||
61e183f8 VK |
145 | static void dwc_initialize(struct dw_dma_chan *dwc) |
146 | { | |
147 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
148 | struct dw_dma_slave *dws = dwc->chan.private; | |
149 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
150 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
151 | ||
152 | if (dwc->initialized == true) | |
153 | return; | |
154 | ||
f776076b | 155 | if (dws) { |
61e183f8 VK |
156 | /* |
157 | * We need controller-specific data to set up slave | |
158 | * transfers. | |
159 | */ | |
160 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
161 | ||
162 | cfghi = dws->cfg_hi; | |
163 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf | 164 | } else { |
0fdb567f | 165 | if (dwc->direction == DMA_MEM_TO_DEV) |
f776076b | 166 | cfghi = DWC_CFGH_DST_PER(dwc->request_line); |
0fdb567f | 167 | else if (dwc->direction == DMA_DEV_TO_MEM) |
f776076b | 168 | cfghi = DWC_CFGH_SRC_PER(dwc->request_line); |
61e183f8 VK |
169 | } |
170 | ||
171 | channel_writel(dwc, CFG_LO, cfglo); | |
172 | channel_writel(dwc, CFG_HI, cfghi); | |
173 | ||
174 | /* Enable interrupts */ | |
175 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
176 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
177 | ||
178 | dwc->initialized = true; | |
179 | } | |
180 | ||
3bfb1d20 HS |
181 | /*----------------------------------------------------------------------*/ |
182 | ||
4c2d56c5 AS |
183 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
184 | { | |
185 | /* | |
186 | * We can be a lot more clever here, but this should take care | |
187 | * of the most common optimization. | |
188 | */ | |
189 | if (!(v & 7)) | |
190 | return 3; | |
191 | else if (!(v & 3)) | |
192 | return 2; | |
193 | else if (!(v & 1)) | |
194 | return 1; | |
195 | return 0; | |
196 | } | |
197 | ||
f52b36d2 | 198 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
199 | { |
200 | dev_err(chan2dev(&dwc->chan), | |
201 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
202 | channel_readl(dwc, SAR), | |
203 | channel_readl(dwc, DAR), | |
204 | channel_readl(dwc, LLP), | |
205 | channel_readl(dwc, CTL_HI), | |
206 | channel_readl(dwc, CTL_LO)); | |
207 | } | |
208 | ||
3f936207 AS |
209 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
210 | { | |
211 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
212 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
213 | cpu_relax(); | |
214 | } | |
215 | ||
1d455437 AS |
216 | /*----------------------------------------------------------------------*/ |
217 | ||
fed2574b AS |
218 | /* Perform single block transfer */ |
219 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
220 | struct dw_desc *desc) | |
221 | { | |
222 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
223 | u32 ctllo; | |
224 | ||
225 | /* Software emulation of LLP mode relies on interrupts to continue | |
226 | * multi block transfer. */ | |
227 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; | |
228 | ||
229 | channel_writel(dwc, SAR, desc->lli.sar); | |
230 | channel_writel(dwc, DAR, desc->lli.dar); | |
231 | channel_writel(dwc, CTL_LO, ctllo); | |
232 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
233 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
234 | |
235 | /* Move pointer to next descriptor */ | |
236 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
237 | } |
238 | ||
3bfb1d20 HS |
239 | /* Called with dwc->lock held and bh disabled */ |
240 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
241 | { | |
242 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 243 | unsigned long was_soft_llp; |
3bfb1d20 HS |
244 | |
245 | /* ASSERT: channel is idle */ | |
246 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 247 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 248 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 249 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
250 | |
251 | /* The tasklet will hopefully advance the queue... */ | |
252 | return; | |
253 | } | |
254 | ||
fed2574b AS |
255 | if (dwc->nollp) { |
256 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
257 | &dwc->flags); | |
258 | if (was_soft_llp) { | |
259 | dev_err(chan2dev(&dwc->chan), | |
260 | "BUG: Attempted to start new LLP transfer " | |
261 | "inside ongoing one\n"); | |
262 | return; | |
263 | } | |
264 | ||
265 | dwc_initialize(dwc); | |
266 | ||
4702d524 | 267 | dwc->residue = first->total_len; |
f5c6a7df | 268 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 269 | |
fdf475fa | 270 | /* Submit first block */ |
fed2574b AS |
271 | dwc_do_single_block(dwc, first); |
272 | ||
273 | return; | |
274 | } | |
275 | ||
61e183f8 VK |
276 | dwc_initialize(dwc); |
277 | ||
3bfb1d20 HS |
278 | channel_writel(dwc, LLP, first->txd.phys); |
279 | channel_writel(dwc, CTL_LO, | |
280 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
281 | channel_writel(dwc, CTL_HI, 0); | |
282 | channel_set_bit(dw, CH_EN, dwc->mask); | |
283 | } | |
284 | ||
285 | /*----------------------------------------------------------------------*/ | |
286 | ||
287 | static void | |
5fedefb8 VK |
288 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
289 | bool callback_required) | |
3bfb1d20 | 290 | { |
5fedefb8 VK |
291 | dma_async_tx_callback callback = NULL; |
292 | void *param = NULL; | |
3bfb1d20 | 293 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 294 | struct dw_desc *child; |
69cea5a0 | 295 | unsigned long flags; |
3bfb1d20 | 296 | |
41d5e59c | 297 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 298 | |
69cea5a0 | 299 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 300 | dma_cookie_complete(txd); |
5fedefb8 VK |
301 | if (callback_required) { |
302 | callback = txd->callback; | |
303 | param = txd->callback_param; | |
304 | } | |
3bfb1d20 | 305 | |
e518076e VK |
306 | /* async_tx_ack */ |
307 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
308 | async_tx_ack(&child->txd); | |
309 | async_tx_ack(&desc->txd); | |
310 | ||
e0bd0f8c | 311 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
312 | list_move(&desc->desc_node, &dwc->free_list); |
313 | ||
495aea4b | 314 | if (!is_slave_direction(dwc->direction)) { |
657a77fa AN |
315 | struct device *parent = chan2parent(&dwc->chan); |
316 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
317 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
318 | dma_unmap_single(parent, desc->lli.dar, | |
30d38a32 | 319 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
320 | else |
321 | dma_unmap_page(parent, desc->lli.dar, | |
30d38a32 | 322 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
323 | } |
324 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
325 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
326 | dma_unmap_single(parent, desc->lli.sar, | |
30d38a32 | 327 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
328 | else |
329 | dma_unmap_page(parent, desc->lli.sar, | |
30d38a32 | 330 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
331 | } |
332 | } | |
3bfb1d20 | 333 | |
69cea5a0 VK |
334 | spin_unlock_irqrestore(&dwc->lock, flags); |
335 | ||
21e93c1e | 336 | if (callback) |
3bfb1d20 HS |
337 | callback(param); |
338 | } | |
339 | ||
340 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
341 | { | |
342 | struct dw_desc *desc, *_desc; | |
343 | LIST_HEAD(list); | |
69cea5a0 | 344 | unsigned long flags; |
3bfb1d20 | 345 | |
69cea5a0 | 346 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 347 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 348 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
349 | "BUG: XFER bit set, but channel not idle!\n"); |
350 | ||
351 | /* Try to continue after resetting the channel... */ | |
3f936207 | 352 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
353 | } |
354 | ||
355 | /* | |
356 | * Submit queued descriptors ASAP, i.e. before we go through | |
357 | * the completed ones. | |
358 | */ | |
3bfb1d20 | 359 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
360 | if (!list_empty(&dwc->queue)) { |
361 | list_move(dwc->queue.next, &dwc->active_list); | |
362 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
363 | } | |
3bfb1d20 | 364 | |
69cea5a0 VK |
365 | spin_unlock_irqrestore(&dwc->lock, flags); |
366 | ||
3bfb1d20 | 367 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 368 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
369 | } |
370 | ||
4702d524 AS |
371 | /* Returns how many bytes were already received from source */ |
372 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
373 | { | |
374 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
375 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
376 | ||
377 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
378 | } | |
379 | ||
3bfb1d20 HS |
380 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
381 | { | |
382 | dma_addr_t llp; | |
383 | struct dw_desc *desc, *_desc; | |
384 | struct dw_desc *child; | |
385 | u32 status_xfer; | |
69cea5a0 | 386 | unsigned long flags; |
3bfb1d20 | 387 | |
69cea5a0 | 388 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
389 | llp = channel_readl(dwc, LLP); |
390 | status_xfer = dma_readl(dw, RAW.XFER); | |
391 | ||
392 | if (status_xfer & dwc->mask) { | |
393 | /* Everything we've submitted is done */ | |
394 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
395 | |
396 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
397 | struct list_head *head, *active = dwc->tx_node_active; |
398 | ||
399 | /* | |
400 | * We are inside first active descriptor. | |
401 | * Otherwise something is really wrong. | |
402 | */ | |
403 | desc = dwc_first_active(dwc); | |
404 | ||
405 | head = &desc->tx_list; | |
406 | if (active != head) { | |
4702d524 AS |
407 | /* Update desc to reflect last sent one */ |
408 | if (active != head->next) | |
409 | desc = to_dw_desc(active->prev); | |
410 | ||
411 | dwc->residue -= desc->len; | |
412 | ||
fdf475fa | 413 | child = to_dw_desc(active); |
77bcc497 AS |
414 | |
415 | /* Submit next block */ | |
fdf475fa | 416 | dwc_do_single_block(dwc, child); |
77bcc497 | 417 | |
fdf475fa | 418 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
419 | return; |
420 | } | |
fdf475fa | 421 | |
77bcc497 AS |
422 | /* We are done here */ |
423 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
424 | } | |
4702d524 AS |
425 | |
426 | dwc->residue = 0; | |
427 | ||
69cea5a0 VK |
428 | spin_unlock_irqrestore(&dwc->lock, flags); |
429 | ||
3bfb1d20 HS |
430 | dwc_complete_all(dw, dwc); |
431 | return; | |
432 | } | |
433 | ||
69cea5a0 | 434 | if (list_empty(&dwc->active_list)) { |
4702d524 | 435 | dwc->residue = 0; |
69cea5a0 | 436 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 437 | return; |
69cea5a0 | 438 | } |
087809fc | 439 | |
77bcc497 AS |
440 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
441 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 442 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 443 | return; |
69cea5a0 | 444 | } |
087809fc | 445 | |
2e4c364e | 446 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__, |
2f45d613 | 447 | (unsigned long long)llp); |
3bfb1d20 HS |
448 | |
449 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 450 | /* Initial residue value */ |
4702d524 AS |
451 | dwc->residue = desc->total_len; |
452 | ||
75c61225 | 453 | /* Check first descriptors addr */ |
69cea5a0 VK |
454 | if (desc->txd.phys == llp) { |
455 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 456 | return; |
69cea5a0 | 457 | } |
84adccfb | 458 | |
75c61225 | 459 | /* Check first descriptors llp */ |
69cea5a0 | 460 | if (desc->lli.llp == llp) { |
3bfb1d20 | 461 | /* This one is currently in progress */ |
4702d524 | 462 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 463 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 464 | return; |
69cea5a0 | 465 | } |
3bfb1d20 | 466 | |
4702d524 AS |
467 | dwc->residue -= desc->len; |
468 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 469 | if (child->lli.llp == llp) { |
3bfb1d20 | 470 | /* Currently in progress */ |
4702d524 | 471 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 472 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 473 | return; |
69cea5a0 | 474 | } |
4702d524 AS |
475 | dwc->residue -= child->len; |
476 | } | |
3bfb1d20 HS |
477 | |
478 | /* | |
479 | * No descriptors so far seem to be in progress, i.e. | |
480 | * this one must be done. | |
481 | */ | |
69cea5a0 | 482 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 483 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 484 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
485 | } |
486 | ||
41d5e59c | 487 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
488 | "BUG: All descriptors done, but channel not idle!\n"); |
489 | ||
490 | /* Try to continue after resetting the channel... */ | |
3f936207 | 491 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
492 | |
493 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
494 | list_move(dwc->queue.next, &dwc->active_list); |
495 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 496 | } |
69cea5a0 | 497 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
498 | } |
499 | ||
93aad1bc | 500 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 501 | { |
21d43f49 AS |
502 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
503 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
504 | } |
505 | ||
506 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
507 | { | |
508 | struct dw_desc *bad_desc; | |
509 | struct dw_desc *child; | |
69cea5a0 | 510 | unsigned long flags; |
3bfb1d20 HS |
511 | |
512 | dwc_scan_descriptors(dw, dwc); | |
513 | ||
69cea5a0 VK |
514 | spin_lock_irqsave(&dwc->lock, flags); |
515 | ||
3bfb1d20 HS |
516 | /* |
517 | * The descriptor currently at the head of the active list is | |
518 | * borked. Since we don't have any way to report errors, we'll | |
519 | * just have to scream loudly and try to carry on. | |
520 | */ | |
521 | bad_desc = dwc_first_active(dwc); | |
522 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 523 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
524 | |
525 | /* Clear the error flag and try to restart the controller */ | |
526 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
527 | if (!list_empty(&dwc->active_list)) | |
528 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
529 | ||
530 | /* | |
ba84bd71 | 531 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
532 | * when someone submits a bad physical address in a |
533 | * descriptor, we should consider ourselves lucky that the | |
534 | * controller flagged an error instead of scribbling over | |
535 | * random memory locations. | |
536 | */ | |
ba84bd71 AS |
537 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
538 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 539 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 540 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
541 | dwc_dump_lli(dwc, &child->lli); |
542 | ||
69cea5a0 VK |
543 | spin_unlock_irqrestore(&dwc->lock, flags); |
544 | ||
3bfb1d20 | 545 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 546 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
547 | } |
548 | ||
d9de4519 HCE |
549 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
550 | ||
8004cbb4 | 551 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
552 | { |
553 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
554 | return channel_readl(dwc, SAR); | |
555 | } | |
556 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
557 | ||
8004cbb4 | 558 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
559 | { |
560 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
561 | return channel_readl(dwc, DAR); | |
562 | } | |
563 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
564 | ||
75c61225 | 565 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 566 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
ff7b05f2 | 567 | u32 status_err, u32 status_xfer) |
d9de4519 | 568 | { |
69cea5a0 VK |
569 | unsigned long flags; |
570 | ||
ff7b05f2 | 571 | if (dwc->mask) { |
d9de4519 HCE |
572 | void (*callback)(void *param); |
573 | void *callback_param; | |
574 | ||
575 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
576 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
577 | |
578 | callback = dwc->cdesc->period_callback; | |
579 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
580 | |
581 | if (callback) | |
d9de4519 | 582 | callback(callback_param); |
d9de4519 HCE |
583 | } |
584 | ||
585 | /* | |
586 | * Error and transfer complete are highly unlikely, and will most | |
587 | * likely be due to a configuration error by the user. | |
588 | */ | |
589 | if (unlikely(status_err & dwc->mask) || | |
590 | unlikely(status_xfer & dwc->mask)) { | |
591 | int i; | |
592 | ||
593 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
594 | "interrupt, stopping DMA transfer\n", | |
595 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
596 | |
597 | spin_lock_irqsave(&dwc->lock, flags); | |
598 | ||
1d455437 | 599 | dwc_dump_chan_regs(dwc); |
d9de4519 | 600 | |
3f936207 | 601 | dwc_chan_disable(dw, dwc); |
d9de4519 | 602 | |
75c61225 | 603 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
604 | channel_writel(dwc, LLP, 0); |
605 | channel_writel(dwc, CTL_LO, 0); | |
606 | channel_writel(dwc, CTL_HI, 0); | |
607 | ||
d9de4519 HCE |
608 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
609 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
610 | ||
611 | for (i = 0; i < dwc->cdesc->periods; i++) | |
612 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
613 | |
614 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
615 | } |
616 | } | |
617 | ||
618 | /* ------------------------------------------------------------------------- */ | |
619 | ||
3bfb1d20 HS |
620 | static void dw_dma_tasklet(unsigned long data) |
621 | { | |
622 | struct dw_dma *dw = (struct dw_dma *)data; | |
623 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
624 | u32 status_xfer; |
625 | u32 status_err; | |
626 | int i; | |
627 | ||
7fe7b2f4 | 628 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
629 | status_err = dma_readl(dw, RAW.ERROR); |
630 | ||
2e4c364e | 631 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
632 | |
633 | for (i = 0; i < dw->dma.chancnt; i++) { | |
634 | dwc = &dw->chan[i]; | |
d9de4519 | 635 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 636 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 637 | else if (status_err & (1 << i)) |
3bfb1d20 | 638 | dwc_handle_error(dw, dwc); |
77bcc497 | 639 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 640 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
641 | } |
642 | ||
643 | /* | |
ff7b05f2 | 644 | * Re-enable interrupts. |
3bfb1d20 HS |
645 | */ |
646 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
647 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
648 | } | |
649 | ||
650 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
651 | { | |
652 | struct dw_dma *dw = dev_id; | |
653 | u32 status; | |
654 | ||
2e4c364e | 655 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, |
3bfb1d20 HS |
656 | dma_readl(dw, STATUS_INT)); |
657 | ||
658 | /* | |
659 | * Just disable the interrupts. We'll turn them back on in the | |
660 | * softirq handler. | |
661 | */ | |
662 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
663 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
664 | ||
665 | status = dma_readl(dw, STATUS_INT); | |
666 | if (status) { | |
667 | dev_err(dw->dma.dev, | |
668 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
669 | status); | |
670 | ||
671 | /* Try to recover */ | |
672 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
673 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
674 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
675 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
676 | } | |
677 | ||
678 | tasklet_schedule(&dw->tasklet); | |
679 | ||
680 | return IRQ_HANDLED; | |
681 | } | |
682 | ||
683 | /*----------------------------------------------------------------------*/ | |
684 | ||
685 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
686 | { | |
687 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
688 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
689 | dma_cookie_t cookie; | |
69cea5a0 | 690 | unsigned long flags; |
3bfb1d20 | 691 | |
69cea5a0 | 692 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 693 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
694 | |
695 | /* | |
696 | * REVISIT: We should attempt to chain as many descriptors as | |
697 | * possible, perhaps even appending to those already submitted | |
698 | * for DMA. But this is hard to do in a race-free manner. | |
699 | */ | |
700 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 701 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 702 | desc->txd.cookie); |
3bfb1d20 | 703 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 704 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 705 | } else { |
2e4c364e | 706 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
707 | desc->txd.cookie); |
708 | ||
709 | list_add_tail(&desc->desc_node, &dwc->queue); | |
710 | } | |
711 | ||
69cea5a0 | 712 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
713 | |
714 | return cookie; | |
715 | } | |
716 | ||
717 | static struct dma_async_tx_descriptor * | |
718 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
719 | size_t len, unsigned long flags) | |
720 | { | |
721 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 722 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
723 | struct dw_desc *desc; |
724 | struct dw_desc *first; | |
725 | struct dw_desc *prev; | |
726 | size_t xfer_count; | |
727 | size_t offset; | |
728 | unsigned int src_width; | |
729 | unsigned int dst_width; | |
3d4f8605 | 730 | unsigned int data_width; |
3bfb1d20 HS |
731 | u32 ctllo; |
732 | ||
2f45d613 | 733 | dev_vdbg(chan2dev(chan), |
2e4c364e | 734 | "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, |
2f45d613 AS |
735 | (unsigned long long)dest, (unsigned long long)src, |
736 | len, flags); | |
3bfb1d20 HS |
737 | |
738 | if (unlikely(!len)) { | |
2e4c364e | 739 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
740 | return NULL; |
741 | } | |
742 | ||
0fdb567f AS |
743 | dwc->direction = DMA_MEM_TO_MEM; |
744 | ||
f776076b AB |
745 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
746 | dw->data_width[dwc->dst_master]); | |
a0982004 | 747 | |
3d4f8605 AS |
748 | src_width = dst_width = min_t(unsigned int, data_width, |
749 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 750 | |
327e6970 | 751 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
752 | | DWC_CTLL_DST_WIDTH(dst_width) |
753 | | DWC_CTLL_SRC_WIDTH(src_width) | |
754 | | DWC_CTLL_DST_INC | |
755 | | DWC_CTLL_SRC_INC | |
756 | | DWC_CTLL_FC_M2M; | |
757 | prev = first = NULL; | |
758 | ||
759 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
760 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 761 | dwc->block_size); |
3bfb1d20 HS |
762 | |
763 | desc = dwc_desc_get(dwc); | |
764 | if (!desc) | |
765 | goto err_desc_get; | |
766 | ||
767 | desc->lli.sar = src + offset; | |
768 | desc->lli.dar = dest + offset; | |
769 | desc->lli.ctllo = ctllo; | |
770 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 771 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
772 | |
773 | if (!first) { | |
774 | first = desc; | |
775 | } else { | |
776 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 777 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 778 | &first->tx_list); |
3bfb1d20 HS |
779 | } |
780 | prev = desc; | |
781 | } | |
782 | ||
3bfb1d20 HS |
783 | if (flags & DMA_PREP_INTERRUPT) |
784 | /* Trigger interrupt after last block */ | |
785 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
786 | ||
787 | prev->lli.llp = 0; | |
3bfb1d20 | 788 | first->txd.flags = flags; |
30d38a32 | 789 | first->total_len = len; |
3bfb1d20 HS |
790 | |
791 | return &first->txd; | |
792 | ||
793 | err_desc_get: | |
794 | dwc_desc_put(dwc, first); | |
795 | return NULL; | |
796 | } | |
797 | ||
798 | static struct dma_async_tx_descriptor * | |
799 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 800 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 801 | unsigned long flags, void *context) |
3bfb1d20 HS |
802 | { |
803 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 804 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 805 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
806 | struct dw_desc *prev; |
807 | struct dw_desc *first; | |
808 | u32 ctllo; | |
809 | dma_addr_t reg; | |
810 | unsigned int reg_width; | |
811 | unsigned int mem_width; | |
a0982004 | 812 | unsigned int data_width; |
3bfb1d20 HS |
813 | unsigned int i; |
814 | struct scatterlist *sg; | |
815 | size_t total_len = 0; | |
816 | ||
2e4c364e | 817 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 818 | |
495aea4b | 819 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
820 | return NULL; |
821 | ||
0fdb567f AS |
822 | dwc->direction = direction; |
823 | ||
3bfb1d20 HS |
824 | prev = first = NULL; |
825 | ||
3bfb1d20 | 826 | switch (direction) { |
db8196df | 827 | case DMA_MEM_TO_DEV: |
327e6970 VK |
828 | reg_width = __fls(sconfig->dst_addr_width); |
829 | reg = sconfig->dst_addr; | |
830 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
831 | | DWC_CTLL_DST_WIDTH(reg_width) |
832 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
833 | | DWC_CTLL_SRC_INC); |
834 | ||
835 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
836 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
837 | ||
f776076b | 838 | data_width = dw->data_width[dwc->src_master]; |
a0982004 | 839 | |
3bfb1d20 HS |
840 | for_each_sg(sgl, sg, sg_len, i) { |
841 | struct dw_desc *desc; | |
69dc14b5 | 842 | u32 len, dlen, mem; |
3bfb1d20 | 843 | |
cbb796cc | 844 | mem = sg_dma_address(sg); |
69dc14b5 | 845 | len = sg_dma_len(sg); |
6bc711f6 | 846 | |
a0982004 AS |
847 | mem_width = min_t(unsigned int, |
848 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 849 | |
69dc14b5 | 850 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
851 | desc = dwc_desc_get(dwc); |
852 | if (!desc) { | |
41d5e59c | 853 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
854 | "not enough descriptors available\n"); |
855 | goto err_desc_get; | |
856 | } | |
857 | ||
3bfb1d20 HS |
858 | desc->lli.sar = mem; |
859 | desc->lli.dar = reg; | |
860 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
861 | if ((len >> mem_width) > dwc->block_size) { |
862 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
863 | mem += dlen; |
864 | len -= dlen; | |
865 | } else { | |
866 | dlen = len; | |
867 | len = 0; | |
868 | } | |
869 | ||
870 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 871 | desc->len = dlen; |
3bfb1d20 HS |
872 | |
873 | if (!first) { | |
874 | first = desc; | |
875 | } else { | |
876 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 877 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 878 | &first->tx_list); |
3bfb1d20 HS |
879 | } |
880 | prev = desc; | |
69dc14b5 VK |
881 | total_len += dlen; |
882 | ||
883 | if (len) | |
884 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
885 | } |
886 | break; | |
db8196df | 887 | case DMA_DEV_TO_MEM: |
327e6970 VK |
888 | reg_width = __fls(sconfig->src_addr_width); |
889 | reg = sconfig->src_addr; | |
890 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
891 | | DWC_CTLL_SRC_WIDTH(reg_width) |
892 | | DWC_CTLL_DST_INC | |
327e6970 VK |
893 | | DWC_CTLL_SRC_FIX); |
894 | ||
895 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
896 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 897 | |
f776076b | 898 | data_width = dw->data_width[dwc->dst_master]; |
a0982004 | 899 | |
3bfb1d20 HS |
900 | for_each_sg(sgl, sg, sg_len, i) { |
901 | struct dw_desc *desc; | |
69dc14b5 | 902 | u32 len, dlen, mem; |
3bfb1d20 | 903 | |
cbb796cc | 904 | mem = sg_dma_address(sg); |
3bfb1d20 | 905 | len = sg_dma_len(sg); |
6bc711f6 | 906 | |
a0982004 AS |
907 | mem_width = min_t(unsigned int, |
908 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 909 | |
69dc14b5 VK |
910 | slave_sg_fromdev_fill_desc: |
911 | desc = dwc_desc_get(dwc); | |
912 | if (!desc) { | |
913 | dev_err(chan2dev(chan), | |
914 | "not enough descriptors available\n"); | |
915 | goto err_desc_get; | |
916 | } | |
917 | ||
3bfb1d20 HS |
918 | desc->lli.sar = reg; |
919 | desc->lli.dar = mem; | |
920 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
921 | if ((len >> reg_width) > dwc->block_size) { |
922 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
923 | mem += dlen; |
924 | len -= dlen; | |
925 | } else { | |
926 | dlen = len; | |
927 | len = 0; | |
928 | } | |
929 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 930 | desc->len = dlen; |
3bfb1d20 HS |
931 | |
932 | if (!first) { | |
933 | first = desc; | |
934 | } else { | |
935 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 936 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 937 | &first->tx_list); |
3bfb1d20 HS |
938 | } |
939 | prev = desc; | |
69dc14b5 VK |
940 | total_len += dlen; |
941 | ||
942 | if (len) | |
943 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
944 | } |
945 | break; | |
946 | default: | |
947 | return NULL; | |
948 | } | |
949 | ||
950 | if (flags & DMA_PREP_INTERRUPT) | |
951 | /* Trigger interrupt after last block */ | |
952 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
953 | ||
954 | prev->lli.llp = 0; | |
30d38a32 | 955 | first->total_len = total_len; |
3bfb1d20 HS |
956 | |
957 | return &first->txd; | |
958 | ||
959 | err_desc_get: | |
960 | dwc_desc_put(dwc, first); | |
961 | return NULL; | |
962 | } | |
963 | ||
327e6970 VK |
964 | /* |
965 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
966 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
967 | * | |
968 | * NOTE: burst size 2 is not supported by controller. | |
969 | * | |
970 | * This can be done by finding least significant bit set: n & (n - 1) | |
971 | */ | |
972 | static inline void convert_burst(u32 *maxburst) | |
973 | { | |
974 | if (*maxburst > 1) | |
975 | *maxburst = fls(*maxburst) - 2; | |
976 | else | |
977 | *maxburst = 0; | |
978 | } | |
979 | ||
980 | static int | |
981 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
982 | { | |
983 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
984 | ||
495aea4b AS |
985 | /* Check if chan will be configured for slave transfers */ |
986 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
987 | return -EINVAL; |
988 | ||
989 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 990 | dwc->direction = sconfig->direction; |
327e6970 | 991 | |
f776076b | 992 | /* Take the request line from slave_id member */ |
78f3c9d2 | 993 | if (is_request_line_unset(dwc)) |
f776076b AB |
994 | dwc->request_line = sconfig->slave_id; |
995 | ||
327e6970 VK |
996 | convert_burst(&dwc->dma_sconfig.src_maxburst); |
997 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
21fe3c52 AS |
1002 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
1003 | { | |
1004 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
123b69ab | 1005 | unsigned int count = 20; /* timeout iterations */ |
21fe3c52 AS |
1006 | |
1007 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
123b69ab AS |
1008 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
1009 | udelay(2); | |
21fe3c52 AS |
1010 | |
1011 | dwc->paused = true; | |
1012 | } | |
1013 | ||
1014 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
1015 | { | |
1016 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
1017 | ||
1018 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1019 | ||
1020 | dwc->paused = false; | |
1021 | } | |
1022 | ||
05827630 LW |
1023 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1024 | unsigned long arg) | |
3bfb1d20 HS |
1025 | { |
1026 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1027 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1028 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1029 | unsigned long flags; |
3bfb1d20 HS |
1030 | LIST_HEAD(list); |
1031 | ||
a7c57cf7 LW |
1032 | if (cmd == DMA_PAUSE) { |
1033 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1034 | |
21fe3c52 | 1035 | dwc_chan_pause(dwc); |
3bfb1d20 | 1036 | |
a7c57cf7 LW |
1037 | spin_unlock_irqrestore(&dwc->lock, flags); |
1038 | } else if (cmd == DMA_RESUME) { | |
1039 | if (!dwc->paused) | |
1040 | return 0; | |
3bfb1d20 | 1041 | |
a7c57cf7 | 1042 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1043 | |
21fe3c52 | 1044 | dwc_chan_resume(dwc); |
3bfb1d20 | 1045 | |
a7c57cf7 LW |
1046 | spin_unlock_irqrestore(&dwc->lock, flags); |
1047 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1048 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1049 | |
fed2574b AS |
1050 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1051 | ||
3f936207 | 1052 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1053 | |
a5dbff11 | 1054 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1055 | |
1056 | /* active_list entries will end up before queued entries */ | |
1057 | list_splice_init(&dwc->queue, &list); | |
1058 | list_splice_init(&dwc->active_list, &list); | |
1059 | ||
1060 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1061 | ||
1062 | /* Flush all pending and queued descriptors */ | |
1063 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1064 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1065 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1066 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1067 | } else { | |
a7c57cf7 | 1068 | return -ENXIO; |
327e6970 | 1069 | } |
c3635c78 LW |
1070 | |
1071 | return 0; | |
3bfb1d20 HS |
1072 | } |
1073 | ||
4702d524 AS |
1074 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1075 | { | |
1076 | unsigned long flags; | |
1077 | u32 residue; | |
1078 | ||
1079 | spin_lock_irqsave(&dwc->lock, flags); | |
1080 | ||
1081 | residue = dwc->residue; | |
1082 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1083 | residue -= dwc_get_sent(dwc); | |
1084 | ||
1085 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1086 | return residue; | |
1087 | } | |
1088 | ||
3bfb1d20 | 1089 | static enum dma_status |
07934481 LW |
1090 | dwc_tx_status(struct dma_chan *chan, |
1091 | dma_cookie_t cookie, | |
1092 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1093 | { |
1094 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1095 | enum dma_status ret; |
3bfb1d20 | 1096 | |
96a2af41 | 1097 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1098 | if (ret != DMA_SUCCESS) { |
1099 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
1100 | ||
96a2af41 | 1101 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1102 | } |
1103 | ||
abf53902 | 1104 | if (ret != DMA_SUCCESS) |
4702d524 | 1105 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1106 | |
a7c57cf7 LW |
1107 | if (dwc->paused) |
1108 | return DMA_PAUSED; | |
3bfb1d20 HS |
1109 | |
1110 | return ret; | |
1111 | } | |
1112 | ||
1113 | static void dwc_issue_pending(struct dma_chan *chan) | |
1114 | { | |
1115 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1116 | ||
3bfb1d20 HS |
1117 | if (!list_empty(&dwc->queue)) |
1118 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1119 | } |
1120 | ||
aa1e6f1a | 1121 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1122 | { |
1123 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1124 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1125 | struct dw_desc *desc; | |
3bfb1d20 | 1126 | int i; |
69cea5a0 | 1127 | unsigned long flags; |
3bfb1d20 | 1128 | |
2e4c364e | 1129 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1130 | |
3bfb1d20 HS |
1131 | /* ASSERT: channel is idle */ |
1132 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1133 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1134 | return -EIO; |
1135 | } | |
1136 | ||
d3ee98cd | 1137 | dma_cookie_init(chan); |
3bfb1d20 | 1138 | |
3bfb1d20 HS |
1139 | /* |
1140 | * NOTE: some controllers may have additional features that we | |
1141 | * need to initialize here, like "scatter-gather" (which | |
1142 | * doesn't mean what you think it means), and status writeback. | |
1143 | */ | |
1144 | ||
f776076b AB |
1145 | dwc_set_masters(dwc); |
1146 | ||
69cea5a0 | 1147 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1148 | i = dwc->descs_allocated; |
1149 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1150 | dma_addr_t phys; |
1151 | ||
69cea5a0 | 1152 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1153 | |
f8122a82 | 1154 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1155 | if (!desc) |
1156 | goto err_desc_alloc; | |
3bfb1d20 | 1157 | |
f8122a82 | 1158 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1159 | |
e0bd0f8c | 1160 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1161 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1162 | desc->txd.tx_submit = dwc_tx_submit; | |
1163 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1164 | desc->txd.phys = phys; |
cbd65312 | 1165 | |
3bfb1d20 HS |
1166 | dwc_desc_put(dwc, desc); |
1167 | ||
69cea5a0 | 1168 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1169 | i = ++dwc->descs_allocated; |
1170 | } | |
1171 | ||
69cea5a0 | 1172 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1173 | |
2e4c364e | 1174 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1175 | |
cbd65312 AS |
1176 | return i; |
1177 | ||
1178 | err_desc_alloc: | |
cbd65312 AS |
1179 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1180 | ||
3bfb1d20 HS |
1181 | return i; |
1182 | } | |
1183 | ||
1184 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1185 | { | |
1186 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1187 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1188 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1189 | unsigned long flags; |
3bfb1d20 HS |
1190 | LIST_HEAD(list); |
1191 | ||
2e4c364e | 1192 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1193 | dwc->descs_allocated); |
1194 | ||
1195 | /* ASSERT: channel is idle */ | |
1196 | BUG_ON(!list_empty(&dwc->active_list)); | |
1197 | BUG_ON(!list_empty(&dwc->queue)); | |
1198 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1199 | ||
69cea5a0 | 1200 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1201 | list_splice_init(&dwc->free_list, &list); |
1202 | dwc->descs_allocated = 0; | |
61e183f8 | 1203 | dwc->initialized = false; |
f776076b | 1204 | dwc->request_line = ~0; |
3bfb1d20 HS |
1205 | |
1206 | /* Disable interrupts */ | |
1207 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1208 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1209 | ||
69cea5a0 | 1210 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1211 | |
1212 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1213 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1214 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1215 | } |
1216 | ||
2e4c364e | 1217 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1218 | } |
1219 | ||
d9de4519 HCE |
1220 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1221 | ||
1222 | /** | |
1223 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1224 | * @chan: the DMA channel to start | |
1225 | * | |
1226 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1227 | * -errno on failure. | |
1228 | */ | |
1229 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1230 | { | |
1231 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1232 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1233 | unsigned long flags; |
d9de4519 HCE |
1234 | |
1235 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1236 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1237 | return -ENODEV; | |
1238 | } | |
1239 | ||
69cea5a0 | 1240 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1241 | |
75c61225 | 1242 | /* Assert channel is idle */ |
d9de4519 HCE |
1243 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
1244 | dev_err(chan2dev(&dwc->chan), | |
1245 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1246 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1247 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1248 | return -EBUSY; |
1249 | } | |
1250 | ||
d9de4519 HCE |
1251 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1252 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1253 | ||
75c61225 | 1254 | /* Setup DMAC channel registers */ |
d9de4519 HCE |
1255 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); |
1256 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1257 | channel_writel(dwc, CTL_HI, 0); | |
1258 | ||
1259 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1260 | ||
69cea5a0 | 1261 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1262 | |
1263 | return 0; | |
1264 | } | |
1265 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1266 | ||
1267 | /** | |
1268 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1269 | * @chan: the DMA channel to stop | |
1270 | * | |
1271 | * Must be called with soft interrupts disabled. | |
1272 | */ | |
1273 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1274 | { | |
1275 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1276 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1277 | unsigned long flags; |
d9de4519 | 1278 | |
69cea5a0 | 1279 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1280 | |
3f936207 | 1281 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1282 | |
69cea5a0 | 1283 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1284 | } |
1285 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1286 | ||
1287 | /** | |
1288 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1289 | * @chan: the DMA channel to prepare | |
1290 | * @buf_addr: physical DMA address where the buffer starts | |
1291 | * @buf_len: total number of bytes for the entire buffer | |
1292 | * @period_len: number of bytes for each period | |
1293 | * @direction: transfer direction, to or from device | |
1294 | * | |
1295 | * Must be called before trying to start the transfer. Returns a valid struct | |
1296 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1297 | */ | |
1298 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1299 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1300 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1301 | { |
1302 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1303 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1304 | struct dw_cyclic_desc *cdesc; |
1305 | struct dw_cyclic_desc *retval = NULL; | |
1306 | struct dw_desc *desc; | |
1307 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1308 | unsigned long was_cyclic; |
1309 | unsigned int reg_width; | |
1310 | unsigned int periods; | |
1311 | unsigned int i; | |
69cea5a0 | 1312 | unsigned long flags; |
d9de4519 | 1313 | |
69cea5a0 | 1314 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1315 | if (dwc->nollp) { |
1316 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1317 | dev_dbg(chan2dev(&dwc->chan), | |
1318 | "channel doesn't support LLP transfers\n"); | |
1319 | return ERR_PTR(-EINVAL); | |
1320 | } | |
1321 | ||
d9de4519 | 1322 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1323 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1324 | dev_dbg(chan2dev(&dwc->chan), |
1325 | "queue and/or active list are not empty\n"); | |
1326 | return ERR_PTR(-EBUSY); | |
1327 | } | |
1328 | ||
1329 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1330 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1331 | if (was_cyclic) { |
1332 | dev_dbg(chan2dev(&dwc->chan), | |
1333 | "channel already prepared for cyclic DMA\n"); | |
1334 | return ERR_PTR(-EBUSY); | |
1335 | } | |
1336 | ||
1337 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1338 | |
f44b92f4 AS |
1339 | if (unlikely(!is_slave_direction(direction))) |
1340 | goto out_err; | |
1341 | ||
0fdb567f AS |
1342 | dwc->direction = direction; |
1343 | ||
327e6970 VK |
1344 | if (direction == DMA_MEM_TO_DEV) |
1345 | reg_width = __ffs(sconfig->dst_addr_width); | |
1346 | else | |
1347 | reg_width = __ffs(sconfig->src_addr_width); | |
1348 | ||
d9de4519 HCE |
1349 | periods = buf_len / period_len; |
1350 | ||
1351 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1352 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1353 | goto out_err; |
1354 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1355 | goto out_err; | |
1356 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1357 | goto out_err; | |
d9de4519 HCE |
1358 | |
1359 | retval = ERR_PTR(-ENOMEM); | |
1360 | ||
1361 | if (periods > NR_DESCS_PER_CHANNEL) | |
1362 | goto out_err; | |
1363 | ||
1364 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1365 | if (!cdesc) | |
1366 | goto out_err; | |
1367 | ||
1368 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1369 | if (!cdesc->desc) | |
1370 | goto out_err_alloc; | |
1371 | ||
1372 | for (i = 0; i < periods; i++) { | |
1373 | desc = dwc_desc_get(dwc); | |
1374 | if (!desc) | |
1375 | goto out_err_desc_get; | |
1376 | ||
1377 | switch (direction) { | |
db8196df | 1378 | case DMA_MEM_TO_DEV: |
327e6970 | 1379 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1380 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1381 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1382 | | DWC_CTLL_DST_WIDTH(reg_width) |
1383 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1384 | | DWC_CTLL_DST_FIX | |
1385 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1386 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1387 | |
1388 | desc->lli.ctllo |= sconfig->device_fc ? | |
1389 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1390 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1391 | ||
d9de4519 | 1392 | break; |
db8196df | 1393 | case DMA_DEV_TO_MEM: |
d9de4519 | 1394 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1395 | desc->lli.sar = sconfig->src_addr; |
1396 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1397 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1398 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1399 | | DWC_CTLL_DST_INC | |
1400 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1401 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1402 | |
1403 | desc->lli.ctllo |= sconfig->device_fc ? | |
1404 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1405 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1406 | ||
d9de4519 HCE |
1407 | break; |
1408 | default: | |
1409 | break; | |
1410 | } | |
1411 | ||
1412 | desc->lli.ctlhi = (period_len >> reg_width); | |
1413 | cdesc->desc[i] = desc; | |
1414 | ||
f8122a82 | 1415 | if (last) |
d9de4519 | 1416 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1417 | |
1418 | last = desc; | |
1419 | } | |
1420 | ||
75c61225 | 1421 | /* Let's make a cyclic list */ |
d9de4519 | 1422 | last->lli.llp = cdesc->desc[0]->txd.phys; |
d9de4519 | 1423 | |
2f45d613 AS |
1424 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1425 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1426 | buf_len, period_len, periods); | |
d9de4519 HCE |
1427 | |
1428 | cdesc->periods = periods; | |
1429 | dwc->cdesc = cdesc; | |
1430 | ||
1431 | return cdesc; | |
1432 | ||
1433 | out_err_desc_get: | |
1434 | while (i--) | |
1435 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1436 | out_err_alloc: | |
1437 | kfree(cdesc); | |
1438 | out_err: | |
1439 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1440 | return (struct dw_cyclic_desc *)retval; | |
1441 | } | |
1442 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1443 | ||
1444 | /** | |
1445 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1446 | * @chan: the DMA channel to free | |
1447 | */ | |
1448 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1449 | { | |
1450 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1451 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1452 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1453 | int i; | |
69cea5a0 | 1454 | unsigned long flags; |
d9de4519 | 1455 | |
2e4c364e | 1456 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1457 | |
1458 | if (!cdesc) | |
1459 | return; | |
1460 | ||
69cea5a0 | 1461 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1462 | |
3f936207 | 1463 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1464 | |
d9de4519 HCE |
1465 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1466 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1467 | ||
69cea5a0 | 1468 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1469 | |
1470 | for (i = 0; i < cdesc->periods; i++) | |
1471 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1472 | ||
1473 | kfree(cdesc->desc); | |
1474 | kfree(cdesc); | |
1475 | ||
1476 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1477 | } | |
1478 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1479 | ||
3bfb1d20 HS |
1480 | /*----------------------------------------------------------------------*/ |
1481 | ||
1482 | static void dw_dma_off(struct dw_dma *dw) | |
1483 | { | |
61e183f8 VK |
1484 | int i; |
1485 | ||
3bfb1d20 HS |
1486 | dma_writel(dw, CFG, 0); |
1487 | ||
1488 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1489 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1490 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1491 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1492 | ||
1493 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1494 | cpu_relax(); | |
61e183f8 VK |
1495 | |
1496 | for (i = 0; i < dw->dma.chancnt; i++) | |
1497 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1498 | } |
1499 | ||
9cade1a4 | 1500 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
a9ddb575 | 1501 | { |
3bfb1d20 HS |
1502 | struct dw_dma *dw; |
1503 | size_t size; | |
482c67ea AS |
1504 | bool autocfg; |
1505 | unsigned int dw_params; | |
1506 | unsigned int nr_channels; | |
4a63a8b3 | 1507 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1508 | int err; |
1509 | int i; | |
1510 | ||
9cade1a4 | 1511 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); |
482c67ea AS |
1512 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; |
1513 | ||
9cade1a4 | 1514 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
123de543 AS |
1515 | |
1516 | if (!pdata && autocfg) { | |
9cade1a4 | 1517 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
123de543 AS |
1518 | if (!pdata) |
1519 | return -ENOMEM; | |
1520 | ||
1521 | /* Fill platform data with the default values */ | |
1522 | pdata->is_private = true; | |
1523 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1524 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
1525 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1526 | return -EINVAL; | |
1527 | ||
482c67ea AS |
1528 | if (autocfg) |
1529 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1530 | else | |
1531 | nr_channels = pdata->nr_channels; | |
1532 | ||
1533 | size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan); | |
9cade1a4 | 1534 | dw = devm_kzalloc(chip->dev, size, GFP_KERNEL); |
3bfb1d20 HS |
1535 | if (!dw) |
1536 | return -ENOMEM; | |
1537 | ||
9cade1a4 | 1538 | dw->clk = devm_clk_get(chip->dev, "hclk"); |
dbde5c29 AS |
1539 | if (IS_ERR(dw->clk)) |
1540 | return PTR_ERR(dw->clk); | |
3075528d | 1541 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1542 | |
9cade1a4 AS |
1543 | dw->regs = chip->regs; |
1544 | chip->dw = dw; | |
482c67ea | 1545 | |
75c61225 | 1546 | /* Get hardware configuration parameters */ |
a0982004 | 1547 | if (autocfg) { |
4a63a8b3 AS |
1548 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1549 | ||
a0982004 AS |
1550 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1551 | for (i = 0; i < dw->nr_masters; i++) { | |
1552 | dw->data_width[i] = | |
1553 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1554 | } | |
1555 | } else { | |
1556 | dw->nr_masters = pdata->nr_masters; | |
1557 | memcpy(dw->data_width, pdata->data_width, 4); | |
1558 | } | |
1559 | ||
11f932ec | 1560 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1561 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1562 | |
75c61225 | 1563 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1564 | dw_dma_off(dw); |
1565 | ||
75c61225 | 1566 | /* Disable BLOCK interrupts as well */ |
236b106f AS |
1567 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
1568 | ||
9cade1a4 | 1569 | err = devm_request_irq(chip->dev, chip->irq, dw_dma_interrupt, 0, |
dbde5c29 | 1570 | "dw_dmac", dw); |
3bfb1d20 | 1571 | if (err) |
dbde5c29 | 1572 | return err; |
3bfb1d20 | 1573 | |
75c61225 | 1574 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
9cade1a4 | 1575 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
f8122a82 AS |
1576 | sizeof(struct dw_desc), 4, 0); |
1577 | if (!dw->desc_pool) { | |
9cade1a4 | 1578 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
f8122a82 AS |
1579 | return -ENOMEM; |
1580 | } | |
1581 | ||
3bfb1d20 HS |
1582 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1583 | ||
3bfb1d20 | 1584 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1585 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1586 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1587 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1588 | |
1589 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1590 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1591 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1592 | list_add_tail(&dwc->chan.device_node, | |
1593 | &dw->dma.channels); | |
1594 | else | |
1595 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1596 | |
93317e8e VK |
1597 | /* 7 is highest priority & 0 is lowest. */ |
1598 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1599 | dwc->priority = r; |
93317e8e VK |
1600 | else |
1601 | dwc->priority = i; | |
1602 | ||
3bfb1d20 HS |
1603 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1604 | spin_lock_init(&dwc->lock); | |
1605 | dwc->mask = 1 << i; | |
1606 | ||
1607 | INIT_LIST_HEAD(&dwc->active_list); | |
1608 | INIT_LIST_HEAD(&dwc->queue); | |
1609 | INIT_LIST_HEAD(&dwc->free_list); | |
1610 | ||
1611 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1612 | |
0fdb567f | 1613 | dwc->direction = DMA_TRANS_NONE; |
f776076b | 1614 | dwc->request_line = ~0; |
a0982004 | 1615 | |
75c61225 | 1616 | /* Hardware configuration */ |
fed2574b AS |
1617 | if (autocfg) { |
1618 | unsigned int dwc_params; | |
9cade1a4 | 1619 | void __iomem *addr = chip->regs + r * sizeof(u32); |
fed2574b | 1620 | |
9cade1a4 | 1621 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
fed2574b | 1622 | |
9cade1a4 AS |
1623 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1624 | dwc_params); | |
985a6c7d | 1625 | |
4a63a8b3 AS |
1626 | /* Decode maximum block size for given channel. The |
1627 | * stored 4 bit value represents blocks from 0x00 for 3 | |
1628 | * up to 0x0a for 4095. */ | |
1629 | dwc->block_size = | |
1630 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1631 | dwc->nollp = |
1632 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1633 | } else { | |
4a63a8b3 | 1634 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1635 | |
1636 | /* Check if channel supports multi block transfer */ | |
1637 | channel_writel(dwc, LLP, 0xfffffffc); | |
1638 | dwc->nollp = | |
1639 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1640 | channel_writel(dwc, LLP, 0); | |
1641 | } | |
3bfb1d20 HS |
1642 | } |
1643 | ||
11f932ec | 1644 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1645 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1646 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1647 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1648 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1649 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1650 | ||
3bfb1d20 HS |
1651 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1652 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1653 | if (pdata->is_private) |
1654 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
9cade1a4 | 1655 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1656 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1657 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1658 | ||
1659 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1660 | ||
1661 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1662 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1663 | |
07934481 | 1664 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1665 | dw->dma.device_issue_pending = dwc_issue_pending; |
1666 | ||
1667 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1668 | ||
9cade1a4 | 1669 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
21d43f49 | 1670 | nr_channels); |
3bfb1d20 HS |
1671 | |
1672 | dma_async_device_register(&dw->dma); | |
1673 | ||
1674 | return 0; | |
3bfb1d20 | 1675 | } |
9cade1a4 | 1676 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1677 | |
9cade1a4 | 1678 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1679 | { |
9cade1a4 | 1680 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1681 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 HS |
1682 | |
1683 | dw_dma_off(dw); | |
1684 | dma_async_device_unregister(&dw->dma); | |
1685 | ||
3bfb1d20 HS |
1686 | tasklet_kill(&dw->tasklet); |
1687 | ||
1688 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1689 | chan.device_node) { | |
1690 | list_del(&dwc->chan.device_node); | |
1691 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1692 | } | |
1693 | ||
3bfb1d20 HS |
1694 | return 0; |
1695 | } | |
9cade1a4 | 1696 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1697 | |
9cade1a4 | 1698 | void dw_dma_shutdown(struct dw_dma_chip *chip) |
3bfb1d20 | 1699 | { |
9cade1a4 | 1700 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1701 | |
6168d567 | 1702 | dw_dma_off(dw); |
3075528d | 1703 | clk_disable_unprepare(dw->clk); |
3bfb1d20 | 1704 | } |
9cade1a4 | 1705 | EXPORT_SYMBOL_GPL(dw_dma_shutdown); |
3bfb1d20 | 1706 | |
9cade1a4 AS |
1707 | #ifdef CONFIG_PM_SLEEP |
1708 | ||
1709 | int dw_dma_suspend(struct dw_dma_chip *chip) | |
3bfb1d20 | 1710 | { |
9cade1a4 | 1711 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1712 | |
6168d567 | 1713 | dw_dma_off(dw); |
3075528d | 1714 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1715 | |
3bfb1d20 HS |
1716 | return 0; |
1717 | } | |
9cade1a4 | 1718 | EXPORT_SYMBOL_GPL(dw_dma_suspend); |
3bfb1d20 | 1719 | |
9cade1a4 | 1720 | int dw_dma_resume(struct dw_dma_chip *chip) |
3bfb1d20 | 1721 | { |
9cade1a4 | 1722 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1723 | |
3075528d | 1724 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1725 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1726 | |
3bfb1d20 | 1727 | return 0; |
3bfb1d20 | 1728 | } |
9cade1a4 | 1729 | EXPORT_SYMBOL_GPL(dw_dma_resume); |
3bfb1d20 | 1730 | |
9cade1a4 | 1731 | #endif /* CONFIG_PM_SLEEP */ |
3bfb1d20 HS |
1732 | |
1733 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1734 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1735 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1736 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |