Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/clk.h> |
15 | #include <linux/delay.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
f8122a82 | 18 | #include <linux/dmapool.h> |
7331205a | 19 | #include <linux/err.h> |
3bfb1d20 HS |
20 | #include <linux/init.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/module.h> | |
3bfb1d20 HS |
25 | #include <linux/slab.h> |
26 | ||
61a76496 | 27 | #include "../dmaengine.h" |
9cade1a4 | 28 | #include "internal.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
dd5720b3 AS |
36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
37 | * support descriptor writeback. | |
3bfb1d20 HS |
38 | */ |
39 | ||
78f3c9d2 AS |
40 | static inline bool is_request_line_unset(struct dw_dma_chan *dwc) |
41 | { | |
42 | return dwc->request_line == (typeof(dwc->request_line))~0; | |
43 | } | |
44 | ||
f776076b | 45 | static inline void dwc_set_masters(struct dw_dma_chan *dwc) |
5be10f34 | 46 | { |
f776076b AB |
47 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
48 | struct dw_dma_slave *dws = dwc->chan.private; | |
49 | unsigned char mmax = dw->nr_masters - 1; | |
5be10f34 | 50 | |
78f3c9d2 AS |
51 | if (!is_request_line_unset(dwc)) |
52 | return; | |
53 | ||
54 | dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws)); | |
55 | dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws)); | |
5be10f34 AS |
56 | } |
57 | ||
327e6970 | 58 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
59 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
60 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 61 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 62 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 63 | DW_DMA_MSIZE_16; \ |
495aea4b | 64 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 65 | DW_DMA_MSIZE_16; \ |
f301c062 | 66 | \ |
327e6970 VK |
67 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
68 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
69 | | DWC_CTLL_LLP_D_EN \ |
70 | | DWC_CTLL_LLP_S_EN \ | |
f776076b AB |
71 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
72 | | DWC_CTLL_SMS(_dwc->src_master)); \ | |
f301c062 | 73 | }) |
3bfb1d20 | 74 | |
3bfb1d20 HS |
75 | /* |
76 | * Number of descriptors to allocate for each channel. This should be | |
77 | * made configurable somehow; preferably, the clients (at least the | |
78 | * ones using slave transfers) should be able to give us a hint. | |
79 | */ | |
80 | #define NR_DESCS_PER_CHANNEL 64 | |
81 | ||
82 | /*----------------------------------------------------------------------*/ | |
3bfb1d20 | 83 | |
41d5e59c DW |
84 | static struct device *chan2dev(struct dma_chan *chan) |
85 | { | |
86 | return &chan->dev->device; | |
87 | } | |
41d5e59c | 88 | |
3bfb1d20 HS |
89 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
90 | { | |
e63a47a3 | 91 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
92 | } |
93 | ||
3bfb1d20 HS |
94 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
95 | { | |
96 | struct dw_desc *desc, *_desc; | |
97 | struct dw_desc *ret = NULL; | |
98 | unsigned int i = 0; | |
69cea5a0 | 99 | unsigned long flags; |
3bfb1d20 | 100 | |
69cea5a0 | 101 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 102 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 103 | i++; |
3bfb1d20 HS |
104 | if (async_tx_test_ack(&desc->txd)) { |
105 | list_del(&desc->desc_node); | |
106 | ret = desc; | |
107 | break; | |
108 | } | |
41d5e59c | 109 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 110 | } |
69cea5a0 | 111 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 112 | |
41d5e59c | 113 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
114 | |
115 | return ret; | |
116 | } | |
117 | ||
3bfb1d20 HS |
118 | /* |
119 | * Move a descriptor, including any children, to the free list. | |
120 | * `desc' must not be on any lists. | |
121 | */ | |
122 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
123 | { | |
69cea5a0 VK |
124 | unsigned long flags; |
125 | ||
3bfb1d20 HS |
126 | if (desc) { |
127 | struct dw_desc *child; | |
128 | ||
69cea5a0 | 129 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 130 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 131 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
132 | "moving child desc %p to freelist\n", |
133 | child); | |
e0bd0f8c | 134 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 135 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 136 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 137 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
138 | } |
139 | } | |
140 | ||
61e183f8 VK |
141 | static void dwc_initialize(struct dw_dma_chan *dwc) |
142 | { | |
143 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
144 | struct dw_dma_slave *dws = dwc->chan.private; | |
145 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
146 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
147 | ||
148 | if (dwc->initialized == true) | |
149 | return; | |
150 | ||
f776076b | 151 | if (dws) { |
61e183f8 VK |
152 | /* |
153 | * We need controller-specific data to set up slave | |
154 | * transfers. | |
155 | */ | |
156 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
157 | ||
158 | cfghi = dws->cfg_hi; | |
159 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf | 160 | } else { |
0fdb567f | 161 | if (dwc->direction == DMA_MEM_TO_DEV) |
f776076b | 162 | cfghi = DWC_CFGH_DST_PER(dwc->request_line); |
0fdb567f | 163 | else if (dwc->direction == DMA_DEV_TO_MEM) |
f776076b | 164 | cfghi = DWC_CFGH_SRC_PER(dwc->request_line); |
61e183f8 VK |
165 | } |
166 | ||
167 | channel_writel(dwc, CFG_LO, cfglo); | |
168 | channel_writel(dwc, CFG_HI, cfghi); | |
169 | ||
170 | /* Enable interrupts */ | |
171 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
172 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
173 | ||
174 | dwc->initialized = true; | |
175 | } | |
176 | ||
3bfb1d20 HS |
177 | /*----------------------------------------------------------------------*/ |
178 | ||
4c2d56c5 AS |
179 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
180 | { | |
181 | /* | |
182 | * We can be a lot more clever here, but this should take care | |
183 | * of the most common optimization. | |
184 | */ | |
185 | if (!(v & 7)) | |
186 | return 3; | |
187 | else if (!(v & 3)) | |
188 | return 2; | |
189 | else if (!(v & 1)) | |
190 | return 1; | |
191 | return 0; | |
192 | } | |
193 | ||
f52b36d2 | 194 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
195 | { |
196 | dev_err(chan2dev(&dwc->chan), | |
197 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
198 | channel_readl(dwc, SAR), | |
199 | channel_readl(dwc, DAR), | |
200 | channel_readl(dwc, LLP), | |
201 | channel_readl(dwc, CTL_HI), | |
202 | channel_readl(dwc, CTL_LO)); | |
203 | } | |
204 | ||
3f936207 AS |
205 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
206 | { | |
207 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
208 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
209 | cpu_relax(); | |
210 | } | |
211 | ||
1d455437 AS |
212 | /*----------------------------------------------------------------------*/ |
213 | ||
fed2574b AS |
214 | /* Perform single block transfer */ |
215 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
216 | struct dw_desc *desc) | |
217 | { | |
218 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
219 | u32 ctllo; | |
220 | ||
1d566f11 AS |
221 | /* |
222 | * Software emulation of LLP mode relies on interrupts to continue | |
223 | * multi block transfer. | |
224 | */ | |
fed2574b AS |
225 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; |
226 | ||
227 | channel_writel(dwc, SAR, desc->lli.sar); | |
228 | channel_writel(dwc, DAR, desc->lli.dar); | |
229 | channel_writel(dwc, CTL_LO, ctllo); | |
230 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
231 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
232 | |
233 | /* Move pointer to next descriptor */ | |
234 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
235 | } |
236 | ||
3bfb1d20 HS |
237 | /* Called with dwc->lock held and bh disabled */ |
238 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
239 | { | |
240 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 241 | unsigned long was_soft_llp; |
3bfb1d20 HS |
242 | |
243 | /* ASSERT: channel is idle */ | |
244 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 245 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 246 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 247 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
248 | |
249 | /* The tasklet will hopefully advance the queue... */ | |
250 | return; | |
251 | } | |
252 | ||
fed2574b AS |
253 | if (dwc->nollp) { |
254 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
255 | &dwc->flags); | |
256 | if (was_soft_llp) { | |
257 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 258 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
259 | return; |
260 | } | |
261 | ||
262 | dwc_initialize(dwc); | |
263 | ||
4702d524 | 264 | dwc->residue = first->total_len; |
f5c6a7df | 265 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 266 | |
fdf475fa | 267 | /* Submit first block */ |
fed2574b AS |
268 | dwc_do_single_block(dwc, first); |
269 | ||
270 | return; | |
271 | } | |
272 | ||
61e183f8 VK |
273 | dwc_initialize(dwc); |
274 | ||
3bfb1d20 HS |
275 | channel_writel(dwc, LLP, first->txd.phys); |
276 | channel_writel(dwc, CTL_LO, | |
277 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
278 | channel_writel(dwc, CTL_HI, 0); | |
279 | channel_set_bit(dw, CH_EN, dwc->mask); | |
280 | } | |
281 | ||
e7637c6c AS |
282 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
283 | { | |
cba15617 AS |
284 | struct dw_desc *desc; |
285 | ||
e7637c6c AS |
286 | if (list_empty(&dwc->queue)) |
287 | return; | |
288 | ||
289 | list_move(dwc->queue.next, &dwc->active_list); | |
cba15617 AS |
290 | desc = dwc_first_active(dwc); |
291 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); | |
292 | dwc_dostart(dwc, desc); | |
e7637c6c AS |
293 | } |
294 | ||
3bfb1d20 HS |
295 | /*----------------------------------------------------------------------*/ |
296 | ||
297 | static void | |
5fedefb8 VK |
298 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
299 | bool callback_required) | |
3bfb1d20 | 300 | { |
5fedefb8 VK |
301 | dma_async_tx_callback callback = NULL; |
302 | void *param = NULL; | |
3bfb1d20 | 303 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 304 | struct dw_desc *child; |
69cea5a0 | 305 | unsigned long flags; |
3bfb1d20 | 306 | |
41d5e59c | 307 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 308 | |
69cea5a0 | 309 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 310 | dma_cookie_complete(txd); |
5fedefb8 VK |
311 | if (callback_required) { |
312 | callback = txd->callback; | |
313 | param = txd->callback_param; | |
314 | } | |
3bfb1d20 | 315 | |
e518076e VK |
316 | /* async_tx_ack */ |
317 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
318 | async_tx_ack(&child->txd); | |
319 | async_tx_ack(&desc->txd); | |
320 | ||
e0bd0f8c | 321 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
322 | list_move(&desc->desc_node, &dwc->free_list); |
323 | ||
d38a8c62 | 324 | dma_descriptor_unmap(txd); |
69cea5a0 VK |
325 | spin_unlock_irqrestore(&dwc->lock, flags); |
326 | ||
21e93c1e | 327 | if (callback) |
3bfb1d20 HS |
328 | callback(param); |
329 | } | |
330 | ||
331 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
332 | { | |
333 | struct dw_desc *desc, *_desc; | |
334 | LIST_HEAD(list); | |
69cea5a0 | 335 | unsigned long flags; |
3bfb1d20 | 336 | |
69cea5a0 | 337 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 338 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 339 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
340 | "BUG: XFER bit set, but channel not idle!\n"); |
341 | ||
342 | /* Try to continue after resetting the channel... */ | |
3f936207 | 343 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
344 | } |
345 | ||
346 | /* | |
347 | * Submit queued descriptors ASAP, i.e. before we go through | |
348 | * the completed ones. | |
349 | */ | |
3bfb1d20 | 350 | list_splice_init(&dwc->active_list, &list); |
e7637c6c | 351 | dwc_dostart_first_queued(dwc); |
3bfb1d20 | 352 | |
69cea5a0 VK |
353 | spin_unlock_irqrestore(&dwc->lock, flags); |
354 | ||
3bfb1d20 | 355 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 356 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
357 | } |
358 | ||
4702d524 AS |
359 | /* Returns how many bytes were already received from source */ |
360 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
361 | { | |
362 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
363 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
364 | ||
365 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
366 | } | |
367 | ||
3bfb1d20 HS |
368 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
369 | { | |
370 | dma_addr_t llp; | |
371 | struct dw_desc *desc, *_desc; | |
372 | struct dw_desc *child; | |
373 | u32 status_xfer; | |
69cea5a0 | 374 | unsigned long flags; |
3bfb1d20 | 375 | |
69cea5a0 | 376 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
377 | llp = channel_readl(dwc, LLP); |
378 | status_xfer = dma_readl(dw, RAW.XFER); | |
379 | ||
380 | if (status_xfer & dwc->mask) { | |
381 | /* Everything we've submitted is done */ | |
382 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
383 | |
384 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
385 | struct list_head *head, *active = dwc->tx_node_active; |
386 | ||
387 | /* | |
388 | * We are inside first active descriptor. | |
389 | * Otherwise something is really wrong. | |
390 | */ | |
391 | desc = dwc_first_active(dwc); | |
392 | ||
393 | head = &desc->tx_list; | |
394 | if (active != head) { | |
4702d524 AS |
395 | /* Update desc to reflect last sent one */ |
396 | if (active != head->next) | |
397 | desc = to_dw_desc(active->prev); | |
398 | ||
399 | dwc->residue -= desc->len; | |
400 | ||
fdf475fa | 401 | child = to_dw_desc(active); |
77bcc497 AS |
402 | |
403 | /* Submit next block */ | |
fdf475fa | 404 | dwc_do_single_block(dwc, child); |
77bcc497 | 405 | |
fdf475fa | 406 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
407 | return; |
408 | } | |
fdf475fa | 409 | |
77bcc497 AS |
410 | /* We are done here */ |
411 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
412 | } | |
4702d524 AS |
413 | |
414 | dwc->residue = 0; | |
415 | ||
69cea5a0 VK |
416 | spin_unlock_irqrestore(&dwc->lock, flags); |
417 | ||
3bfb1d20 HS |
418 | dwc_complete_all(dw, dwc); |
419 | return; | |
420 | } | |
421 | ||
69cea5a0 | 422 | if (list_empty(&dwc->active_list)) { |
4702d524 | 423 | dwc->residue = 0; |
69cea5a0 | 424 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 425 | return; |
69cea5a0 | 426 | } |
087809fc | 427 | |
77bcc497 AS |
428 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
429 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 430 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 431 | return; |
69cea5a0 | 432 | } |
087809fc | 433 | |
5a87f0e6 | 434 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
3bfb1d20 HS |
435 | |
436 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 437 | /* Initial residue value */ |
4702d524 AS |
438 | dwc->residue = desc->total_len; |
439 | ||
75c61225 | 440 | /* Check first descriptors addr */ |
69cea5a0 VK |
441 | if (desc->txd.phys == llp) { |
442 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 443 | return; |
69cea5a0 | 444 | } |
84adccfb | 445 | |
75c61225 | 446 | /* Check first descriptors llp */ |
69cea5a0 | 447 | if (desc->lli.llp == llp) { |
3bfb1d20 | 448 | /* This one is currently in progress */ |
4702d524 | 449 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 450 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 451 | return; |
69cea5a0 | 452 | } |
3bfb1d20 | 453 | |
4702d524 AS |
454 | dwc->residue -= desc->len; |
455 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 456 | if (child->lli.llp == llp) { |
3bfb1d20 | 457 | /* Currently in progress */ |
4702d524 | 458 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 459 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 460 | return; |
69cea5a0 | 461 | } |
4702d524 AS |
462 | dwc->residue -= child->len; |
463 | } | |
3bfb1d20 HS |
464 | |
465 | /* | |
466 | * No descriptors so far seem to be in progress, i.e. | |
467 | * this one must be done. | |
468 | */ | |
69cea5a0 | 469 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 470 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 471 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
472 | } |
473 | ||
41d5e59c | 474 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
475 | "BUG: All descriptors done, but channel not idle!\n"); |
476 | ||
477 | /* Try to continue after resetting the channel... */ | |
3f936207 | 478 | dwc_chan_disable(dw, dwc); |
3bfb1d20 | 479 | |
e7637c6c | 480 | dwc_dostart_first_queued(dwc); |
69cea5a0 | 481 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
482 | } |
483 | ||
93aad1bc | 484 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 485 | { |
21d43f49 AS |
486 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
487 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
488 | } |
489 | ||
490 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
491 | { | |
492 | struct dw_desc *bad_desc; | |
493 | struct dw_desc *child; | |
69cea5a0 | 494 | unsigned long flags; |
3bfb1d20 HS |
495 | |
496 | dwc_scan_descriptors(dw, dwc); | |
497 | ||
69cea5a0 VK |
498 | spin_lock_irqsave(&dwc->lock, flags); |
499 | ||
3bfb1d20 HS |
500 | /* |
501 | * The descriptor currently at the head of the active list is | |
502 | * borked. Since we don't have any way to report errors, we'll | |
503 | * just have to scream loudly and try to carry on. | |
504 | */ | |
505 | bad_desc = dwc_first_active(dwc); | |
506 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 507 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
508 | |
509 | /* Clear the error flag and try to restart the controller */ | |
510 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
511 | if (!list_empty(&dwc->active_list)) | |
512 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
513 | ||
514 | /* | |
ba84bd71 | 515 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
516 | * when someone submits a bad physical address in a |
517 | * descriptor, we should consider ourselves lucky that the | |
518 | * controller flagged an error instead of scribbling over | |
519 | * random memory locations. | |
520 | */ | |
ba84bd71 AS |
521 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
522 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 523 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 524 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
525 | dwc_dump_lli(dwc, &child->lli); |
526 | ||
69cea5a0 VK |
527 | spin_unlock_irqrestore(&dwc->lock, flags); |
528 | ||
3bfb1d20 | 529 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 530 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
531 | } |
532 | ||
d9de4519 HCE |
533 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
534 | ||
8004cbb4 | 535 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
536 | { |
537 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
538 | return channel_readl(dwc, SAR); | |
539 | } | |
540 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
541 | ||
8004cbb4 | 542 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
543 | { |
544 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
545 | return channel_readl(dwc, DAR); | |
546 | } | |
547 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
548 | ||
75c61225 | 549 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 550 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
ff7b05f2 | 551 | u32 status_err, u32 status_xfer) |
d9de4519 | 552 | { |
69cea5a0 VK |
553 | unsigned long flags; |
554 | ||
ff7b05f2 | 555 | if (dwc->mask) { |
d9de4519 HCE |
556 | void (*callback)(void *param); |
557 | void *callback_param; | |
558 | ||
559 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
560 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
561 | |
562 | callback = dwc->cdesc->period_callback; | |
563 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
564 | |
565 | if (callback) | |
d9de4519 | 566 | callback(callback_param); |
d9de4519 HCE |
567 | } |
568 | ||
569 | /* | |
570 | * Error and transfer complete are highly unlikely, and will most | |
571 | * likely be due to a configuration error by the user. | |
572 | */ | |
573 | if (unlikely(status_err & dwc->mask) || | |
574 | unlikely(status_xfer & dwc->mask)) { | |
575 | int i; | |
576 | ||
fc61f6b4 AS |
577 | dev_err(chan2dev(&dwc->chan), |
578 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", | |
579 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
580 | |
581 | spin_lock_irqsave(&dwc->lock, flags); | |
582 | ||
1d455437 | 583 | dwc_dump_chan_regs(dwc); |
d9de4519 | 584 | |
3f936207 | 585 | dwc_chan_disable(dw, dwc); |
d9de4519 | 586 | |
75c61225 | 587 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
588 | channel_writel(dwc, LLP, 0); |
589 | channel_writel(dwc, CTL_LO, 0); | |
590 | channel_writel(dwc, CTL_HI, 0); | |
591 | ||
d9de4519 HCE |
592 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
593 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
594 | ||
595 | for (i = 0; i < dwc->cdesc->periods; i++) | |
596 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
597 | |
598 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
599 | } |
600 | } | |
601 | ||
602 | /* ------------------------------------------------------------------------- */ | |
603 | ||
3bfb1d20 HS |
604 | static void dw_dma_tasklet(unsigned long data) |
605 | { | |
606 | struct dw_dma *dw = (struct dw_dma *)data; | |
607 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
608 | u32 status_xfer; |
609 | u32 status_err; | |
610 | int i; | |
611 | ||
7fe7b2f4 | 612 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
613 | status_err = dma_readl(dw, RAW.ERROR); |
614 | ||
2e4c364e | 615 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
616 | |
617 | for (i = 0; i < dw->dma.chancnt; i++) { | |
618 | dwc = &dw->chan[i]; | |
d9de4519 | 619 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 620 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 621 | else if (status_err & (1 << i)) |
3bfb1d20 | 622 | dwc_handle_error(dw, dwc); |
77bcc497 | 623 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 624 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
625 | } |
626 | ||
627 | /* | |
ff7b05f2 | 628 | * Re-enable interrupts. |
3bfb1d20 HS |
629 | */ |
630 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
631 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
632 | } | |
633 | ||
634 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
635 | { | |
636 | struct dw_dma *dw = dev_id; | |
3783cef8 | 637 | u32 status = dma_readl(dw, STATUS_INT); |
3bfb1d20 | 638 | |
3783cef8 AS |
639 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
640 | ||
641 | /* Check if we have any interrupt from the DMAC */ | |
642 | if (!status) | |
643 | return IRQ_NONE; | |
3bfb1d20 HS |
644 | |
645 | /* | |
646 | * Just disable the interrupts. We'll turn them back on in the | |
647 | * softirq handler. | |
648 | */ | |
649 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
650 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
651 | ||
652 | status = dma_readl(dw, STATUS_INT); | |
653 | if (status) { | |
654 | dev_err(dw->dma.dev, | |
655 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
656 | status); | |
657 | ||
658 | /* Try to recover */ | |
659 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
660 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
661 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
662 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
663 | } | |
664 | ||
665 | tasklet_schedule(&dw->tasklet); | |
666 | ||
667 | return IRQ_HANDLED; | |
668 | } | |
669 | ||
670 | /*----------------------------------------------------------------------*/ | |
671 | ||
672 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
673 | { | |
674 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
675 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
676 | dma_cookie_t cookie; | |
69cea5a0 | 677 | unsigned long flags; |
3bfb1d20 | 678 | |
69cea5a0 | 679 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 680 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
681 | |
682 | /* | |
683 | * REVISIT: We should attempt to chain as many descriptors as | |
684 | * possible, perhaps even appending to those already submitted | |
685 | * for DMA. But this is hard to do in a race-free manner. | |
686 | */ | |
3bfb1d20 | 687 | |
dd8ecfca AS |
688 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie); |
689 | list_add_tail(&desc->desc_node, &dwc->queue); | |
3bfb1d20 | 690 | |
69cea5a0 | 691 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
692 | |
693 | return cookie; | |
694 | } | |
695 | ||
696 | static struct dma_async_tx_descriptor * | |
697 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
698 | size_t len, unsigned long flags) | |
699 | { | |
700 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 701 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
702 | struct dw_desc *desc; |
703 | struct dw_desc *first; | |
704 | struct dw_desc *prev; | |
705 | size_t xfer_count; | |
706 | size_t offset; | |
707 | unsigned int src_width; | |
708 | unsigned int dst_width; | |
3d4f8605 | 709 | unsigned int data_width; |
3bfb1d20 HS |
710 | u32 ctllo; |
711 | ||
2f45d613 | 712 | dev_vdbg(chan2dev(chan), |
5a87f0e6 AS |
713 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
714 | &dest, &src, len, flags); | |
3bfb1d20 HS |
715 | |
716 | if (unlikely(!len)) { | |
2e4c364e | 717 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
718 | return NULL; |
719 | } | |
720 | ||
0fdb567f AS |
721 | dwc->direction = DMA_MEM_TO_MEM; |
722 | ||
f776076b AB |
723 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
724 | dw->data_width[dwc->dst_master]); | |
a0982004 | 725 | |
3d4f8605 AS |
726 | src_width = dst_width = min_t(unsigned int, data_width, |
727 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 728 | |
327e6970 | 729 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
730 | | DWC_CTLL_DST_WIDTH(dst_width) |
731 | | DWC_CTLL_SRC_WIDTH(src_width) | |
732 | | DWC_CTLL_DST_INC | |
733 | | DWC_CTLL_SRC_INC | |
734 | | DWC_CTLL_FC_M2M; | |
735 | prev = first = NULL; | |
736 | ||
737 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
738 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 739 | dwc->block_size); |
3bfb1d20 HS |
740 | |
741 | desc = dwc_desc_get(dwc); | |
742 | if (!desc) | |
743 | goto err_desc_get; | |
744 | ||
745 | desc->lli.sar = src + offset; | |
746 | desc->lli.dar = dest + offset; | |
747 | desc->lli.ctllo = ctllo; | |
748 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 749 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
750 | |
751 | if (!first) { | |
752 | first = desc; | |
753 | } else { | |
754 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 755 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 756 | &first->tx_list); |
3bfb1d20 HS |
757 | } |
758 | prev = desc; | |
759 | } | |
760 | ||
3bfb1d20 HS |
761 | if (flags & DMA_PREP_INTERRUPT) |
762 | /* Trigger interrupt after last block */ | |
763 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
764 | ||
765 | prev->lli.llp = 0; | |
3bfb1d20 | 766 | first->txd.flags = flags; |
30d38a32 | 767 | first->total_len = len; |
3bfb1d20 HS |
768 | |
769 | return &first->txd; | |
770 | ||
771 | err_desc_get: | |
772 | dwc_desc_put(dwc, first); | |
773 | return NULL; | |
774 | } | |
775 | ||
776 | static struct dma_async_tx_descriptor * | |
777 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 778 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 779 | unsigned long flags, void *context) |
3bfb1d20 HS |
780 | { |
781 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 782 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 783 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
784 | struct dw_desc *prev; |
785 | struct dw_desc *first; | |
786 | u32 ctllo; | |
787 | dma_addr_t reg; | |
788 | unsigned int reg_width; | |
789 | unsigned int mem_width; | |
a0982004 | 790 | unsigned int data_width; |
3bfb1d20 HS |
791 | unsigned int i; |
792 | struct scatterlist *sg; | |
793 | size_t total_len = 0; | |
794 | ||
2e4c364e | 795 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 796 | |
495aea4b | 797 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
798 | return NULL; |
799 | ||
0fdb567f AS |
800 | dwc->direction = direction; |
801 | ||
3bfb1d20 HS |
802 | prev = first = NULL; |
803 | ||
3bfb1d20 | 804 | switch (direction) { |
db8196df | 805 | case DMA_MEM_TO_DEV: |
327e6970 VK |
806 | reg_width = __fls(sconfig->dst_addr_width); |
807 | reg = sconfig->dst_addr; | |
808 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
809 | | DWC_CTLL_DST_WIDTH(reg_width) |
810 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
811 | | DWC_CTLL_SRC_INC); |
812 | ||
813 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
814 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
815 | ||
f776076b | 816 | data_width = dw->data_width[dwc->src_master]; |
a0982004 | 817 | |
3bfb1d20 HS |
818 | for_each_sg(sgl, sg, sg_len, i) { |
819 | struct dw_desc *desc; | |
69dc14b5 | 820 | u32 len, dlen, mem; |
3bfb1d20 | 821 | |
cbb796cc | 822 | mem = sg_dma_address(sg); |
69dc14b5 | 823 | len = sg_dma_len(sg); |
6bc711f6 | 824 | |
a0982004 AS |
825 | mem_width = min_t(unsigned int, |
826 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 827 | |
69dc14b5 | 828 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
829 | desc = dwc_desc_get(dwc); |
830 | if (!desc) { | |
41d5e59c | 831 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
832 | "not enough descriptors available\n"); |
833 | goto err_desc_get; | |
834 | } | |
835 | ||
3bfb1d20 HS |
836 | desc->lli.sar = mem; |
837 | desc->lli.dar = reg; | |
838 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
839 | if ((len >> mem_width) > dwc->block_size) { |
840 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
841 | mem += dlen; |
842 | len -= dlen; | |
843 | } else { | |
844 | dlen = len; | |
845 | len = 0; | |
846 | } | |
847 | ||
848 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 849 | desc->len = dlen; |
3bfb1d20 HS |
850 | |
851 | if (!first) { | |
852 | first = desc; | |
853 | } else { | |
854 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 855 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 856 | &first->tx_list); |
3bfb1d20 HS |
857 | } |
858 | prev = desc; | |
69dc14b5 VK |
859 | total_len += dlen; |
860 | ||
861 | if (len) | |
862 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
863 | } |
864 | break; | |
db8196df | 865 | case DMA_DEV_TO_MEM: |
327e6970 VK |
866 | reg_width = __fls(sconfig->src_addr_width); |
867 | reg = sconfig->src_addr; | |
868 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
869 | | DWC_CTLL_SRC_WIDTH(reg_width) |
870 | | DWC_CTLL_DST_INC | |
327e6970 VK |
871 | | DWC_CTLL_SRC_FIX); |
872 | ||
873 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
874 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 875 | |
f776076b | 876 | data_width = dw->data_width[dwc->dst_master]; |
a0982004 | 877 | |
3bfb1d20 HS |
878 | for_each_sg(sgl, sg, sg_len, i) { |
879 | struct dw_desc *desc; | |
69dc14b5 | 880 | u32 len, dlen, mem; |
3bfb1d20 | 881 | |
cbb796cc | 882 | mem = sg_dma_address(sg); |
3bfb1d20 | 883 | len = sg_dma_len(sg); |
6bc711f6 | 884 | |
a0982004 AS |
885 | mem_width = min_t(unsigned int, |
886 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 887 | |
69dc14b5 VK |
888 | slave_sg_fromdev_fill_desc: |
889 | desc = dwc_desc_get(dwc); | |
890 | if (!desc) { | |
891 | dev_err(chan2dev(chan), | |
892 | "not enough descriptors available\n"); | |
893 | goto err_desc_get; | |
894 | } | |
895 | ||
3bfb1d20 HS |
896 | desc->lli.sar = reg; |
897 | desc->lli.dar = mem; | |
898 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
899 | if ((len >> reg_width) > dwc->block_size) { |
900 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
901 | mem += dlen; |
902 | len -= dlen; | |
903 | } else { | |
904 | dlen = len; | |
905 | len = 0; | |
906 | } | |
907 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 908 | desc->len = dlen; |
3bfb1d20 HS |
909 | |
910 | if (!first) { | |
911 | first = desc; | |
912 | } else { | |
913 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 914 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 915 | &first->tx_list); |
3bfb1d20 HS |
916 | } |
917 | prev = desc; | |
69dc14b5 VK |
918 | total_len += dlen; |
919 | ||
920 | if (len) | |
921 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
922 | } |
923 | break; | |
924 | default: | |
925 | return NULL; | |
926 | } | |
927 | ||
928 | if (flags & DMA_PREP_INTERRUPT) | |
929 | /* Trigger interrupt after last block */ | |
930 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
931 | ||
932 | prev->lli.llp = 0; | |
30d38a32 | 933 | first->total_len = total_len; |
3bfb1d20 HS |
934 | |
935 | return &first->txd; | |
936 | ||
937 | err_desc_get: | |
938 | dwc_desc_put(dwc, first); | |
939 | return NULL; | |
940 | } | |
941 | ||
327e6970 VK |
942 | /* |
943 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
944 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
945 | * | |
946 | * NOTE: burst size 2 is not supported by controller. | |
947 | * | |
948 | * This can be done by finding least significant bit set: n & (n - 1) | |
949 | */ | |
950 | static inline void convert_burst(u32 *maxburst) | |
951 | { | |
952 | if (*maxburst > 1) | |
953 | *maxburst = fls(*maxburst) - 2; | |
954 | else | |
955 | *maxburst = 0; | |
956 | } | |
957 | ||
958 | static int | |
959 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
960 | { | |
961 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
962 | ||
495aea4b AS |
963 | /* Check if chan will be configured for slave transfers */ |
964 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
965 | return -EINVAL; |
966 | ||
967 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 968 | dwc->direction = sconfig->direction; |
327e6970 | 969 | |
f776076b | 970 | /* Take the request line from slave_id member */ |
78f3c9d2 | 971 | if (is_request_line_unset(dwc)) |
f776076b AB |
972 | dwc->request_line = sconfig->slave_id; |
973 | ||
327e6970 VK |
974 | convert_burst(&dwc->dma_sconfig.src_maxburst); |
975 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
21fe3c52 AS |
980 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
981 | { | |
982 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
123b69ab | 983 | unsigned int count = 20; /* timeout iterations */ |
21fe3c52 AS |
984 | |
985 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
123b69ab AS |
986 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
987 | udelay(2); | |
21fe3c52 AS |
988 | |
989 | dwc->paused = true; | |
990 | } | |
991 | ||
992 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
993 | { | |
994 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
995 | ||
996 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
997 | ||
998 | dwc->paused = false; | |
999 | } | |
1000 | ||
05827630 LW |
1001 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1002 | unsigned long arg) | |
3bfb1d20 HS |
1003 | { |
1004 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1005 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1006 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1007 | unsigned long flags; |
3bfb1d20 HS |
1008 | LIST_HEAD(list); |
1009 | ||
a7c57cf7 LW |
1010 | if (cmd == DMA_PAUSE) { |
1011 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1012 | |
21fe3c52 | 1013 | dwc_chan_pause(dwc); |
3bfb1d20 | 1014 | |
a7c57cf7 LW |
1015 | spin_unlock_irqrestore(&dwc->lock, flags); |
1016 | } else if (cmd == DMA_RESUME) { | |
1017 | if (!dwc->paused) | |
1018 | return 0; | |
3bfb1d20 | 1019 | |
a7c57cf7 | 1020 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1021 | |
21fe3c52 | 1022 | dwc_chan_resume(dwc); |
3bfb1d20 | 1023 | |
a7c57cf7 LW |
1024 | spin_unlock_irqrestore(&dwc->lock, flags); |
1025 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1026 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1027 | |
fed2574b AS |
1028 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1029 | ||
3f936207 | 1030 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1031 | |
a5dbff11 | 1032 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1033 | |
1034 | /* active_list entries will end up before queued entries */ | |
1035 | list_splice_init(&dwc->queue, &list); | |
1036 | list_splice_init(&dwc->active_list, &list); | |
1037 | ||
1038 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1039 | ||
1040 | /* Flush all pending and queued descriptors */ | |
1041 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1042 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1043 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1044 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1045 | } else { | |
a7c57cf7 | 1046 | return -ENXIO; |
327e6970 | 1047 | } |
c3635c78 LW |
1048 | |
1049 | return 0; | |
3bfb1d20 HS |
1050 | } |
1051 | ||
4702d524 AS |
1052 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1053 | { | |
1054 | unsigned long flags; | |
1055 | u32 residue; | |
1056 | ||
1057 | spin_lock_irqsave(&dwc->lock, flags); | |
1058 | ||
1059 | residue = dwc->residue; | |
1060 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1061 | residue -= dwc_get_sent(dwc); | |
1062 | ||
1063 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1064 | return residue; | |
1065 | } | |
1066 | ||
3bfb1d20 | 1067 | static enum dma_status |
07934481 LW |
1068 | dwc_tx_status(struct dma_chan *chan, |
1069 | dma_cookie_t cookie, | |
1070 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1071 | { |
1072 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1073 | enum dma_status ret; |
3bfb1d20 | 1074 | |
96a2af41 | 1075 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1076 | if (ret == DMA_COMPLETE) |
12381dc0 | 1077 | return ret; |
3bfb1d20 | 1078 | |
12381dc0 | 1079 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 1080 | |
12381dc0 | 1081 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1082 | if (ret != DMA_COMPLETE) |
4702d524 | 1083 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1084 | |
effd5cf6 | 1085 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 1086 | return DMA_PAUSED; |
3bfb1d20 HS |
1087 | |
1088 | return ret; | |
1089 | } | |
1090 | ||
1091 | static void dwc_issue_pending(struct dma_chan *chan) | |
1092 | { | |
1093 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
dd8ecfca | 1094 | unsigned long flags; |
3bfb1d20 | 1095 | |
dd8ecfca AS |
1096 | spin_lock_irqsave(&dwc->lock, flags); |
1097 | if (list_empty(&dwc->active_list)) | |
1098 | dwc_dostart_first_queued(dwc); | |
1099 | spin_unlock_irqrestore(&dwc->lock, flags); | |
3bfb1d20 HS |
1100 | } |
1101 | ||
aa1e6f1a | 1102 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1103 | { |
1104 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1105 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1106 | struct dw_desc *desc; | |
3bfb1d20 | 1107 | int i; |
69cea5a0 | 1108 | unsigned long flags; |
3bfb1d20 | 1109 | |
2e4c364e | 1110 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1111 | |
3bfb1d20 HS |
1112 | /* ASSERT: channel is idle */ |
1113 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1114 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1115 | return -EIO; |
1116 | } | |
1117 | ||
d3ee98cd | 1118 | dma_cookie_init(chan); |
3bfb1d20 | 1119 | |
3bfb1d20 HS |
1120 | /* |
1121 | * NOTE: some controllers may have additional features that we | |
1122 | * need to initialize here, like "scatter-gather" (which | |
1123 | * doesn't mean what you think it means), and status writeback. | |
1124 | */ | |
1125 | ||
f776076b AB |
1126 | dwc_set_masters(dwc); |
1127 | ||
69cea5a0 | 1128 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1129 | i = dwc->descs_allocated; |
1130 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1131 | dma_addr_t phys; |
1132 | ||
69cea5a0 | 1133 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1134 | |
f8122a82 | 1135 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1136 | if (!desc) |
1137 | goto err_desc_alloc; | |
3bfb1d20 | 1138 | |
f8122a82 | 1139 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1140 | |
e0bd0f8c | 1141 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1142 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1143 | desc->txd.tx_submit = dwc_tx_submit; | |
1144 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1145 | desc->txd.phys = phys; |
cbd65312 | 1146 | |
3bfb1d20 HS |
1147 | dwc_desc_put(dwc, desc); |
1148 | ||
69cea5a0 | 1149 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1150 | i = ++dwc->descs_allocated; |
1151 | } | |
1152 | ||
69cea5a0 | 1153 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1154 | |
2e4c364e | 1155 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1156 | |
cbd65312 AS |
1157 | return i; |
1158 | ||
1159 | err_desc_alloc: | |
cbd65312 AS |
1160 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1161 | ||
3bfb1d20 HS |
1162 | return i; |
1163 | } | |
1164 | ||
1165 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1166 | { | |
1167 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1168 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1169 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1170 | unsigned long flags; |
3bfb1d20 HS |
1171 | LIST_HEAD(list); |
1172 | ||
2e4c364e | 1173 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1174 | dwc->descs_allocated); |
1175 | ||
1176 | /* ASSERT: channel is idle */ | |
1177 | BUG_ON(!list_empty(&dwc->active_list)); | |
1178 | BUG_ON(!list_empty(&dwc->queue)); | |
1179 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1180 | ||
69cea5a0 | 1181 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1182 | list_splice_init(&dwc->free_list, &list); |
1183 | dwc->descs_allocated = 0; | |
61e183f8 | 1184 | dwc->initialized = false; |
f776076b | 1185 | dwc->request_line = ~0; |
3bfb1d20 HS |
1186 | |
1187 | /* Disable interrupts */ | |
1188 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1189 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1190 | ||
69cea5a0 | 1191 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1192 | |
1193 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1194 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1195 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1196 | } |
1197 | ||
2e4c364e | 1198 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1199 | } |
1200 | ||
d9de4519 HCE |
1201 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1202 | ||
1203 | /** | |
1204 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1205 | * @chan: the DMA channel to start | |
1206 | * | |
1207 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1208 | * -errno on failure. | |
1209 | */ | |
1210 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1211 | { | |
1212 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1213 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1214 | unsigned long flags; |
d9de4519 HCE |
1215 | |
1216 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1217 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1218 | return -ENODEV; | |
1219 | } | |
1220 | ||
69cea5a0 | 1221 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1222 | |
75c61225 | 1223 | /* Assert channel is idle */ |
d9de4519 HCE |
1224 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
1225 | dev_err(chan2dev(&dwc->chan), | |
1226 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1227 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1228 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1229 | return -EBUSY; |
1230 | } | |
1231 | ||
d9de4519 HCE |
1232 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1233 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1234 | ||
75c61225 | 1235 | /* Setup DMAC channel registers */ |
d9de4519 HCE |
1236 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); |
1237 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1238 | channel_writel(dwc, CTL_HI, 0); | |
1239 | ||
1240 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1241 | ||
69cea5a0 | 1242 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1243 | |
1244 | return 0; | |
1245 | } | |
1246 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1247 | ||
1248 | /** | |
1249 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1250 | * @chan: the DMA channel to stop | |
1251 | * | |
1252 | * Must be called with soft interrupts disabled. | |
1253 | */ | |
1254 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1255 | { | |
1256 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1257 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1258 | unsigned long flags; |
d9de4519 | 1259 | |
69cea5a0 | 1260 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1261 | |
3f936207 | 1262 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1263 | |
69cea5a0 | 1264 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1265 | } |
1266 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1267 | ||
1268 | /** | |
1269 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1270 | * @chan: the DMA channel to prepare | |
1271 | * @buf_addr: physical DMA address where the buffer starts | |
1272 | * @buf_len: total number of bytes for the entire buffer | |
1273 | * @period_len: number of bytes for each period | |
1274 | * @direction: transfer direction, to or from device | |
1275 | * | |
1276 | * Must be called before trying to start the transfer. Returns a valid struct | |
1277 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1278 | */ | |
1279 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1280 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1281 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1282 | { |
1283 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1284 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1285 | struct dw_cyclic_desc *cdesc; |
1286 | struct dw_cyclic_desc *retval = NULL; | |
1287 | struct dw_desc *desc; | |
1288 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1289 | unsigned long was_cyclic; |
1290 | unsigned int reg_width; | |
1291 | unsigned int periods; | |
1292 | unsigned int i; | |
69cea5a0 | 1293 | unsigned long flags; |
d9de4519 | 1294 | |
69cea5a0 | 1295 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1296 | if (dwc->nollp) { |
1297 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1298 | dev_dbg(chan2dev(&dwc->chan), | |
1299 | "channel doesn't support LLP transfers\n"); | |
1300 | return ERR_PTR(-EINVAL); | |
1301 | } | |
1302 | ||
d9de4519 | 1303 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1304 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1305 | dev_dbg(chan2dev(&dwc->chan), |
1306 | "queue and/or active list are not empty\n"); | |
1307 | return ERR_PTR(-EBUSY); | |
1308 | } | |
1309 | ||
1310 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1311 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1312 | if (was_cyclic) { |
1313 | dev_dbg(chan2dev(&dwc->chan), | |
1314 | "channel already prepared for cyclic DMA\n"); | |
1315 | return ERR_PTR(-EBUSY); | |
1316 | } | |
1317 | ||
1318 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1319 | |
f44b92f4 AS |
1320 | if (unlikely(!is_slave_direction(direction))) |
1321 | goto out_err; | |
1322 | ||
0fdb567f AS |
1323 | dwc->direction = direction; |
1324 | ||
327e6970 VK |
1325 | if (direction == DMA_MEM_TO_DEV) |
1326 | reg_width = __ffs(sconfig->dst_addr_width); | |
1327 | else | |
1328 | reg_width = __ffs(sconfig->src_addr_width); | |
1329 | ||
d9de4519 HCE |
1330 | periods = buf_len / period_len; |
1331 | ||
1332 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1333 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1334 | goto out_err; |
1335 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1336 | goto out_err; | |
1337 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1338 | goto out_err; | |
d9de4519 HCE |
1339 | |
1340 | retval = ERR_PTR(-ENOMEM); | |
1341 | ||
1342 | if (periods > NR_DESCS_PER_CHANNEL) | |
1343 | goto out_err; | |
1344 | ||
1345 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1346 | if (!cdesc) | |
1347 | goto out_err; | |
1348 | ||
1349 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1350 | if (!cdesc->desc) | |
1351 | goto out_err_alloc; | |
1352 | ||
1353 | for (i = 0; i < periods; i++) { | |
1354 | desc = dwc_desc_get(dwc); | |
1355 | if (!desc) | |
1356 | goto out_err_desc_get; | |
1357 | ||
1358 | switch (direction) { | |
db8196df | 1359 | case DMA_MEM_TO_DEV: |
327e6970 | 1360 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1361 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1362 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1363 | | DWC_CTLL_DST_WIDTH(reg_width) |
1364 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1365 | | DWC_CTLL_DST_FIX | |
1366 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1367 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1368 | |
1369 | desc->lli.ctllo |= sconfig->device_fc ? | |
1370 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1371 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1372 | ||
d9de4519 | 1373 | break; |
db8196df | 1374 | case DMA_DEV_TO_MEM: |
d9de4519 | 1375 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1376 | desc->lli.sar = sconfig->src_addr; |
1377 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1378 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1379 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1380 | | DWC_CTLL_DST_INC | |
1381 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1382 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1383 | |
1384 | desc->lli.ctllo |= sconfig->device_fc ? | |
1385 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1386 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1387 | ||
d9de4519 HCE |
1388 | break; |
1389 | default: | |
1390 | break; | |
1391 | } | |
1392 | ||
1393 | desc->lli.ctlhi = (period_len >> reg_width); | |
1394 | cdesc->desc[i] = desc; | |
1395 | ||
f8122a82 | 1396 | if (last) |
d9de4519 | 1397 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1398 | |
1399 | last = desc; | |
1400 | } | |
1401 | ||
75c61225 | 1402 | /* Let's make a cyclic list */ |
d9de4519 | 1403 | last->lli.llp = cdesc->desc[0]->txd.phys; |
d9de4519 | 1404 | |
5a87f0e6 AS |
1405 | dev_dbg(chan2dev(&dwc->chan), |
1406 | "cyclic prepared buf %pad len %zu period %zu periods %d\n", | |
1407 | &buf_addr, buf_len, period_len, periods); | |
d9de4519 HCE |
1408 | |
1409 | cdesc->periods = periods; | |
1410 | dwc->cdesc = cdesc; | |
1411 | ||
1412 | return cdesc; | |
1413 | ||
1414 | out_err_desc_get: | |
1415 | while (i--) | |
1416 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1417 | out_err_alloc: | |
1418 | kfree(cdesc); | |
1419 | out_err: | |
1420 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1421 | return (struct dw_cyclic_desc *)retval; | |
1422 | } | |
1423 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1424 | ||
1425 | /** | |
1426 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1427 | * @chan: the DMA channel to free | |
1428 | */ | |
1429 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1430 | { | |
1431 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1432 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1433 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1434 | int i; | |
69cea5a0 | 1435 | unsigned long flags; |
d9de4519 | 1436 | |
2e4c364e | 1437 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1438 | |
1439 | if (!cdesc) | |
1440 | return; | |
1441 | ||
69cea5a0 | 1442 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1443 | |
3f936207 | 1444 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1445 | |
d9de4519 HCE |
1446 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1447 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1448 | ||
69cea5a0 | 1449 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1450 | |
1451 | for (i = 0; i < cdesc->periods; i++) | |
1452 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1453 | ||
1454 | kfree(cdesc->desc); | |
1455 | kfree(cdesc); | |
1456 | ||
1457 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1458 | } | |
1459 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1460 | ||
3bfb1d20 HS |
1461 | /*----------------------------------------------------------------------*/ |
1462 | ||
1463 | static void dw_dma_off(struct dw_dma *dw) | |
1464 | { | |
61e183f8 VK |
1465 | int i; |
1466 | ||
3bfb1d20 HS |
1467 | dma_writel(dw, CFG, 0); |
1468 | ||
1469 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1470 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1471 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1472 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1473 | ||
1474 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1475 | cpu_relax(); | |
61e183f8 VK |
1476 | |
1477 | for (i = 0; i < dw->dma.chancnt; i++) | |
1478 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1479 | } |
1480 | ||
9cade1a4 | 1481 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
a9ddb575 | 1482 | { |
3bfb1d20 | 1483 | struct dw_dma *dw; |
482c67ea AS |
1484 | bool autocfg; |
1485 | unsigned int dw_params; | |
1486 | unsigned int nr_channels; | |
4a63a8b3 | 1487 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1488 | int err; |
1489 | int i; | |
1490 | ||
000871ce AS |
1491 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
1492 | if (!dw) | |
1493 | return -ENOMEM; | |
1494 | ||
1495 | dw->regs = chip->regs; | |
1496 | chip->dw = dw; | |
1497 | ||
d2f78e95 AS |
1498 | dw->clk = devm_clk_get(chip->dev, "hclk"); |
1499 | if (IS_ERR(dw->clk)) | |
1500 | return PTR_ERR(dw->clk); | |
8be4f523 AS |
1501 | err = clk_prepare_enable(dw->clk); |
1502 | if (err) | |
1503 | return err; | |
d2f78e95 | 1504 | |
9cade1a4 | 1505 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); |
482c67ea AS |
1506 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; |
1507 | ||
9cade1a4 | 1508 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
123de543 AS |
1509 | |
1510 | if (!pdata && autocfg) { | |
9cade1a4 | 1511 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
8be4f523 AS |
1512 | if (!pdata) { |
1513 | err = -ENOMEM; | |
1514 | goto err_pdata; | |
1515 | } | |
123de543 AS |
1516 | |
1517 | /* Fill platform data with the default values */ | |
1518 | pdata->is_private = true; | |
1519 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1520 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
8be4f523 AS |
1521 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
1522 | err = -EINVAL; | |
1523 | goto err_pdata; | |
1524 | } | |
123de543 | 1525 | |
482c67ea AS |
1526 | if (autocfg) |
1527 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1528 | else | |
1529 | nr_channels = pdata->nr_channels; | |
1530 | ||
000871ce AS |
1531 | dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan), |
1532 | GFP_KERNEL); | |
8be4f523 AS |
1533 | if (!dw->chan) { |
1534 | err = -ENOMEM; | |
1535 | goto err_pdata; | |
1536 | } | |
3bfb1d20 | 1537 | |
75c61225 | 1538 | /* Get hardware configuration parameters */ |
a0982004 | 1539 | if (autocfg) { |
4a63a8b3 AS |
1540 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1541 | ||
a0982004 AS |
1542 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1543 | for (i = 0; i < dw->nr_masters; i++) { | |
1544 | dw->data_width[i] = | |
1545 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1546 | } | |
1547 | } else { | |
1548 | dw->nr_masters = pdata->nr_masters; | |
1549 | memcpy(dw->data_width, pdata->data_width, 4); | |
1550 | } | |
1551 | ||
11f932ec | 1552 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1553 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1554 | |
75c61225 | 1555 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1556 | dw_dma_off(dw); |
1557 | ||
75c61225 | 1558 | /* Disable BLOCK interrupts as well */ |
236b106f AS |
1559 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
1560 | ||
75c61225 | 1561 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
9cade1a4 | 1562 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
f8122a82 AS |
1563 | sizeof(struct dw_desc), 4, 0); |
1564 | if (!dw->desc_pool) { | |
9cade1a4 | 1565 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
8be4f523 AS |
1566 | err = -ENOMEM; |
1567 | goto err_pdata; | |
f8122a82 AS |
1568 | } |
1569 | ||
3bfb1d20 HS |
1570 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1571 | ||
97977f75 AS |
1572 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
1573 | "dw_dmac", dw); | |
1574 | if (err) | |
8be4f523 | 1575 | goto err_pdata; |
97977f75 | 1576 | |
3bfb1d20 | 1577 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1578 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1579 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1580 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1581 | |
1582 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1583 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1584 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1585 | list_add_tail(&dwc->chan.device_node, | |
1586 | &dw->dma.channels); | |
1587 | else | |
1588 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1589 | |
93317e8e VK |
1590 | /* 7 is highest priority & 0 is lowest. */ |
1591 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1592 | dwc->priority = r; |
93317e8e VK |
1593 | else |
1594 | dwc->priority = i; | |
1595 | ||
3bfb1d20 HS |
1596 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1597 | spin_lock_init(&dwc->lock); | |
1598 | dwc->mask = 1 << i; | |
1599 | ||
1600 | INIT_LIST_HEAD(&dwc->active_list); | |
1601 | INIT_LIST_HEAD(&dwc->queue); | |
1602 | INIT_LIST_HEAD(&dwc->free_list); | |
1603 | ||
1604 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1605 | |
0fdb567f | 1606 | dwc->direction = DMA_TRANS_NONE; |
f776076b | 1607 | dwc->request_line = ~0; |
a0982004 | 1608 | |
75c61225 | 1609 | /* Hardware configuration */ |
fed2574b AS |
1610 | if (autocfg) { |
1611 | unsigned int dwc_params; | |
9cade1a4 | 1612 | void __iomem *addr = chip->regs + r * sizeof(u32); |
fed2574b | 1613 | |
9cade1a4 | 1614 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
fed2574b | 1615 | |
9cade1a4 AS |
1616 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1617 | dwc_params); | |
985a6c7d | 1618 | |
1d566f11 AS |
1619 | /* |
1620 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1621 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1622 | * up to 0x0a for 4095. |
1623 | */ | |
4a63a8b3 AS |
1624 | dwc->block_size = |
1625 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1626 | dwc->nollp = |
1627 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1628 | } else { | |
4a63a8b3 | 1629 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1630 | |
1631 | /* Check if channel supports multi block transfer */ | |
1632 | channel_writel(dwc, LLP, 0xfffffffc); | |
1633 | dwc->nollp = | |
1634 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1635 | channel_writel(dwc, LLP, 0); | |
1636 | } | |
3bfb1d20 HS |
1637 | } |
1638 | ||
11f932ec | 1639 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1640 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1641 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1642 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1643 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1644 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1645 | ||
3bfb1d20 HS |
1646 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1647 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1648 | if (pdata->is_private) |
1649 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
9cade1a4 | 1650 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1651 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1652 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1653 | ||
1654 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1655 | ||
1656 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1657 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1658 | |
07934481 | 1659 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1660 | dw->dma.device_issue_pending = dwc_issue_pending; |
1661 | ||
1662 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1663 | ||
1222934e AS |
1664 | err = dma_async_device_register(&dw->dma); |
1665 | if (err) | |
1666 | goto err_dma_register; | |
1667 | ||
9cade1a4 | 1668 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
21d43f49 | 1669 | nr_channels); |
3bfb1d20 | 1670 | |
3bfb1d20 | 1671 | return 0; |
8be4f523 | 1672 | |
1222934e AS |
1673 | err_dma_register: |
1674 | free_irq(chip->irq, dw); | |
8be4f523 AS |
1675 | err_pdata: |
1676 | clk_disable_unprepare(dw->clk); | |
1677 | return err; | |
3bfb1d20 | 1678 | } |
9cade1a4 | 1679 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1680 | |
9cade1a4 | 1681 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1682 | { |
9cade1a4 | 1683 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1684 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 HS |
1685 | |
1686 | dw_dma_off(dw); | |
1687 | dma_async_device_unregister(&dw->dma); | |
1688 | ||
97977f75 | 1689 | free_irq(chip->irq, dw); |
3bfb1d20 HS |
1690 | tasklet_kill(&dw->tasklet); |
1691 | ||
1692 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1693 | chan.device_node) { | |
1694 | list_del(&dwc->chan.device_node); | |
1695 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1696 | } | |
1697 | ||
8be4f523 AS |
1698 | clk_disable_unprepare(dw->clk); |
1699 | ||
3bfb1d20 HS |
1700 | return 0; |
1701 | } | |
9cade1a4 | 1702 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1703 | |
9cade1a4 | 1704 | void dw_dma_shutdown(struct dw_dma_chip *chip) |
3bfb1d20 | 1705 | { |
9cade1a4 | 1706 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1707 | |
6168d567 | 1708 | dw_dma_off(dw); |
3075528d | 1709 | clk_disable_unprepare(dw->clk); |
3bfb1d20 | 1710 | } |
9cade1a4 | 1711 | EXPORT_SYMBOL_GPL(dw_dma_shutdown); |
3bfb1d20 | 1712 | |
9cade1a4 AS |
1713 | #ifdef CONFIG_PM_SLEEP |
1714 | ||
1715 | int dw_dma_suspend(struct dw_dma_chip *chip) | |
3bfb1d20 | 1716 | { |
9cade1a4 | 1717 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1718 | |
6168d567 | 1719 | dw_dma_off(dw); |
3075528d | 1720 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1721 | |
3bfb1d20 HS |
1722 | return 0; |
1723 | } | |
9cade1a4 | 1724 | EXPORT_SYMBOL_GPL(dw_dma_suspend); |
3bfb1d20 | 1725 | |
9cade1a4 | 1726 | int dw_dma_resume(struct dw_dma_chip *chip) |
3bfb1d20 | 1727 | { |
9cade1a4 | 1728 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1729 | |
3075528d | 1730 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1731 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1732 | |
3bfb1d20 | 1733 | return 0; |
3bfb1d20 | 1734 | } |
9cade1a4 | 1735 | EXPORT_SYMBOL_GPL(dw_dma_resume); |
3bfb1d20 | 1736 | |
9cade1a4 | 1737 | #endif /* CONFIG_PM_SLEEP */ |
3bfb1d20 HS |
1738 | |
1739 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1740 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1741 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1742 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |