[linux-2.6-block.git] / drivers / dma / Kconfig

#
# DMA engine configuration
#

menuconfig DMADEVICES
	bool "DMA Engine support"
	depends on !HIGHMEM64G && HAS_DMA
	help
	  DMA engines can do asynchronous data transfers without
	  involving the host CPU.  Currently, this framework can be
	  used to offload memory copies in the network stack and
	  RAID operations in the MD driver.  This menu only presents
	  DMA Device drivers supported by the configured arch, it may
	  be empty in some cases.

if DMADEVICES

comment "DMA Devices"

config INTEL_IOATDMA
	tristate "Intel I/OAT DMA support"
	depends on PCI && X86
	select DMA_ENGINE
	select DCA
	help
	  Enable support for the Intel(R) I/OAT DMA engine present
	  in recent Intel Xeon chipsets.

	  Say Y here if you have such a chipset.

	  If unsure, say N.

config INTEL_IOP_ADMA
	tristate "Intel IOP ADMA support"
	depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
	select DMA_ENGINE
	help
	  Enable support for the Intel(R) IOP Series RAID engines.

config DW_DMAC
	tristate "Synopsys DesignWare AHB DMA support"
	depends on AVR32
	select DMA_ENGINE
	default y if CPU_AT32AP7000
	help
	  Support the Synopsys DesignWare AHB DMA controller.  This
	  can be integrated in chips such as the Atmel AT32ap7000.

config FSL_DMA
	tristate "Freescale Elo and Elo Plus DMA support"
	depends on FSL_SOC
	select DMA_ENGINE
	---help---
	  Enable support for the Freescale Elo and Elo Plus DMA controllers.
	  The Elo is the DMA controller on some 82xx and 83xx parts, and the
	  Elo Plus is the DMA controller on 85xx and 86xx parts.

config MV_XOR
	bool "Marvell XOR engine support"
	depends on PLAT_ORION
	select DMA_ENGINE
	---help---
	  Enable support for the Marvell XOR engine.

config MX3_IPU
	bool "MX3x Image Processing Unit support"
	depends on ARCH_MX3
	select DMA_ENGINE
	default y
	help
	  If you plan to use the Image Processing unit in the i.MX3x, say
	  Y here. If unsure, select Y.

config MX3_IPU_IRQS
	int "Number of dynamically mapped interrupts for IPU"
	depends on MX3_IPU
	range 2 137
	default 4
	help
	  Out of 137 interrupt sources on i.MX31 IPU only very few are used.
	  To avoid bloating the irq_desc[] array we allocate a sufficient
	  number of IRQ slots and map them dynamically to specific sources.

config DMA_ENGINE
	bool

comment "DMA Clients"
	depends on DMA_ENGINE

config NET_DMA
	bool "Network: TCP receive copy offload"
	depends on DMA_ENGINE && NET
	default (INTEL_IOATDMA || FSL_DMA)
	help
	  This enables the use of DMA engines in the network stack to
	  offload receive copy-to-user operations, freeing CPU cycles.

	  Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
	  say N.

config ASYNC_TX_DMA
	bool "Async_tx: Offload support for the async_tx api"
	depends on DMA_ENGINE
	help
	  This allows the async_tx api to take advantage of offload engines for
	  memcpy, memset, xor, and raid6 p+q operations.  If your platform has
	  a dma engine that can perform raid operations and you have enabled
	  MD_RAID456 say Y.

	  If unsure, say N.

config DMATEST
	tristate "DMA Test client"
	depends on DMA_ENGINE
	help
	  Simple DMA test client. Say N unless you're debugging a
	  DMA Device driver.

endif
Commit	Line	Data
c13c8260 CL	1	#
	2	# DMA engine configuration
	3	#
	4
2ed6dc34	5	menuconfig DMADEVICES
6d4f5879	6	bool "DMA Engine support"
9c402f4e	7	depends on !HIGHMEM64G && HAS_DMA
2ed6dc34	8	help
6d4f5879 HS	9	DMA engines can do asynchronous data transfers without
	10	involving the host CPU. Currently, this framework can be
	11	used to offload memory copies in the network stack and
9c402f4e DW	12	RAID operations in the MD driver. This menu only presents
	13	DMA Device drivers supported by the configured arch, it may
	14	be empty in some cases.
2ed6dc34 SN	15
	16	if DMADEVICES
	17
	18	comment "DMA Devices"
	19
	20	config INTEL_IOATDMA
	21	tristate "Intel I/OAT DMA support"
	22	depends on PCI && X86
	23	select DMA_ENGINE
	24	select DCA
	25	help
	26	Enable support for the Intel(R) I/OAT DMA engine present
	27	in recent Intel Xeon chipsets.
	28
	29	Say Y here if you have such a chipset.
	30
	31	If unsure, say N.
	32
	33	config INTEL_IOP_ADMA
	34	tristate "Intel IOP ADMA support"
	35	depends on ARCH_IOP32X \|\| ARCH_IOP33X \|\| ARCH_IOP13XX
2ed6dc34 SN	36	select DMA_ENGINE
	37	help
	38	Enable support for the Intel(R) IOP Series RAID engines.
c13c8260	39
3bfb1d20 HS	40	config DW_DMAC
	41	tristate "Synopsys DesignWare AHB DMA support"
	42	depends on AVR32
	43	select DMA_ENGINE
	44	default y if CPU_AT32AP7000
	45	help
	46	Support the Synopsys DesignWare AHB DMA controller. This
	47	can be integrated in chips such as the Atmel AT32ap7000.
	48
173acc7c	49	config FSL_DMA
77cd62e8 TT	50	tristate "Freescale Elo and Elo Plus DMA support"
77cd62e8 TT	51	depends on FSL_SOC
173acc7c ZW	52	select DMA_ENGINE
173acc7c ZW	53	---help---
77cd62e8 TT	54	Enable support for the Freescale Elo and Elo Plus DMA controllers.
	55	The Elo is the DMA controller on some 82xx and 83xx parts, and the
	56	Elo Plus is the DMA controller on 85xx and 86xx parts.
173acc7c	57
ff7b0479 SB	58	config MV_XOR
	59	bool "Marvell XOR engine support"
	60	depends on PLAT_ORION
ff7b0479 SB	61	select DMA_ENGINE
	62	---help---
	63	Enable support for the Marvell XOR engine.
	64
5296b56d GL	65	config MX3_IPU
	66	bool "MX3x Image Processing Unit support"
	67	depends on ARCH_MX3
	68	select DMA_ENGINE
	69	default y
	70	help
	71	If you plan to use the Image Processing unit in the i.MX3x, say
	72	Y here. If unsure, select Y.
	73
	74	config MX3_IPU_IRQS
	75	int "Number of dynamically mapped interrupts for IPU"
	76	depends on MX3_IPU
	77	range 2 137
	78	default 4
	79	help
	80	Out of 137 interrupt sources on i.MX31 IPU only very few are used.
	81	To avoid bloating the irq_desc[] array we allocate a sufficient
	82	number of IRQ slots and map them dynamically to specific sources.
	83
c13c8260	84	config DMA_ENGINE
2ed6dc34	85	bool
c13c8260	86
db217334	87	comment "DMA Clients"
2ed6dc34	88	depends on DMA_ENGINE
db217334 CL	89
	90	config NET_DMA
	91	bool "Network: TCP receive copy offload"
	92	depends on DMA_ENGINE && NET
9c402f4e	93	default (INTEL_IOATDMA \|\| FSL_DMA)
2ed6dc34	94	help
db217334 CL	95	This enables the use of DMA engines in the network stack to
db217334 CL	96	offload receive copy-to-user operations, freeing CPU cycles.
9c402f4e DW	97
	98	Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
	99	say N.
db217334	100
729b5d1b DW	101	config ASYNC_TX_DMA
	102	bool "Async_tx: Offload support for the async_tx api"
	103	depends on DMA_ENGINE
	104	help
	105	This allows the async_tx api to take advantage of offload engines for
	106	memcpy, memset, xor, and raid6 p+q operations. If your platform has
	107	a dma engine that can perform raid operations and you have enabled
	108	MD_RAID456 say Y.
	109
	110	If unsure, say N.
	111
4a776f0a HS	112	config DMATEST
	113	tristate "DMA Test client"
	114	depends on DMA_ENGINE
	115	help
	116	Simple DMA test client. Say N unless you're debugging a
	117	DMA Device driver.
	118
2ed6dc34	119	endif